Log in    Register
ChipFind

Industry news

Agilent Tech. Parasitic Reduction Tool Enhances RFIC Simulation Speed, Capacity While Preserving Accuracy

Parasitic Reduction Tool Enhances RFIC Simulation Speed, Capacity While Preserving AccuracyAgilent's GoldenGate is the leading RFIC Simulator platform delivering high capacity and unique analysis for full chip verification and design for yield. Developed for the specific needs of RFIC/Wireless designers, GoldenGate is fully integrated into the Cadence Analog Design Environment (ADE).

Agilent Technologies today announced Jivaro-for-GoldenGate, a parasitic model order-reduction tool designed for use with the company's GoldenGate RF simulator software. Jivaro-for-GoldenGate is expected to enhance RFIC simulation speed and capacity with negligible loss in accuracy.

"Efficiently handling circuit simulation with an increasingly large number of extracted parasitics has pushed the envelope of simulator technology," said Paul Colestock, RFIC marketing manager with Agilent's EEsof EDA division. "Unlike their digital counterparts, RFIC designers need to simulate circuits with self and mutual inductance in addition to parasitic resistance and capacitance. This creates a simulation-capacity requirement that is either unsupportable with current hardware or requires unreasonable simulation times. Combining GoldenGate with Jivaro-for-GoldenGate solves this problem."

Jivaro-for-GoldenGate is designed in cooperation with edXact, a company that provides high-precision, high-performance technology for backend physical verification. edXact's Jivaro-A netlist-reduction engine is the core of this new RFIC design software.

Tailored to the challenging demands of large, complex RFIC designs, Agilent's GoldenGate is the leading RFIC simulation and analysis solution featuring unique harmonic-balance capabilities. Combining Agilent's GoldenGate simulator with Jivaro-for-GoldenGate increases simulation capacity, reduces memory requirements and boosts simulation speed when simulating large parasitic-dominated post-layout netlists.

"Jivaro-for-GoldenGate fills the gap between circuit extraction and circuit simulation created by an increased number of parasitic components (resistance,capacitance, self and mutual inductance) required to model the physical reality of circuit interconnects, substrates or packages," said Mathias Silvant, edXact president. "Jivaro-for-GoldenGate delivers simulation speed and capacity with negligible loss of accuracy by optimizing the parasitic models against the need to keep the accuracy of the netlist predictable at a very high level."

Source: Agilent  •  More info: http://www.agilent.com/about/n...08182.html
Table of contents

© 2006 — 2020 ChipFind Ltd.
Contact phone, e-mail, ICQ
RegisterAdvertising