DG528/529
Vishay Siliconix
Document Number: 70068
P-32167--Rev. C, 15-Nov-93
www.vishay.com
S
FaxBack 408-970-5600
5-1
Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers
FEATURES
BENEFITS
APPLICATIONS
D
Low r
DS(on)
: 270
W
D
44-V Power Supply Rating
D
On-Board Address Latches
D
Break-Before-Make
D
Low Leakage--I
D(on)
: 30 pA
D
Improved System Accuracy
D
Microporcessor Bus Compatible
D
Easily Interfaced
D
Reduced Crosstalk
D
Data Acquisition Systems
D
Automatic Test Equipment
D
Avionics and Military Systems
D
Medical Instrumentation
DESCRIPTION
The DG528 is an 8-channel single-ended analog multiplexer
designed to connect one of eight inputs to a common output as
determined by a 3-bit binary address (A
0
, A
1
, A
2
). DG529, a
4-channel dual analog multiplexer, is designed to connect one
of four differential inputs to a common differential output as
determined by its 2-bit binary address (A
0
, A
1
) logic.
These analog multiplexers have on-chip address and control
latches to simplify design in microprocessor based
applications. Break-before-make switching action protects
against momentary shorting of the input signals. The
DG528/529 are built on the improved PLUS-40 CMOS
process. A buried layer prevents latchup.
The on chip TTL-compatible address latches simplify digital
interface design and reduce board space in data acquisition
systems, process controls, avionics, and ATE.
FUNCTIONAL BLOCK DIAGRAMS AND PIN CONFIGURATIONS
WR
D
RS
S
8
A
0
A
1
EN
A
2
V
GND
S
1
V+
S
2
S
5
S
3
S
6
S
4
S
7
Dual-In-Line
Decoders/Drivers
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
Top View
9
10
Latches
EN
A
2
V
GND
S
1
V+
S
2
S
5
S
3
S
6
PLCC
14
15
16
17
18
8
7
6
5
4
1
2
3
19
20
11
10
9
13
12
Top View
4
D
NC
8
7
A
WR
NC
RS
A
Latches
Decoders/Drivers
0
1
S
S
S
WR
D
a
RS
D
b
A
0
A
1
EN
GND
V
V+
S
1a
S
1b
S
2a
S
2b
S
3a
S
3b
S
4a
S
4b
Dual-In-Line
Decoders/Drivers
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
Top View
9
10
Latches
DG528
DG528
DG529
DG528/529
Vishay Siliconix
www.vishay.com
S
FaxBack 408-970-5600
5-2
Document Number: 70068
P-32167--Rev. C, 15-Nov-93
TRUTH TABLES AND ORDERING INFORMATION
TRUTH TABLE
DG528
8-Channel Single-Ended Multiplexer
A
2
A
1
A
0
EN
WR
RS
On Switch
Latching
X
X
X
X
1
Maintains previous
switch condition
Reset
X
X
X
X
X
0
None (latches cleared)
Transparent Operation
X
X
X
0
0
1
None
0
0
0
1
0
1
1
0
0
1
1
0
1
2
0
1
0
1
0
1
3
0
1
1
1
0
1
4
1
0
0
1
0
1
5
1
0
1
1
0
1
6
1
1
0
1
0
1
7
1
1
1
1
0
1
8
TRUTH TABLE
DG529
Differential 4-Channel Multiplexer
A
0
EN
WR
RS
On Switch
Latching
X
X
1
Maintains previous
switch condition
Reset
X
X
X
0
None (latches cleared)
Transparent Operation
X
0
0
1
None
0
1
0
1
1
1
1
0
1
2
0
1
0
1
3
1
1
0
1
4
Logic "0" = V
AL
v
0.8 V
Logic "1" = V
AH
w
2.4 V
X = Don't Care
ORDERING INFORMATION
DG528
Temp Range
Package
Part Number
0 to 70
_
C
18-Pin Plastic DIP
DG528CJ
0 to 70
_
C
20-Pin PLCC
DG528DN
25 to 85
_
C
18 Pi C DIP
DG528BK
55
125 C
18-Pin CerDIP
DG528AK
55 to 125
_
C
18-Pin CerDIP
DG528AK/883
5962-8768901VA
ORDERING INFORMATION
DG529
Temp Range
Package
Part Number
0 to 70
_
C
18-Pin Plastic DIP
DG529CJ
25 to 85
_
C
18-Pin CerDIP
DG529BK
55 to 125
_
C
18-Pin CerDIP
DG529AK/883
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to V
V+
44 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND
25 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputs
a
, V
S
, V
D
(V) 2 V to (V+) +2 V or
. . . . . . . . . . . . . . . . . . . . . . . .
30 mA, whichever occurs first
Current (Any Terminal Except S or D)
30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Current, S or D
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max)
40 mA
. . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature
(AK, BK Suffix)
65 to 150
_
C
. . . . . . . . . . . . . .
(CJ, DN Suffix)
65 to 125
_
C
. . . . . . . . . . . . . .
Power Dissipation (Package)
b
18-Pin Plastic DIP
c
470 mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-Pin CerDIP
d
900 mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin PLCC
e
800 mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a.
Signals on S
X
, D
X
or IN
X
exceeding V+ or V will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b.
All leads soldered or welded to PC board.
c.
Derate 6.3 mW/
_
C above 75
_
C.
d.
Derate 1.2 mW/
_
C above 75
_
C.
e.
Derate 10 mW/
_
C above 75
_
C.
DG528/529
Vishay Siliconix
Document Number: 70068
P-32167--Rev. C, 15-Nov-93
www.vishay.com
S
FaxBack 408-970-5600
5-3
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V = 15 V, WR = 0
A Suffix
55 to 125
_
C
B, C, D
Suffix
40 to 85
_
C
Parameter
Symbol
V+ = 15 V, V = 15 V, WR = 0
RS = 2.4 V, V
IN
= 2.4 V, 0.8
m
F
f
Temp
b
Typ
c
Min
d
Max
d
Min
d
Max
d
Unit
Analog Switch
Analog Signal Range
e
V
ANALOG
Full
15
15
15
15
V
Drain-Source
On-Resistance
r
DS(on)
V
D
= 10 V, I
S
= 200
m
A
Room
Full
270
400
500
450
550
W
Greatest Change in r
DS(on)
Between Channels
f
D
r
DS(on)
10 V < V
S
< 10 V
Room
6
%
Source Off
Leakage Current
I
S(off)
V
EN
= 0 V, V
S
=
"
10 V
V
D
=
#
10 V
Room
Full
"
0.005
1
50
1
50
5
50
5
50
A
Drain Off
L
k
C
t
I
D(off)
V
EN
= 0 V
V
D
=
"
10 V
DG528
Room
Full
"
0.015
10
200
10
200
20
200
20
200
A
Leakage Current
I
D(off)
V
D
=
"
10 V
V
S
=
#
10 V
DG529
Room
Full
"
0.008
10
100
10
100
20
100
20
100
nA
Drain On
L
k
C
t
I
D(on)
V
S
= V
D
=
10 V
V
2 4 V
DG528
Room
Full
"
0.03
10
200
10
200
20
200
20
200
Leakage Current
I
D(on)
S
D
V
EN
= 2.4 V
DG529
Room
Full
"
0.015
10
100
10
100
20
100
20
100
Digital Control
Logic Input Current
I
AH
V
A
= 2.4 V
Room
Hot
0.002
10
30
10
30
A
Input Voltage High
I
AH
V
A
= 15 V
Room
Hot
0.006
10
30
10
30
m
A
Logic Input Current
Input Voltage Low
I
AL
V
EN
= 0 V, 2.4 V, V
A
= 0 V
RS = 0 V, WR = 0 V
Room
Hot
0.002
10
30
10
30
Dynamic Characteristics
Transition Time
t
TRANS
See Figure 5
Room
0.6
1
Break-Before-Make Interval
t
OPEN
See Figure 4
Room
0.2
EN and WR
Turn-On Time
t
ON(EN, WR)
See Figures 6 and 7
Room
1
1.5
m
s
EN and WR
Turn-Off Time
t
OFF(EN, WR)
See Figures 6 and 8
Room
0.4
1
Charge Injection
Q
V
S
= 0 V, R
y
= 0
W
C
L
= 10
m
F
Room
4
pC
Off Isolation
OIRR
V
EN
= 0 V, R
L
= 1 k
W
C
L
= 15 pF
V
S
= 7 V
RMS,
f = 500 kHz
Room
68
dB
Logic Input Capacitance
C
in
f = 1 MHz
Room
2.5
F
Source Off Capacitance
C
S(off)
V
EN
= 0 V, V
S
= 0 V
f = 140 kHz
Room
5
pF
Drain Off Capacitance
C
D(off)
V
EN
= 0 V
V
D
= 0 V
DG528
Room
25
pF
Drain Off Capacitance
C
D(off)
V
D
= 0 V
f = 140 kHz
DG529
Room
12
Minimum Input Timing Requirements
Write Pulse Width
t
W
Full
300
300
A
X
, EN Setup Time
t
S
Full
180
180
ns
A
X
, EN Hold Time
t
H
Full
30
30
ns
Reset Pulse Width
t
RS
V
S
= 5 V, See Figure 3
Full
500
500
DG528/529
Vishay Siliconix
www.vishay.com
S
FaxBack 408-970-5600
5-4
Document Number: 70068
P-32167--Rev. C, 15-Nov-93
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V = 15 V, WR = 0
A Suffix
55 to 125
_
C
B, C, D
Suffix
40 to 85
_
C
Parameter
Symbol
V+ = 15 V, V = 15 V, WR = 0
RS = 2.4 V, V
IN
= 2.4 V, 0.8
m
F
f
Temp
b
Typ
c
Min
d
Max
d
Min
d
Max
d
Unit
Power Supplies
Positive Supply Current
I+
V
EN
= 0 V, V
A
= 0
Room
2.5
2.5
mA
Negative Supply Current
I
V
EN
= 0 V, V
A
= 0
Room
1.5
1.5
mA
Notes:
a.
Refer to PROCESS OPTION FLOWCHART.
b.
Room = 25
_
C, Full = as determined by the operating temperature suffix.
c.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d.
The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e.
Guaranteed by design, not subject to production test.
f.
V
IN
= input voltage to perform proper function.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
20
15
10
5
0
5
10
15
20
500
400
300
200
100
r
DS(on)
vs. V
D
and Power Supply
V
D
Drain Voltage (V)
"
7.5 V
r DS(on)
Drain-Source On-Resistance (
"
10 V
"
15 V
"
20 V
T
A
= 25
_
C
15
10
5
0
5
10
15
0
20
40
60
Leakage Currents vs. Analog Voltage
I
D(off)
I
D(on)
I
S(off)
"
15 V Supplies
T
A
= 25
_
C
(pA)
I
, I
SD
V
ANALOG
Analog Voltage (V)
2.5
2.0
1.5
1.0
0.5
0
Input Switching Threshold vs.
V+ and V Supply Voltages
V+, V Positive and Negative Supplies (V)
T
A
= 25
_
C
(V)
T
V
0
"
5
"
10
"
15
"
20
Supply Currents vs. Toggle Frequency
I+, I (mA)
1 k
10 k
100 k
1 M
4
3
2
1
0
I+
I
Toggle Frequency (Hz)
)
W
DG528/529
Vishay Siliconix
Document Number: 70068
P-32167--Rev. C, 15-Nov-93
www.vishay.com
S
FaxBack 408-970-5600
5-5
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
FIGURE 1.
V+
V+
V+
Latches
EN
CLK
RESET
A
X
WR
RS
V
REF
D
O
D
n
Q
O
Q
n
Level
Shift
V+
V
V
V
V
GND
V
V+
D
V
V+
Decode
S
1
V
V+
V
V+
V+
S
n
DETAILED DESCRIPTION
The internal structure of the DG528/DG529 includes a 5-V
logic interface with input protection circuitry followed by a latch,
level shifter, decoder and finally the switch constructed with
parallel n- and p-channel MOSFETs (see Figure 1).
The logic interface circuit compares the TTL input signal
against a TTL threshold reference voltage. The output of the
comparator feeds the data input of a D type latch. The level
sensitive D latch continuously places the D
X
input signal on the
Q
X
output when the WR input is low, resulting in transparent
latch operation. As soon as WR returns high, the latches hold
the data last present on the D
X
input, subject to the minimum
input timing requirements.
Following the latches the Q
X
signals are level shifted and
decoded to provide proper drive levels for the CMOS switches.
This level shifting insures full on/off switch operation for any
analog signal present between the V+ and V supply rails.
The EN pin is used to enable the address latches during the
WR pulse. It can be hard-wired to the logic supply or to V+ if one
of the channels will always be used (except during a reset) or
it can be tied to address decoding circuitry for memory mapped
operation. The RS pin is used as a master reset. All latches are
cleared regardless of the state of any other latch or control line.
The WR pin is used to transfer the state of the address control
lines to their latches, except during a reset or when EN is low
(see Truth Tables).
FIGURE 2.
FIGURE 3.
3 V
0
3 V
0
50%
80%
80%
EN
3 V
0
0
50%
t
W
t
S
t
H
t
RS
t
OFF (RS)
WR
RS
A
0
, A
1
, (A
2
)
80%
V
O
Switch
Output
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