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FEATURES

APPLICATIONS

DESCRIPTION

SIMPLIFIED SCHEMATIC

VIN

ENA

GND

VSENSE

BOOT

TPS5430

VIN

VOUT

100

0.5

1.5

2.5

3.5

ficiency

O !

Output Current ! A

V = 12 V,

= 5 V,

fs = 500 kHz

Efficiency vs Output Current

TPS5430

SLVS632 JANUARY 2006

5.5-V to 36-V, 3-A STEP-DOWN SWIFTTM CONVERTER

Consumer: Set-top Box, DVD, LCD Displays

Wide Input Voltage Range: 5.5 V to 36 V

Industrial and Car Audio Power Supplies

Up to 3-A Continuous (4-A Peak) Output

Battery Chargers, High Power LED Supply

Current

12V/24V Distributed Power Systems

High Efficiency up to 95% Enabled by 110-m

Integrated MOSFET Switch

Wide Output Voltage Range: Adjustable Down
to 1.22 V with 1.5% Initial Accuracy

As a member of the SWIFTTM family of DC/DC
regulators, the TPS5430 is a high-output-current

Internal Compensation Minimizes External

PWM converter that integrates a low resistance high

Parts Count

side N-channel MOSFET. Included on the substrate

Fixed 500 kHz Switching Frequency for Small

with the listed features are a high performance

Filter Size

voltage error amplifier that provides tight voltage
regulation accuracy under transient conditions; an

Improved Line Regulation and Transient

under-voltage-lockout circuit to prevent start-up until

Response by Input Voltage Feed Forward

the input voltage reaches 5.5V; an internally set

System Protected by Over Current Limiting

slow-start circuit to limit inrush currents; and a voltage

and Thermal Shutdown

feed-forward

circuit

improve

the

transient

40

C to 125

C Operating Junction

response. Other features include an active high

Temperature Range

enable,

over

current

protection

and

thermal

shutdown. To reduce design complexity and external

Available in Small Thermally Enhanced 8-Pin

component count, the TPS5430 feedback loop is

SOIC PowerPADTM Package

internally compensated.

For SWIFT Documentation, Application Notes

The TPS5430 device is available in a thermally

and Design Software, See the TI Website at

enhanced, easy to use 8-pin SOIC PowerPADTM

www.ti.com/swift

package. TI provides evaluation modules and the
SWIFTTM Designer software tool to aid in quickly
achieving high-performance power supply designs to
meet aggressive equipment development cycles.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

(1) (2)

RECOMMENDED OPERATING CONDITIONS

TPS5430

SLVS632 JANUARY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

OUTPUT VOLTAGE

PACKAGE

PART NUMBER

C to 125

Adjustable to 1.22 V

Thermally Enhanced SOIC (DDA)

(1)

TPS5430DDA

(1)

The DDA package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS5430DDAR). See applications section
of data sheet for PowerPADTM drawing and layout information.

over operating free-air temperature range (unless otherwise noted)

(1) (2)

VALUE

UNIT

VIN

0.3 to 38

ENA

0.3 to 7

VSENSE

0.3 to 3

Input voltage range

BOOT

0.3 to 48

BOOT-PH

PH (steady-state)

0.6 to 38

PH (transient < 10 ns)

1.2

Source current

Internally Limited

Leakage current

Operating virtual junction temperature range

40 to 125

STG

Storage temperature

65 to 150

Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds

300

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal.

PACKAGE

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

8 Pin DDA (2-layer board with solder)

(3)

C/W

8 Pin DDA (4-layer board with solder)

(4)

C/W

(1)

Maximum power dissipation may be limited by overcurrent protection.

(2)

Power rating at a specific ambient temperature T

should be determined with a junction temperature of 125

C. This is the point where

distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125

C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more

information.

(3)

Test board conditions:
a. 3 in x 3 in, 2 layers, thickness: 0.062 inch.
b. 2 oz. copper traces located on the top and bottom of the PCB.
c. 6 thermal vias in the PowerPAD area under the device package.

(4)

Test board conditions:
a. 3 in x 3 in, 4 layers, thickness: 0.062 inch.
b. 2 oz. copper traces located on the top and bottom of the PCB.
c. 2 oz. copper ground planes on the 2 internal layers.
d. 6 thermal vias in the PowerPAD area under the device package.

MIN

NOM

MAX

UNIT

VIN

Input voltage range

5.5

Operating junction temperature

125

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ELECTRICAL CHARACTERISTICS

TPS5430

SLVS632 JANUARY 2006

= 40

C to 125

C, VIN = 5.5 V to 36.0 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN PIN)

VIN

Input voltage range

5.5

VSENSE = 2 V, Not switching, PH pin

4.4

open

Quiescent current

Shutdown, ENA = 0 V

UNDER VOLTAGE LOCK OUT (UVLO)

Start threshold voltage, UVLO

5.3

5.5

Hysteresis voltage, UVLO

330

VOLTAGE REFERENCE

= 25

1.202

1.221

1.239

Voltage reference accuracy

Io = 0 A 3 A

1.196

1.221

1.245

OSCILLATOR

Internally set free-running frequency

400

500

600

kHz

Minimum controllable on time

150

200

Maximum duty cycle

ENABLE (ENA PIN)

Start threshold voltage, ENA

1.3

Stop threshold voltage, ENA

0.5

Hysteresis voltage, ENA

450

Internal slow-start time (0~100%)

6.6

CURRENT LIMIT

Current limit

4.0

5.0

6.0

Current limit hiccup time

THERMAL SHUTDOWN

Thermal shutdown trip point

135

162

Thermal shutdown hysteresis

OUTPUT MOSFET

VIN = 5.5 V

150

DS-ON

High side power MOSFET switch

VIN = 10 V 36 V

110

230

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PIN ASSIGNMENTS

PowerPAD

(Pin 9)

BOOT

VSENSE

VIN

GND

ENA

DDA PACKAGE

(TOP VIEW)

TPS5430

SLVS632 JANUARY 2006

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME

NO.

BOOT

Boost capacitor for the high-side FET gate driver. Connect 0.01

F low ESR capacitor from BOOT pin to PH pin.

2, 3

Not connected internally.

VSENSE

Feedback voltage for the regulator. Connect to output voltage divider.

ENA

On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.

GND

Ground. Connect to PowerPAD.

Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramic

VIN

capacitor.

Source of the high side power MOSFET. Connected to external inductor and diode.

PowerPAD

GND pin must be connected to the exposed pad for proper operation.

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TYPICAL CHARACTERISTICS

460

470

480

490

500

510

520

530

!50

!25

100

125

f
!

Oscillator F

requency

kHz

T ! Junction Temperature ! C

2.5

2.75

3.25

3.5

!50

!25

100

125

! Junction Temperature !

I Q

Quiescent Current

1.210

1.215

1.220

1.225

1.230

-50

-25

100

125

T - Junction Temperature - C

- V

oltage Reference - V

= 125 C

= 27 C

= !40 C

ENA = 0 V

!Input V oltage !V

I SD

Shutdown Current

7.5

8.5

!50

!25

100

125

! Junction Temperature !

Internal Slow Start T

ime

100

110

120

130

140

150

160

170

180

!50

!25

100

125

On R

esistance

r DS(on)

!Junction Temperature

= 12 V

TPS5430

SLVS632 JANUARY 2006

OSCILLATOR FREQUENCY

NON-SWITCHING QUIESCENT CURRENT

JUNCTION TEMPERATURE

Figure 1.

Figure 2.

SHUTDOWN QUIESCENT CURRENT

VOLTAGE REFERENCE

INPUT VOLTAGE

JUNCTION TEMPERATURE

Figure 3.

Figure 4.

ON RESISTANCE

INTERNAL SLOW START TIME

JUNCTION TEMPERATURE

Figure 5.

Figure 6.

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APPLICATION INFORMATION

FUNCTIONAL BLOCK DIAGRAM

VIN

UVLO

ENABLE

Thermal

Protection

Reference

Overcurrent

Gate Drive

Oscillator

Ramp

Generator

VREF

ENA

GND

SHDN

BOOT

SHDN

VIN

SHDN

HICCUP

SHDN

Feed Forward

BOOT

POWERPAD

VIN

VOUT

TPS5430

1.221 V Bandgap

Slow Start

Boot

Regulator

Error

Amplifier

Gain = 25

PWM

Comparator

Protection

Gate
Driver

Control

VSENSE

DETAILED DESCRIPTION

Oscillator Frequency

Voltage Reference

Enable (ENA) and Internal Slow Start

TPS5430

SLVS632 JANUARY 2006

The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.

The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.

The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled
below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin
to ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode. The
quiescent current of the TPS5430 in shutdown mode is typically 18

The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow start circuit is used to ramp up the reference voltage from 0 V to its
final value linearly. The internal slow start time is 8ms typically.

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Undervoltage Lockout (UVLO)

Boost Capacitor (BOOT)

Output Feedback (VSENSE) and Internal Compensation

Voltage Feed Forward

Feed Forward Gain

)

VIN

Ramp

(1)

Pulse-Width-Modulation (PWM) Control

Overcurrent Protection

TPS5430

SLVS632 JANUARY 2006

APPLICATION INFORMATION (continued)

The TPS5430 incorporates an under voltage lockout circuit to keep the device disabled when VIN (the input
voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive until VIN
exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, device start-up
begins. The device operates until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the
UVLO comparator is 330 mV.

Connect a 0.01

F low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the

gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.

The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.

The TPS5430 implements internal compensation to simplify the regulator design. Since the TPS5430 uses
voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. Refer to Internal Compensation Network in the applications
section for more details.

The internal voltage feed forward provides a constant DC power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e.

The typical feed forward gain of TPS5430 is 25.

The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback
voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and
compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the
PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle.
Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.

Overcurrent protection is implemented by sensing the drain-to-source voltage across the high-side MOSFET.
The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.

Once overcurrent indicator is set true, overcurrent protection is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle current
limiting.

If the sensed current continues to increase during cycle-by-cycle current limiting, the hiccup mode overcurrent
protection will be triggered instead of cycle-by-cycle current limiting. During hiccup mode overcurrent protection,
the voltage reference is grounded and the high-side MOSFET is turned off for the hiccup time. Once the hiccup
time duration is complete, the regulator restarts under control of the slow start circuit.

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Thermal Shutdown

PCB Layout

TPS5430

SLVS632 JANUARY 2006

APPLICATION INFORMATION (continued)

The TPS5430 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction
temperature drops 14

C below the thermal shutdown trip point.

Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the TPS5430 ground pin. The best way to do this
is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass
capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 10 uF ceramic
with a X5R or X7R dielectric.

There should be a ground area on the top layer directly underneath the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by
connecting it to the ground area under the device as shown below.

The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located very close to the PH pin and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to
minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as
shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.

Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout and GND as small as is practical.

Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace
may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a
trace under the output capacitor is not desired.

If the grounding scheme shown is utilized, use a via connection to a different layer to route to the ENA pin.

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0.080

0.026

0.098

0.1

0.050

0.110

0.220

0.050

0.040

0.013 DIA 4 PL

All dimensions in inches

Application Circuits

PwPd

10.8 - 19.8 V

GND

VSNS

VIN

ENA

BOOT

220

B340A

0.01

VOUT

5 V

3.24 kW

10 kW

VIN

TPS5430DDA

Design Procedure

TPS5430

SLVS632 JANUARY 2006

APPLICATION INFORMATION (continued)

Figure 10. TPS5430 Land Pattern

Figure 11

shows the schematic for a typical TPS5430 application. The TPS5430 can provide up to 3-A output

current at a nominal output voltage of 5.0 V. For proper thermal performance the exposed PowerPAD
underneath the device must be soldered down to the printed circuit board.

Figure 11. Application Circuit, 12-V to 5.0-V

The following design procedure can be used to select component values for the TPS5430. Alternately, the
SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.

To begin the design process a few parameters must be decided upon. The designer needs to know the following:

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OUT(MAX)

0.25

CBULK

)

OUT(MAX)

ESR

MAX

(2)

CIN

OUT(MAX)

(3)

TPS5430

SLVS632 JANUARY 2006

APPLICATION INFORMATION (continued)

Input voltage range

Output voltage

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

Design Parameters

For this design example, use the following as the input parameters:

DESIGN PARAMETER

(1)

EXAMPLE VALUE

Input voltage range

10.8 V to 19.8 V

Output voltage

5.0 V

Input ripple voltage

300 mV

Output ripple voltage

30 mV

Output current rating

3 A

Operating frequency

500 kHz

(1)

As an additional constraint, the design is set up to be small size and low component height.

Switching Frequency

The switching frequency for the TPS5430 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.

Input Capacitors

The TPS5430 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The recommended value for the decoupling capacitor, C1, is 10

F. A high quality ceramic type X5R or X7R is

required. For some applications a smaller value decoupling capacitor may be used, so long as the input voltage
and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,
including ripple.

This input ripple voltage can be approximated by

Equation 2

Where I

OUT(MAX)

is the maximum load current, f

is the switching frequency, C

is the input capacitor value and

ESR

MAX

is the maximum series resistance of the input capacitor.

The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by

Equation 3

In this case the input ripple voltage would be 156 mV and the RMS ripple current would be 1.5 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitor is
rated for 25 V and the ripple current capacity is greater than 3 A, providing ample margin. It is very important that
the maximum ratings for voltage and current are not exceeded under any circumstance.

Additionally some bulk capacitance may be needed, especially if the TPS5430 circuit is not located within about
2 inches from the input voltage source. The value for this capacitor is not critical but it also should be rated to
handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage
is acceptable.

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MIN

OUT(MAX)

IN(MAX)

)

OUT

IN(max)

IND

OUT

(4)

L(RMS)

OUT(MAX)

)

OUT

IN(MAX)

OUT

IN(MAX)

OUT

0.8

(5)

L(PK)

OUT(MAX)

)

OUT

IN(MAX)

OUT

1.6

IN(MAX)

OUT

(6)

85 V

OUT

(7)

TPS5430

SLVS632 JANUARY 2006

Output Filter Componts

Two components need to be selected for the output filter, L1 and C2. Since the TPS5430 is an internally
compensated device, a limited range of filter component types and values can be supported.

Inductor Selection

To calculate the minimum value of the output inductor, use

Equation 4

IND

is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.

Three things need to be considered when determining the amount of ripple current in the inductor: the peak to
peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current
and the amount of ripple current determines at what point the circuit will become discontinuous. For designs
using the TPS5430, K

IND

of 0.2 to 0.3 yields good results. Low output ripple voltages can be obtained when

paired with the proper output capacitor, the peak switch current will be well below the current limit set point and
relatively low load currents can be sourced before dicontinuous operation.

For this design example use K

IND

= 0.2 and the minimum inductor value is calculated to be 12.5

H. The next

highest standard value is 15

H, which is used in this design.

For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from

Equation 5

and the peak inductor current can be determined with

Equation 6

For this design, the RMS inductor current is 3.003 A, and the peak inductor current is 3.31 A. The chosen
inductor is a Sumida CDRH104R-150 15

H. It has a saturation current rating of 3.4 A and a RMS current rating

of 3.6 A, easily meeting these requirements. A lesser rated inductor could be used, however this device was
chosen because of its low profile component height. In general, inductor values for use with the TPS5430 are in
the range of 10

H to 100

Capacitor Selection

The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value
of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the
desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the
design of the internal compensation, it is desirable to keep the closed loop crossover frequency in the range 3
kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design
example, it is assumed that the intended closed loop crossover frequency will be between 2590 Hz and 24 kHz
and also below the ESR zero of the output capacitor. Under these conditions the closed loop crossover
frequency will be related to the LC corner frequency by:

And the desired output capacitor value for the output filter to:

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OUT

)

3357

OUT

(8)

ESR

MAX

)

OUT

(9)

-p(MAX)

ESR

MAX

OUT

IN(MAX)

)

OUT

IN(MAX)

OUT

(10)

COUT(RMS)

1
12

OUT

IN(MAX)

)

OUT

IN(MAX)

OUT

(11)

1.221

OUT

)

1.221

(12)

TPS5430

SLVS632 JANUARY 2006

For a desired crossover of 18 kHz and a 15-

H inductor, the calculated value for the output capacitor is 220

The capacitor type shold be chosen so that the ESR zero is above the loop crossover. The maximum ESR
should be: (Add new equation)

The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet will result in an acceptable output
ripple voltage:

Where:

P-P

is the desired peak-to-peak output ripple.

is the number of parallel output capacitors.

is the switching frequency.

For this design example, a single 220-

F output capacitor is chosen for C3. The calculated RMS ripple current is

143 mA and the maximum ESR required is 40 m

. A capacitor that meets these requirements is a Sanyo

Poscap 10TPB220M, rated at 10 V with a maximum ESR of 40 m

and a ripple current rating of 3.0 A. An

additional small 0.1-

F ceramic bypass capacitor may also used, but is not included in this design.

The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 and 54 kHz.

The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one
half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by

Equation 11

Where:

is the number of output capacitors in parallel.

is the switching frequency.

Other capacitor types can be used with the TPS5430, depending on the needs of the application.

Output Voltage Setpoint

The output voltage of the TPS5430 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5.0 V using

Equation 12

For any TPS5430 design, start with an R1 value of 10 k

. R2 is then 3.24 k

Boot Capacitor

The boot capacitor should be 0.01

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PwPd

GND

12!35 V

ENA
NC
NC

22 H

C1
10 F

VIN

5 V

VSNS

TPS5430DDA

BOOT

C3
220 F

VIN

R2
3.24 kW

0.01 F

VOUT

R1
10 kW

SBL845

ADVANCED INFORMATION

Output Voltage Limitations

OUTMAX

0.87

INMIN

OMAX

0.230

)

OMAX

(13)

OUTMIN

0.12

INMAX

OMIN

0.110

)

OMIN

(14)

TPS5430

SLVS632 JANUARY 2006

Catch Diode

The TPS5430 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the
peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage
of 40 V, forward current of 3 A, and a forward voltage drop of 0.5V.

Additional Circuits

Figure 12

shows an application circuit utilizing a wide input voltage range. The design parameters are simillar to

those given for the design example, with a larger value output inductor and a lower closed loop crosover
frequency.

Figure 12. 12-35 V Input to 5 V Output Application Circuit

Due to the internal design of the TPS5430, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:

Where

INMIN

= minimum input voltage

OMAX

= maximum load current

= catch diode forward voltage.

= output inductor series resistance.

This equation assumes maximum on resistance for the internal high side FET.

The lower limit is constrained by the minimum controllable on time which may be as high as 200nsec. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:

Where

INMAX

= maximum input voltage

OMIN

= minimum load current

= catch diode forward voltage.

= output inductor series resistance.

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Internal Compensation Network

H(s)

)

Fz1

)

Fz2

Fp0

)

Fp1

)

Fp2

)

Fp3

(15)

Thermal Calculations

TPS5430

SLVS632 JANUARY 2006

This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
carefully checked to assure proper functionality.

The design equations given in the example circuit can be used to generate circuits using the TPS5430. These
designs are based on certain assumptions and will tend to always select output capacitors within a limited range
of ESR values. If a different capacitor type is desired, it may be posssible to to fit one to the internal
compensation of the TPS5430.

Equation 15

gives the nominal frequency response of the internal voltage-mode

type III compensation network:

Where

Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
Fp3 represents the non-ideal parasitics effect.

Using this information along with the desired output voltage, feed forward gain and output filter characteristics,the
closed loop transfer function can be derived.

The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.

Conduction Loss: Pcon=Io

Rds,on

VOUT/VIN

Switching Loss: Psw = VIN

IOUT

0.01

Quiescent Current Loss: Pq = VIN

0.01

Total Loss: Ptot = Pcon + Psw + Pq
Given T

=> Estimated Junction Temperature: T

= T

+ Rth

Ptot

Given T

JMAX

= 125

C => Estimated Maximum Ambient Temperature: T

AMAX

= T

JMAX

Rth x Ptot

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PERFORMANCE GRAPHS

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.5

1.5

2.5

- Output Current - A

Output Regulation - %

100

0.5

1.5

2.5

3.5

- Output Current - A

Efficiency - %

V = 15 V

V = 10.8 V

V = 12 V

V = 18 V

V = 19.8 V

t -Time - 500 ns/Div

PH = 5 V/Div

= 100 mV/Div (AC Coupled)

-0.1

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

0.08

0.1

10.8

13.8

16.8

19.8

V - Input Voltage - V

Input Regulation - %

= 0 A

= 3 A

= 1.5 A

TPS5430

SLVS632 JANUARY 2006

The performance graphs in Figures 12 - 18 are applicable to the circuit in Figure 10. Ta = 25

C. unless

otherwise specified.

Figure 13. Efficiency vs. Output Current

Figure 14. Output Regulation % vs. Output Current

Figure 15. Input Regulation % vs. Input Voltage

Figure 16. Input Voltage Ripple and PH Node, Io = 3 A.

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

TPS5430DDA

ACTIVE

Power

PAD

DDA

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TPS5430DDAG4

ACTIVE

Power

PAD

DDA

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TPS5430DDAR

ACTIVE

Power

PAD

DDA

2500 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TPS5430DDARG4

ACTIVE

Power

PAD

DDA

2500 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

10-Feb-2006

Addendum-Page 1

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Part Number TPS5430

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