TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A DECEMBER 1995 REVISED AUGUST 1996
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
Dual TL16C550C Universal Asynchronous
Receiver/Transmitters (UARTs)
D
IEEE 1284 Bidirectional Parallel Data (PD)
Port
Compatible With Standard Centronics
Parallel Interface
Support for Parallel Protocols: Extended
Capability Port (ECP) and Enhanced
Parallel Port (EPP)
Data Path 16-Byte FIFO Buffer
Direct Memory Access (DMA) Transfer
Decompression of Run Length Encoded
Data in ECP Reverse Mode
Direct Connection to Printer, No External
Transceiver is Needed
D
Serial Ports Have Infrared Data Association
(IrDA) Inputs and Outputs
1200 bps to 115.2 kbps Data Rate
D
16-Byte FIFOs Reduce CPU Interrupts
D
12 mA Drive Current for All 1284 Control
Terminals and Parallel Port Data Terminals
D
Programmable Auto Flow Control on the
UARTs
D
Capable of Running With All Existing
TL16C450 Software
D
After Reset, All Registers Are Identical to
the TL16C450 Register Set
D
Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation
D
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
D
Programmable Baud-Rate Generator
Allows Division of Any Input Reference
Clock by 1 to (2
16
1) and Generates an
Internal 16
×
Clock
D
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
D
On-Board Prescaler With Programmable
Divisor Values From 0 to 33
D
Independent Control of Transmit, Receive,
Line Status, and Data-Set Interrupts on
Each Channel
D
Fully Programmable Serial-Interface
Characteristics:
5-, 6-, 7-, or 8-Bit Characters
Even-, Odd-, or No-Parity Bit Generation
and Detection
1-, 1 1/2-, or 2-Stop Bit Generation
Baud Generation (DC to 1 Mbit Per
Second)
D
False Start-Bit Detection
D
Complete Status Reporting Capabilities
D
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
D
Line Break Generation and Detection
D
Internal Diagnostic Capabilities:
Loopback Controls for Communications
Link-Fault Isolation
Break, Parity, Overrun, and Framing
Error Simulation
D
Fully Prioritized Interrupt System Controls
D
Modem-Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D
Available in 80-Pin Quad Flatpack (QFP)
Package
description
The TL16PIR552 has a dual-channel universal asynchronous receiver/transmitter (UART). The UART is similar
to the TL16C550C. The device serves two serial input/output ports simultaneously in microcomputer or
microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual UART can be read by the CPU at any time during
functional operation. The information obtained includes the type and condition of the transfer operation being
performed and the error condition.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A DECEMBER 1995 REVISED AUGUST 1996
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
description (continued)
The receiver and transmitter FIFOs in the UARTs store up to 16 bytes including three additional bits of error
status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can
significantly reduce software overload and increase system efficiency by automatically controlling serial data
flow through RTS output and CTS input signals.
The TL16PIR552 UART includes a programmable baud-rate generator capable of dividing a reference clock
by divisors from 1 to 65535 and producing a 16
×
reference clock for the internal transmitter logic. Provisions
are also included to use this 16
×
clock for the receiver logic. The UART accommodates a 1-Mbaud serial rate
(16-MHz input clock) so that a bit time is 1
µ
s and a typical character time is 10
µ
s (start bit, eight data bits, stop
bit).
Each serial channel has a prescaler with programmable divisor values from 0 to 33. The serial ports also have
a dedicated infrared serial data input (IRSIN0/1) and the serial data outputs multiplex between a RS-232-type
serial output or an infrared serial data output. This is selected through an internal register bit and uses the same
SOUT0/1 output terminals. The same UART circuit is used for the data path for the IrDA or the RS-232
operations. Channel 0 is powered up at IR0 and channel 1 is powered up during the RS-232 mode.
In addition to dual communication capabilities, the TL16PIR552 provides the user with an IEEE 1284 host side
compatible, bidirectional, parallel data port. The parallel port operates in a compatible, FIFO, extended
capability port (ECP) with RLE data decompression mode, and in a enhanced parallel port (EPP) mode. The
default mode of operation is compatible with the Centronics printer port. The parallel port and the two serial ports
provide IBM PC/AT
TM
-compatible computers with a single device to serve a 3-port system.
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
D7
D6
D5
D4
PH PACKAGE
(TOP VIEW)
D3
D2
D1
D0
GND
A0
A1
A2
IOW
IOR
CS0
TC
PDACK
V
CC
RESET
CS1
PPCS
ECPCS
SELECT
FAULT
BUSY
ACK
TEST
XIN
GND
XOUT
TXRDY1
PINTR
PDRQ
CLK_OUT0
VCC
IOCHRDY
INTRPT0
INTRPT1
RXRDY1
PD7
PD6
PD5
PD4
GND
PD3
PD2
PD1
GND
INIT
SELECTIN
STROBE
AUT
OFD
V
CC
SOUT0
DTR0
R
TS0
V
CC
CTS0
DSR0
IRSIN0
DCD0
RI0
SIN0
GND
SOUT1
DTR1
RTS1
SIN1
DSR1
DCD1
CTS1
PD0
RXRDY0
TXRDY0
BDO
PERROR
IRSIN1
RI1
CLK_OUT1
VCC
IBM and PC/AT are trademarks of International Business Machines Corporation.
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A DECEMBER 1995 REVISED AUGUST 1996
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
functional block diagram
IR Encoder
and
Transmit
M
U
X
M
U
X
IR Decoder
Receiver
prescaler
# 0
SOUT0
IRSIN0
SIN0
RTS0
DTR0
CTS0
DSR0
DCD0
RI0
CLK_OUT0
D7 D0
A2 A0
IOW
IOR
RESET
CS0
INTRPT0
RXRDY0
TXRDY0
IR Incoder
and
Transmit
M
U
X
M
U
X
IR Decoder
Receiver
prescaler
# 1
SOUT1
IRSIN1
SIN1
RTS1
DTR1
CST1
DSR1
DCD1
RI1
CLK_OUT1
RESET
CS1
INTRPT1
RXRDY1
TXRDY1
22 MHz
RESET
TC
PDACK
PPCS
ECPCS
PINTR
PDRQ
IOCHRDY
TEST
XIN
XOUT
1284
Port
UART 1
UART 0
PD7 PD0
AUTOFD
INIT
SELECTIN
STROBE
ACK
BUSY
FAULT
PERROR
SELECT
36
18
1210
13
14
19
15
40
42
32
73
19
20
41
43
33
28
29
31
19
16
17
21
22
34
35
39
59
65
68
61
60
63
64
66
67
70
78
75
72
71
79
76
77
80
4447, 4952
57
54
55
56
27
26
25
23
24
NOTE A: Terminal numbers shown are for the PH package.
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A DECEMBER 1995 REVISED AUGUST 1996
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
A0A2
1012
I
Register select. A0A2 are address lines that select the internal registers in the device.
ACK
27
I
Data acknowledge. In compatibility mode ACK is pulled low by the peripheral device to acknowledge
transfer of a data byte from the host. In ECP mode, ACK is used in a closed loop handshake with the host
AUTOFD to transfer data from the peripheral device to the host. It is asserted low by the peripheral device
to indicate data is available. In EPP mode, ACK is used by the peripheral device to interrupt the host. This
signal is active high and is positive-edge triggered.
AUTOFD
57
O
Autofeed. In compatibility mode AUTOFD is set low in conjunction with SELECTIN being set high to request
a 1284 mode. Then AUTOFD is set high after the peripheral device acknowledges the signal by setting ACK
low. In EPP mode, AUTOFD is an active low output that is used to denote data read or write operations.
It also provides a ninth data bit that is used to determine whether address or data information is present
on the data lines in the forward mode. In EPP mode this signal is active low to denote data read or write
operations. In ECP mode, AUTOFD requests a byte of data from the peripheral when asserted,
handshaking with ACK in the reverse direction. In the forward direction AUTOFD indicates whether the data
lines contain the ECP address or data. The host drives this signal to flow control in the reverse direction.
It is an "interlocked" handshake with ACK. AUTOFD also provides command information in the forward
phase.
BDO
38
O
Bus buffer output. BDO output is active (high) when the CPU is not reading data. It controls the system bus
driver.
BUSY
26
I
Busy. In compatibility mode BUSY is driven high to indicate that the peripheral is not ready to receive data.
In the ECP mode, BUSY is driven high to indicate that the peripheral is not ready to receive data and is
driven low to indicate that the peripheral is ready to receive data in forward mode. In reverse mode, BUSY
is low when the information on the data lines are commands (RLE) and it is high when the information on
the data lines is data. In EPP mode, BUSY is active low. It is driven inactive as a positive acknowledgment
from the peripheral device that data or address information is completed. It is active when the peripheral
is ready for the next data and address transfer. In ECP mode, BUSY deasserts to indicate that the peripheral
can accept data. It handshakes with STROBE in the forward direction. In the reverse direction BUSY
indicates whether the data lines contain the ECP command information or data. The peripheral uses this
signal to control flow in the forward direction. It is an "interlocked" handshake with STROBE. BUSY also
provides command information in the reverse direction.
CLK_OUT0,
CLK_OUT1
36, 73
O
Prescaler Outputs. CLK_OUT0 and CLK_OUT1 drive the UARTs.
CS0, CS1
15,20
I
Chip select. CS0 and CS1 are active low inputs that act as an enable for the write operation and a read
operation for the UART. CS0 enables UART0 and CS1 enables UART1.
CTS0,
CTS1
63
79
I
Clear to send. CTS0 and CTS1 are modem-status signals whose condition can be verified by reading bit
4 (CTS) of the MSR. Bit 0 (
CTS) of the MSR indicates that CTS0 or CTS1 has changed states since the
last read operation from the MSR. When the modem-status interrupt is enabled, CTS0 or CTS1 changes
states, and an interrupt is generated. CTS0 or CTS1 is also used in the auto-CTS mode to control the
transmitter.
D7D0
18
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the CPU and the device.
DCD0,
DCD1
66
77
I
Data carrier detect. DCD0 and DCD1 are modem status signals whose condition can be verified by reading
bit 7 (DCD) of the modem status register (MSR). Bit 3 (
DCD) of the MSR indicates that DCD0 or DCD1
has changed state since the last read from MSR. If the modem status interrupt is enabled when DCD0 or
DCD1 changes state, an interrupt is generated.
DSR0,
DSR1
64
76
I
Data set ready. DSR0 and DSR1 are modem status signals whose condition can be verified by reading bit
5 (DSR) of the MSR. Bit 1 (
DSR) of the MSR indicates that DSR0 or DSR1 has changed state since the
last read from MSR. If the modem status interrupt is enabled when DSR0 or DSR1 changes state, an
interrupt is generated.
DTR0,
DTR1
60
71
O
Data terminal ready. When active, (low), DTR0 or DTR1 informs a modem or data set that the UART is ready
to establish communication. DTR0 or DTR1 is placed in the active state by setting bit 0 of the modem-control
register (MCR) to 1. DTRx is placed in the inactive state either as a result of a master reset, during
loop-mode operation, or resetting bit 0 of the MCR.
ECPCS
22
I
Chip select. ECPCS is used for the ECP parallel port internal registers, and is an active low signal.
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A DECEMBER 1995 REVISED AUGUST 1996
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
FAULT
25
I
Fault indication. In compatibility mode FAULT is set high to acknowledge the 1284 mode requested. The
EPP mode is user defined. In ECP mode FAULT generates an error interrupt when asserted. It provides
a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP
mode the peripheral is permitted (but not required) to drive this terminal low to request a reverse transfer.
The request is merely a "hit" to the host; the host has ultimate control over the transfer direction. FAULT
is typically used to generate an interrupt to the host CPU.
GND
9, 30,
48, 53,
69
Ground terminal.
INIT
54
O
Initiation. In compatibility mode INIT is pulsed low to reset the interface and force a return to the compatibility
mode idle phase.In ECP mode INIT is driven low to place the channel in the reverse direction and it allows
the peripheral to drive the bidirectional data lines when SELECTIN is high. In EPP mode INIT is active low.
When driven low, this signal initiates a termination cycle that results in the interface returning to the
compatibility mode.
INTRPT0,
INTRPT1
40,41
O
Interrupt (01). When active (high), INTRPT0 or INTRPT1 informs the CPU that the UART has an interrupt
to be serviced. Four conditions that cause an interrupt to be issued include a receiver error, received data
is available, an empty transmitter holding register, or an enabled modem-status interrupt.
IOCHRDY
39
O
ISA channel ready. IOCHRDY is an open drain output that extends the length of a bus cycle when it is
inactive.
IOR
14
I
Read input. IOR is an active low input signal that enables the selected channel to output data to D7D0.
The data output depends upon the register selected by the address A2A0 inputs and chip select.
IOW
13
I
Write input. IOW is an active low input signal that enables the data to be input to either a UART or to the
parallel port. The data destination depends upon the register selected by the address inputs A2A0 and
chip select.
IRSIN0, IRSIN1
65, 78
I
Serial data. IRSIN0 and IRSIN1 are serial inputs from an IR serial data communication device.
PD0PD7
5249,
4744
I/O
Parallel data bits (07). PD0PD7 provide a byte wide input or 4744 output port to the system. These bits
contain address, data, or RLE command data.
PDACK
17
I
Parallel port DMA acknowledge. PDACK is an active low input.
PDRQ
35
O
DMA Request. PDRQ is used for parallel port DMA requests during ECP and FIFO modes.
PERROR
23
I
Peripheral error. In compatibility mode PERROR is driven high when the device encounters an error in the
paper path. In ECP mode the peripheral drives PERROR low to acknowledge a reverse request (INIT).
Based on this signal the host determines when it is permitted to drive the data bus. In EPP mode the signal
is user defined.
PINTR
34
O
Parallel port interrupt. PINTR is a 3-state output. In EPP mode this is an active high, positive-edge triggered
input.
PPCS
21
I
Chip select. PPCS is used for the parallel port internal registers and is an active-low signal.
RI0,
RI1
67,80
I
Ring Indicator. RI0 and RI1 are modem-status signals whose condition can be verified by reading bit 6 (RI)
of the MSR. Bit 2 (TERI) of the MSR indicates that the RI0/RI1 input has transitioned from a low to a high
level since the last read operation from MSR. If the modem-status interrupt is enabled when this transition
occurs, an interrupt is generated.
RESET
19
I
Reset. RESET is an active high reset that when asserted, clears all UARTs and parallel port printer internal
registers.
RTS0,
RTS1
61
72
O
Request to send. When active, RTS0 or RTS1 informs the modem or data set that the UART is ready to
receive data. RTS0 or RTS1 is set to its active level by setting the RTSx modem-control register bit and is
set to inactive (high) either as a result of master reset or during loop-mode operations or by resetting bit
1 (RTS) of the MCR. In the auto-RTS mode, RTSx is set to its inactive level by the receiver threshold-control
logic.
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
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