SN65C1167, SN75C1167, SN65C1168, SN75C1168

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS

SLLS159E - MARCH 1993 - REVISED NOVEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Meet or Exceed Standards TIA/EIA-422-B
and ITU Recommendation V.11

BiCMOS Process Technology

Low Supply-Current Requirements:
9 mA Max

Low Pulse Skew

Receiver Input Impedance . . . 17 k

Typ

Receiver Input Sensitivity . . .

200 mV

Receiver Common-Mode Input Voltage
Range of -7 V to 7 V

Operate From Single 5-V Power Supply

Glitch-Free Power-Up/Power-Down
Protection

Receiver 3-State Outputs Active-Low
Enable for SN65C1167 and SN75C1167 Only

Improved Replacements for the MC34050
and MC34051

description/ordering information

The SN65C1167, SN75C1167, SN65C1168,
and SN75C1168 dual drivers and receivers are
integrated circuits designed for balanced
transmission lines. The devices meet
TIA/EIA-422-B and ITU recommendation V.11.

ORDERING INFORMATION

PACKAGE

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP (N)

Tube

SN75C1167N

SOP (NS)

Tape and reel

SN75C1167NSR

75C1167

SSOP (DB)

Tape and reel

SN75C1167DBR

CA1167

C to 70

PDIP (N)

Tube

SN75C1168N

C to 70

SOP (NS)

Tape and reel

SN75C1168NSR

75C1168

SSOP (DB)

Tape and reel

SN75C1168DBR

CA1168

TSSOP (PW)

Tube

SN75C1168PW

CA1168

TSSOP (PW)

Tape and reel

SN75C1168PWR

CA1168

SOP (NS)

Tape and reel

SN65C1167NSR

65C1167

SSOP (DB)

Tape and reel

SN65C1167DBR

CB1167

-40

C to 85

PDIP (N)

Tube

SN65C1168N

-40

C to 85

SOP (NS)

Tape and reel

SN65C1168NSR

65C1168

TSSOP (PW)

Tube

SN65C1168PW

CB1168

TSSOP (PW)

Tape and reel

SN65C1168PWR

CB1168

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1B
1A

2A
2B

GND

1D
1Y
1Z
DE
2Z
2Y
2D

SN65C1167 . . . DB OR NS PACKAGE

SN75C1167 . . . DB, N, OR NS PACKAGE

(TOP VIEW)

1B
1A

1DE

2A
2B

GND

1D
1Y
1Z
2DE
2Z
2Y
2D

SN65C1168 . . . N, NS, OR PW PACKAGE

SN75C1168 . . . DB, N, NS, OR PW PACKAGE

(TOP VIEW)

SN65C1167, SN75C1167, SN65C1168, SN75C1168

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS

SLLS159E - MARCH 1993 - REVISED NOVEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description/ordering information (continued)

The SN65C1167 and SN75C1167 combine dual 3-state differential line drivers and 3-state differential line
receivers, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, which can be connected together externally to function as direction control.
The SN65C1168 and SN75C1168 drivers have individual active-high enables.

Function Tables

EACH DRIVER

INPUT

ENABLE

OUTPUTS

INPUT

ENABLE

SN75C1167, EACH RECEIVER

DIFFERENTIAL INPUTS

ENABLE

OUTPUT

DIFFERENTIAL INPUTS

A - B

ENABLE

OUTPUT

VID

0.2 V

-0.2 V < VID < 0.2 V

VID

-0.2 V

Open

H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)

logic diagram (positive logic)

2DE

1DE

SN65C1168, SN75C1168

SN65C1167/SN75C1167

SN65C1167, SN75C1167, SN65C1168, SN75C1168

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS

SLLS159E - MARCH 1993 - REVISED NOVEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1)

-0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

-0.5 V to V

+ 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(A or B, Receiver)

-11 V to 14 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage range, V

, Receiver (see Note 2)

-14 V to 14 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

, Driver

-5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamp current range, I

or I

, Driver

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current range, I

, Driver

150 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply current, I

200 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GND current

-200 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current range, I

, Receiver

25 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature

150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

(see Notes 3 and 4): DB package

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . .

N package

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package

108

C/W

. . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

-65

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. All voltage values except differential input voltage are with respect to the network GND.
2. Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.
3. Maximum power dissipation is a function of TJ(max),

JA, and TA. The maximum allowable power dissipation at any allowable

ambient temperature is PD = (TJ(max) - TA)/

JA. Selecting the maximum of 150

C can affect reliability.

4. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.5

5.5

VIC

Common-mode input voltage
(see Note 5)

Receiver

VID

Differential input voltage

Receiver

VIH

High-level input voltage

Except A, B

VIL

Low-level input voltage

Except A, B

0.8

IOH

High-level output current

Receiver

-6

IOH

High-level output current

Driver

-20

IOL

Low-level output current

Receiver

IOL

Low-level output current

Driver

Operating free-air temperature

SN75C1167, SN75C1168

Operating free-air temperature

SN65C1167, SN65C1168

-40

NOTE 5: Refer to TIA/EIA-422-B for exact conditions.

SN65C1167, SN75C1167, SN65C1168, SN75C1168

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS

SLLS159E - MARCH 1993 - REVISED NOVEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIK

Input clamp voltage

II = -18 mA

-1.5

VOH

High-level output voltage

VIH = 2 V,

VIL = 0.8 V,

IOH = -20 mA

2.4

3.4

VOL

Low-level output voltage

VIH = 2 V,

VIL = 0.8 V,

IOL = 20 mA

0.2

0.4

|VOD1|

Differential output voltage

IO = 0 mA

|VOD2|

Differential output voltage

3.1

|VOD|

Change in magnitude of differential
output voltage

RL = 100

See Figure 1 and Note 5

0.4

VOC

Common-mode output voltage

RL = 100

See Figure 1 and Note 5

|VOC|

Change in magnitude of common-mode
output voltage

0.4

IO(OFF) Output current with power off (see Note 3)

VCC = 0 V

VO = 6 V

100

IO(OFF) Output current with power off (see Note 3)

VCC = 0 V

VO = -0.25 V

-100

IOZ

High-impedance-state output current

VO = 2.5 V

IOZ

High-impedance-state output current

VO = 5 V

-20

IIH

High-level input current

VI = VCC or VIH

IIL

Low-level input current

VI = GND or VIL

-1

IOS

Short-circuit output current

VO = VCC or GND,

See Note 6

-30

-150

ICC

Supply current (total package)

No load,

VI = VCC or GND

ICC

Supply current (total package)

No load,
Enabled

VI = 2.4 or 0.5 V, See Note 7

Input capacitance

All typical values are at VCC = 5 V and TA = 25

NOTES:

5. Refer to TIA/EIA-422-B for exact conditions.
6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
7. This parameter is measured per input, while the other inputs are at VCC or GND.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPHL

Propagation delay time, high- to low-level output

R1 = R2 = 50

R3 = 500

tPLH

Propagation delay time, low- to high-level output

R1 = R2 = 50

C1 = C2 = C3 = 40 pF,
See Figure 2

R3 = 500

S1 is open,

tsk(p)

Pulse skew

C1 = C2 = C3 = 40 pF,
See Figure 2

S1 is open,

0.5

Rise time

R1 = R2 = 50

C1 = C2 = C3 = 40 pF,

R3 = 500

S1 is open,

Fall time

C1 = C2 = C3 = 40 pF,
See Figure 3

S1 is open,

tPZH

Output enable time to high level

R1 = R2 = 50

C1 = C2 = C3 = 40 pF,

R3 = 500

S1 is closed,

tPZL

Output enable time to low level

C1 = C2 = C3 = 40 pF,
See Figure 4

S1 is closed,

tPHZ

Output disable time from low level

R1 = R2 = 50

C1 = C2 = C3 = 40 pF,

R3 = 500

S1 is closed,

tPLZ

Output disable time from high level

C1 = C2 = C3 = 40 pF,
See Figure 4

S1 is closed,

All typical values are at VCC = 5 V and TA = 25

SN65C1167, SN75C1167, SN65C1168, SN75C1168

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS

SLLS159E - MARCH 1993 - REVISED NOVEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIT+

Positive-going input threshold voltage,
differential input

0.2

VIT-

Negative-going input threshold voltage,
differential input

-0.2

Vhys Input hysteresis (VIT+ - VIT-)

VIK

Input clamp voltage, RE

SN75C1167

II = -18 mA

-1.5

VOH

High-level output voltage

VID = 200 mV,

IOH = -6 mA

3.8

4.2

VOL

Low-level output voltage

VID = -200 mV,

IOL = 6 mA

0.1

0.3

IOZ

High-impedance-state output
current

SN75C1167

VO = VCC or GND

0.5

Line input current

Other input at 0 V

VI = 10 V

1.5

Line input current

Other input at 0 V

VI = -10 V

-2.5

Enable input current, RE

SN75C1167

VI = VCC or GND

Input resistance

VIC = -7 V to 7 V,

Other input at 0 V

VI = VCC or GND

ICC

Supply current (total package)

No load, Enabled

VIH = 2.4 V or 0.5 V,
See Note 5

All typical values are at VCC = 5 V and TA = 25

The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode

input voltage and threshold voltage levels only.

NOTE 5: Refer to TIA/EIA-422-B for exact conditions.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 8)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH Propagation delay time, low- to high-level output

See Figure 5

tPHL Propagation delay time, high- to low-level output

See Figure 5

tTLH

Transition time, low- to high-level output

VIC = 0 V,

See Figure 5

tTHL

Transition time, high- to low-level output

VIC = 0 V,

See Figure 5

tPZH Output enable time to high level

tPZL

Output enable time to low level

RL = 1 kW, See Figure 6

tPHZ Output disable time from high level

RL = 1 kW, See Figure 6

tPLZ

Output disable time from low level

All typical values are at VCC = 5 V and TA = 25

NOTE 8: Measured per input while the other inputs are at VCC or GND

SN65C1167, SN75C1167, SN65C1168, SN75C1168

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS

SLLS159E - MARCH 1993 - REVISED NOVEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

VOC

VOD2

Figure 1. Driver Test Circuit, V

and V

50%

tPLH

tPHL

tPLH

VOLTAGE WAVEFORMS

Input

(see Note B)

1.3 V

Input

1.5 V

See Note A

TEST CIRCUIT

1.3 V

tsk(p)

1.3 V

VOH

VOL

3 V

0 V

VOH

VOL

NOTES: A. C1, C2, and C3 include probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf

6 ns.

Figure 2. Driver Test Circuit and Voltage Waveforms

VOLTAGE WAVEFORMS

0 V

3 V

10%

90%

Input

1.5 V

See Note A

TEST CIRCUIT

10%

90%

Input

(see Note B)

Differential

Output

VOD

NOTES: A. C1, C2, and C3 include probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf

6 ns.

Figure 3. Driver Test Circuit and Voltage Waveforms

SN65C1167, SN75C1167, SN65C1168, SN75C1168

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS

SLLS159E - MARCH 1993 - REVISED NOVEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

VOH

VOL

1.5 V

2 V

0.8 V

VOL + 0.3 V

tPZH

tPHZ

tPZL

tPLZ

VOLTAGE WAVEFORMS

Input DE

3 V

0 V

1.5 V

1.3 V

0 V

3 V

1.5 V

See Note A

TEST CIRCUIT

VOL - 0.3 V

Pulse

Generator

See Note B

Output

NOTES: A. C1, C2, and C3 include probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf

6 ns.

Figure 4. Driver Test Circuit and Voltage Waveforms

-2.5 V

2.5 V

VOL

VOH

0 V

10%

90%

tPHL

tPLH

VOLTAGE WAVEFORMS

A Input

VCC

B Input

Device

Under

Test

CL = 50 pF
(see Note A)

TEST CIRCUIT

90%

10%

tTLH

50%

tTHL

Output

(see Note B)

B Input

A Input = 0 V

50%

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: PRR

1 MHz, duty cycle = 50%, tr = tf

6 ns.

Figure 5. Receiver Test Circuit and Voltage Waveforms

SN65C1167, SN75C1167, SN65C1168, SN75C1168

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS

SLLS159E - MARCH 1993 - REVISED NOVEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

VCC

Device

Under

Test

CL = 50 pF
(see Note A)

TEST CIRCUIT

tPZL

tPLZ

3 V

0 V

RE Input

1.3 V

GND

0.5 V

Output

VOH

VCC

0.5 V

Output

VOL

50%

tPZH

tPHZ

VID = -2.5 V

or 2.5 V

tPZH, tPHZ Measurement: S1 to GND

tPZL, tPLZ Measurement: S1 to VCC

VOLTAGE WAVEFORMS

RE Input

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: PRR

1 MHz, duty cycle = 50%, tr = tf

6 ns.

Figure 6. Receiver Test Circuit and Voltage Waveforms

MECHANICAL

MPDI002C JANUARY 1995 REVISED DECEMBER 20002

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

N (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

0.325 (8,26)
0.300 (7,62)

0.010 (0,25) NOM

Gauge Plane

0.015 (0,38)

0.430 (10,92) MAX

1.060

(26,92)

0.940

(23,88)

0.920

0.850

0.775

0.745

(19,69)

(18,92)

0.775

(19,69)

(18,92)

0.745

A MIN

DIM

A MAX

PINS **

(23,37)

(21,59)

Seating Plane

14/18 PIN ONLY
20 pin vendor option

4040049/E 12/2002

0.070 (1,78)

0.045 (1,14)

0.020 (0,51) MIN

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

0.010 (0,25)

0.100 (2,54)

16 PINS SHOWN

MS-100

VARIATION

0.030 (0,76)

0.045 (1,14)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).

D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

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Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

2003, Texas Instruments Incorporated

Part Number SN75C1168