SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
Meets or Exceeds the Requirements of
ANSI TIA/EIA-644-1995 Standard
D
Signaling Rates up to 400 Mbit/s
D
Bus-Terminal ESD Exceeds 12 kV
D
Operates from a Single 3.3-V Supply
D
Low-Voltage Differential Signaling With
Typical Output Voltages of 350 mV and a
100
Load
D
Propagation Delay Times
Driver: 1.7 ns Typ
Receiver: 3.7 ns Typ
D
Power Dissipation at 200 MHz
Driver: 25 mW Typical
Receiver: 60 mW Typical
D
LVTTL Input Levels are 5 V Tolerant
D
Driver is High Impedance When Disabled or
With V
CC
< 1.5 V
D
Receiver has Open-Circuit Fail Safe
D
Surface-Mount Packaging
D Package (SOIC)
DGK Package (MSOP) ('LVDS79 Only)
description
The SN65LVDS179, SN65LVDS180,
SN65LVDS050, and SN65LVDS051 are differen-
tial line drivers and receivers that use low-voltage
differential signaling (LVDS) to achieve signaling
rates as high as 400 Mbps. The TIA/EIA-644
standard compliant electrical interface provides a
minimum differential output voltage magnitude of
247 mV into a 100
load and receipt of 100 mV
signals with up to 1 V of ground potential
difference between a transmitter and receiver.
The intended application of this device and
signaling technique is for point-to-point baseband
data transmission over controlled impedance
media of approximately 100
characteristic
impedance. The transmission media may be
printed-circuit board traces, backplanes, or
cables. (Note: The ultimate rate and distance of
data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to
the environment, and other application specific
characteristics).
Copyright
©
2000, Texas Instruments Incorporated
R
D
Y
Z
A
B
R
D
Y
Z
A
B
DE
RE
2
3
2
5
4
3
5
6
8
7
9
10
12
11
2D
1D
1Y
1Z
2Y
2Z
DE
9
15
12
14
13
10
11
2R
1R
1A
1B
2A
2B
RE
5
3
4
2
1
6
7
1R
1D
1Y
1Z
1A
1B
1DE
3
15
4
14
13
2
1
2R
2D
2Y
2Z
2A
2B
2DE
5
9
12
10
11
6
7
1
2
3
4
8
7
6
5
V
CC
R
D
GND
A
B
Z
Y
SN65LVDS179D (Marked as DL179 or LVD179)
SN65LVDS179DGK (Marked as S79)
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
R
RE
DE
D
GND
GND
V
CC
V
CC
A
B
Z
Y
NC
SN65LVDS180D (Marked as LVDS180)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
RE
2R
2A
2B
GND
V
CC
1D
1Y
1Z
DE
2Z
2Y
2D
SN65LVDS050D (Marked as LVDS050)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
1DE
2R
2A
2B
GND
V
CC
1D
1Y
1Z
2DE
2Z
2Y
2D
SN65LVDS051D (Marked as LVDS051)
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
description (continued)
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
SMALL OUTLINE
(DGK)
SN65LVDS050D
--
40
°
C to 85
°
C
SN65LVDS051D
--
40
°
C to 85
°
C
SN65LVDS179D
SN65LVDS179DGK
SN65LVDS180D
--
NOTE:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics
of the media, the noise coupling to the environment, and other application specific characteristics.
The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are characterized for operation from
40
°
C to 85
°
C.
Function Tables
SN65LVDS179 RECEIVER
INPUTS
OUTPUT
VID = VA VB
R
VID
100 mV
H
100 MV < VID < 100 mV
?
VID
100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
SN65LVDS179 DRIVER
INPUT
OUTPUTS
D
Y
Z
L
L
H
H
H
L
Open
L
H
H = high level, L = low level
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 RECEIVER
INPUTS
OUTPUT
VID = VA VB
RE
R
VID
100 mV
L
H
100 MV < VID < 100 mV
L
?
VID
100 mV
L
L
Open
L
H
X
H
Z
H = high level, L = low level, Z = high impedance,
X = don't care
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 DRIVER
INPUTS
OUTPUTS
D
DE
Y
Z
L
H
L
H
H
H
H
L
Open
H
L
H
X
L
Z
Z
H = high level, L = low level, Z = high impedance,
X = don't care
equivalent input and output schematic diagrams
300 k
50
VCC
7 V
D or RE
Input
300 k
50
VCC
7 V
DE
Input
5
10 k
7 V
Y or Z
Output
VCC
7 V
VCC
7 V
R Output
VCC
5
B Input
A Input
300 k
300 k
7 V
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range (D, R, DE, RE)
0.5 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: Y, Z, A, B , and GND (see Note 2)
CLass 3, A:12 kV, B:600 V
. . . . . . . . . . . . . . . . . .
All
Class 3, A:7 kV, B:500 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation
see dissipation rating table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
250
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA
25
°
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
°
C
TA = 85
°
C
POWER RATING
D8
725 mW
5.8 mW/
°
C
377 mW
D14 or D16
950 mW
7.8 mW/
°
C
494 mW
DGK
424 mW
3.4 mW/
°
C
220 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
High-level input voltage, VIH
2
V
Low-level input voltage, VIL
0.8
V
Magnitude of differential input voltage,
VID
0.1
0.6
V
Commonmode input voltage, VIC (see Figure 6)
V
ID
2
2.4
*
V
ID
2
V
VCC0.8
Operating freeair temperature, TA
40
85
°
C
device electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SN65LVDS179
No receiver load, Driver RL = 100
9
12
mA
Driver and receiver enabled, No receiver load, Driver RL = 100
9
12
SN65LVDS180
Driver enabled, Receiver disabled, RL = 100
5
7
mA
SN65LVDS180
Driver disabled, Receiver enabled, No load
1.5
2
mA
Supply
Disabled
0.5
1
ICC
Supply
current
Drivers and receivers enabled, No receiver loads, Driver RL = 100
12
20
current
SN65LVDS050
Drivers enabled, Receivers disabled, RL = 100
10
16
mA
SN65LVDS050
Drivers disabled, Receivers enabled, No loads
3
6
mA
Disabled
0.5
1
SN65LVDS051
Drivers enabled, No receiver loads, Driver RL = 100
12
20
mA
SN65LVDS051
Drivers disabled, No loads
3
6
mA
All typical values are at 25
°
C and with a 3.3-V supply.
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOD
Differential output voltage magnitude
RL = 100
247
340
454
VOD
Change in differential output voltage magnitude between logic
states
RL = 100
,
See Figure 1 and Figure 2
50
50
mV
VOC(SS)
Steady-state common-mode output voltage
1.125
1.2
1.375
V
VOC(SS)
Change in steady-state common-mode output voltage between
logic states
See Figure 3
50
50
mV
VOC(PP)
Peak-to-peak common-mode output voltage
50
150
mV
IIH
High level input current
DE
VIH = 5 V
0.5
20
µ
A
IIH
High-level input current
D
VIH = 5 V
2
20
µ
A
IIL
Low level input current
DE
VIL = 0 8 V
0.5
10
µ
A
IIL
Low-level input current
D
VIL = 0.8 V
2
10
µ
A
IOS
Short circuit output current
VOY or VOZ = 0 V
3
10
mA
IOS
Short-circuit output current
VOD = 0 V
3
10
mA
IOZ
High impedance output current
VOD = 600 mV
±
1
µ
A
IOZ
High-impedance output current
VO = 0 V or VCC
±
1
µ
A
IO(OFF)
Power-off output current
VCC = 0 V, VO = 3.6 V
±
1
µ
A
CIN
Input capacitance
3
pF
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH+
Positive-going differential input voltage threshold
See Figure 5 and Table 1
100
mV
VITH
Negative-going differential input voltage threshold
See Figure 5 and Table 1
100
mV
VOH
High-level output voltage
IOH = 8 mA
2.4
V
VOL
Low-level output voltage
IOL = 8 mA
0.4
V
II
Input current (A or B inputs)
VI = 0
2
11
20
µ
A
II
Input current (A or B inputs)
VI = 2.4 V
1.2
3
µ
A
II(OFF)
Power-off input current (A or B inputs)
VCC = 0
±
20
µ
A
IIH
High-level input current (enables)
VIH = 5 V
±
10
µ
A
IIL
Low-level input current (enables)
VIL = 0.8 V
±
10
µ
A
IOZ
High-impedance output current
VO = 0 or 5 V
±
10
µ
A
CI
Input capacitance
5
pF
All typical values are at 25
°
C and with a 3.3-V supply.
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
6
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
1.7
2.7
ns
tPHL
Propagation delay time, high-to-low-level output
1.7
2.7
ns
tr
Differential output signal rise time
RL = 100
,
CL 10 pF
0.8
1
ns
tf
Differential output signal fall time
CL = 10 pF,
See Figure 6
0.8
1
ns
tsk(p)
Pulse skew (|tpHL tpLH|)
See Figure 6
300
ps
tsk(o)
Channel-to-channel output skew§
150
ps
tPZH
Propagation delay time, high-impedance-to-high-level output
4.3
10
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
See Figure 7
4.6
10
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
See Figure 7
3.1
10
ns
tpLZ
Propagation delay time, low-level-to-high-impedance output
3.4
10
ns
All typical values are at 25
°
C and with a 3.3-V.
tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
§ tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
¶ tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
3.7
4.5
ns
tPHL
Propagation delay time, high-to-low-level output
3.7
4.5
ns
tsk(p)
Pulse skew (|tpHL tpLH|)
CL = 10 pF, See Figure 6
0.3
ns
tr
Output signal rise time
0.7
1.5
ns
tf
Output signal fall time
0.9
1.5
ns
tPZH
Propagation delay time, high-level-to-high-impedance output
2.5
ns
tPZL
Propagation delay time, low-level-to-low-impedance output
See Figure 7
2.5
ns
tPHZ
Propagation delay time, high-impedance-to-high-level output
See Figure 7
7
ns
tPLZ
Propagation delay time, low-impedance-to-high-level output
4
ns
All typical values are at 25
°
C and with a 3.3-V.
tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
§ tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
¶ tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
7
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
driver
VOD
VOZ
VOY
VOC
VI
IOY
IOZ
II
A
Z
Y
V
OY
)
V
OZ
2
Driver Enable
Figure 1. Driver Voltage and Current Definitions
2 V
1.4 V
0.8 V
100%
80%
20%
0%
0 V
VOD(H)
VOD(L)
Output
Input
VOD
Z
Y
Input
100
±
1%
CL = 10 pF
(2 Places)
tPHL
tPLH
tf
tr
Driver Enable
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf
1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10
±
0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
8
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOC
Z
Y
Input
CL = 10 pF
(2 Places)
3 V
0 V
VOC(PP)
VOC(SS)
VOC
49.9
,
±
1% (2 Places)
Driver Enable
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf
1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10
±
0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a 3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
1.2 V
Z
Y
0.8 V or 2 V
49.9
,
±
1% (2 Places)
CL = 10 pF
(2 Places)
DE
VOY VOZ
2 V
0.8 V
tPHZ
tPZH
tPLZ
tPZL
1.4 V
~1.4 V
1.2 V
1.25 V
1.2 V
~1 V
1.15 V
DE
VOY or VOZ
VOZ or VOY
D at 2 V and input to DE
D at 0.8 V and input to DE
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf
1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500
±
10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
9
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
receiver
VIB
VID
VIA
VIC
VO
A
B
R
V
IA
)
V
IB
2
Figure 5. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
(V)
RESULTING DIFFERENTIAL
INPUT VOLTAGE
(mV)
RESULTING COMMON-
MODE INPUT VOLTAGE
(V)
VIA
VIB
VID
VIC
1.25
1.15
100
1.2
1.15
1.25
100
1.2
2.4
2.3
100
2.35
2.3
2.4
100
2.35
0.1
0
100
0.05
0
0.1
100
0.05
1.5
0.9
600
1.2
0.9
1.5
600
1.2
2.4
1.8
600
2.1
1.8
2.4
600
2.1
0.6
0
600
0.3
0
0.6
600
0.3
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
10
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
VIB
VID
VIA
VO
CL
10 pF
VOH
VOL
1.4 V
VO
VIA
VIB
VID
1.4 V
1 V
0.4 V
0 V
0.4 V
tPHL
tPLH
tr
tf
0.4 V
2.4 V
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf
1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10
±
0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 6. Timing Test Circuit and Waveforms
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
11
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
VO
CL
10 pF
+
500
1.2 V
B
A
RE
Inputs
VTEST
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf
1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500
±
10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
tPZL
VTEST
A
tPZL
tPLZ
2.5 V
1.4 V
VOL +0.5 V
VOL
2 V
1.4 V
0.8 V
2.5 V
1 V
RE
R
tPZH
VTEST
A
tPZH
tPHZ
VOH
1.4 V
VOH 0.5 V
0 V
2 V
1.4 V
0.8 V
0 V
1.4 V
RE
R
Figure 7. Enable/Disable Time Test Circuit and Waveforms
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
12
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
|VID| Differential Input Voltage V
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
1
0
0.1
0.3
2
1.5
0.5
0.2
0.4
0.6
2.5
0
0.5
VCC = 3 V
Common-Mode Input V
oltage V
V
IC
VCC > 3.15 V
MIN
Figure 8
Figure 9
0
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL Low-Level Output Current mA
4
3
0
4
6
2
2
VCC = 3.3 V
TA = 25
°
C
1
V
OL
Low-Level Output V
oltage V
Figure 10
4
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH High-Level Output Current mA
3.5
2.5
0
2
0
1.5
3
0.5
V
OH
High-Level Output V
oltage V
1
3
2
1
VCC = 3.3 V
TA = 25
°
C
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
13
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 11
0
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL Low-Level Output Current mA
5
0
60
2
10
V
OL
20
30
3
1
Low-Level Output V
otlage V
40
50
4
VCC = 3.3 V
TA = 25
°
C
Figure 12
80
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH High-Level Output Current mA
4
0
0
2
60
V
OH
40
20
3
1
High-Level Output V
oltage V
VCC = 3.3 V
TA = 25
°
C
Figure 13
50
DRIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
TA Free-Air Temperature
°
C
2.5
1.5
50
90
2
10
t
PHL
High-T
o-Low Propagation Delay T
ime ns
30
30
70
10
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
Figure 14
50
DRIVER
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
TA Free-Air Temperature
°
C
2.5
1.5
50
90
2
10
t
PLH
Low-T
o-High Propagation Delay T
ime ns
30
30
70
10
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
14
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 15
50
RECEIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
TA FreeAir Temperature
°
C
4.5
2.5
50
90
3.5
10
t
PLH
30
30
70
10
VCC = 3.6 V
VCC = 3 V
4
3
VCC = 3.3 V
High-T
o-Low Level Propagation Dealy T
ime ns
Figure 16
50
RECEIVER
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREEAIR TEMPERATURE
TA Free-Air Temperature
°
C
4.5
2.5
50
90
3.5
10
t
PLH
Low-T
o-High Level Propagation Delay T
ime ns
30
30
70
10
VCC = 3.6 V
VCC = 3 V
4
3
VCC = 3.3 V
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
15
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low commonmode output and balanced interface for very low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the
power and dual supply requirements.
10
0.1
1M
Data Rate Hz
1
100k
10M
100M
100
T
ransmission Distance m
1000
5% Jitter
30% Jitter
24 AWG UTP 96
(PVC Dielectric)
Figure 17. Data Transmission Distance Versus Rate
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
16
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between 100 mV and
100 mV and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how
it handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near V
CC
through 300-k
resistors as shown in Figure 11. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
Rt
100
Typ
300 k
300 k
VCC
VIT
2.3 V
A
B
Y
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
17
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047 / D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0
°
8
°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G APRIL 1998 REVISED MARCH 2000
18
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
0,15 NOM
Gage Plane
4073329/A 02/97
4,98
0,25
5
3,05
4,78
2,95
8
4
3,05
2,95
1
0,38
1,07 MAX
0,15 MIN
Seating Plane
0,65
M
0,25
0
°
6
°
0,10
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
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Copyright
©
2000, Texas Instruments Incorporated
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