ST24LC21B, ST24LW21

ST24FC21, ST24FC21B, ST24FW21

1 Kbit (x8) Dual Mode Serial EEPROM

for VESA PLUG & PLAY

June 2002

1/22

AI01741

SDA

VCC

ST24xy21

VCLK

SCL

VSS

Figure 1. Logic Diagram

1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
3.6V to 5.5V or 2.5V to 5.5V SINGLE SUPPLY
VOLTAGE
HARDWARE WRITE CONTROL (ST24LW21
and ST24FW21)
TTL SCHMITT-TRIGGER on VCLK INPUT
100k / 400k Hz COMPATIBILITY with the I

BUS BIT TRANSFER RANGE
TWO WIRE SERIAL INTERFACE I

C BUS

COMPATIBLE
I

C PAGE WRITE (up to 8 Bytes)

C BYTE, RANDOM and SEQUENTIAL READ

MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ERROR RECOVERY MECHANISM
(ST24FC21 and ST24FW21) VESA 2
COMPATIBLE

DESCRIPTION
The ST24LC21B, ST24LW21, ST24FC21,
ST24FC21B and ST24FW21 are 1K bit electrically
erasable programmable memory (EEPROM), or-
ganized in 128x8 bits. In the text, products are
referred as ST24xy21, where "x" is either "L" for
VESA 1 or "F" for VESA 2 compatible memories
and where "y" indicates the Write Control pin con-
nection: "C" means WC on pin 7 and "W" means
WC on pin 3.

SDA

Serial Data Address Input/Output

SCL

Serial Clock (I

C mode)

Supply Voltage

Ground

VCLK

Clock Transmit only mode

Write Control

Table 1. Signal Names

SO8 (M)

150mil Width

PSDIP8 (B)

0.25mm Frame

Note: WC signal is only available for ST24LW21 and ST24FW21

products.

SDA

VSS

SCL

VCLK

VCC

AI01742

ST24LC21B

Figure 2A. DIP Pin Connections

AI01743

SDA

VSS

SCL

VCLK

VCC

ST24LC21B

Figure 2B. SO Pin Connections

Warning: NC = Not Connected.

SDA

VSS

SCL

VCLK

VCC

AI01744

ST24FC21

ST24FC21B

Figure 2C. DIP Pin Connections

AI01745

SDA

VSS

SCL

VCLK

VCC

ST24FC21

ST24FC21B

Figure 2D. SO Pin Connections

Warning: NC = Not Connected. DU = Don't Use, must
be left open or connected to V

or V

SDA

VSS

SCL

VCLK

VCC

AI01746

ST24FW21
ST24LW21

Figure 2E. DIP Pin Connections

AI01747

SDA

VSS

SCL

VCLK

VCC

ST24FW21
ST24LW21

Figure 2F. SO Pin Connections

Warning: NC = Not Connected.

Warning: NC = Not Connected. DU = Don't Use, must
be left open or connected to V

or V

2/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

�40 to 85

�

STG

Storage Temperature

�65 to 150

�

LEAD

Lead Temperature, Soldering

(SO8 package)
(PSDIP8 package)

40 sec
10 sec

215
260

�

Input or Output Voltages

�0.3 to 6.5

Supply Voltage

�0.3 to 6.5

ESD

Electrostatic Discharge Voltage (Human Body model)

(2)

4000

Electrostatic Discharge Voltage (Machine model)

(3)

500

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500

3. EIAJ IC-121 (Condition C) (200pF, 0

Table 2. Absolute Maximum Ratings

(1)

Device Code

Chip Enable

Bit

Device Select

Note: The MSB b7 is sent first.

X = 0 or 1.

Table 3A. Device Select Code (ST24LC21B, ST24LW21, ST24FC21 and ST24FW21)

The ST24xy21 can operate in two modes: Trans-
mit-Only mode and I

C bidirectional mode. When

powered, the device is in Transmit-Only mode with
EEPROM data clocked out from the rising edge of
the signal applied on VCLK.
The device will switch to the I

C bidirectional mode

upon the falling edge of the signal applied on SCL
pin. When in I

C mode, the ST24LC21B (or the

ST24LW21) cannot switch back to the Transmit
Only mode (except when the power supply is re-
moved). For the ST24FC21, ST24FC21B (or the
ST24FW21), after the falling edge of SCL, the
memory enter in a transition state which allowed to

switch back to the Transmit-Only mode if no valid
I

C activity is observed. Both Plastic Dual-in-Line

and Plastic Small Outline packages are available.
Transmit Only Mode
After a Power-up, the ST24xy21 is in the Transmit
Only mode. A proper initialization sequence (see
Figure 3) must supply nine clock pulses on the
VCLK pin (in order to internally synchronize the
device). During this initialization sequence, the
SDA pin is in high impedance. On the rising edge
of the tenth pulse applied on VCLK pin, the device
will output the first bit of byte located at address 00h
(most significant bit first).

DESCRIPTION (cont'd)

Device Code

Chip Enable

Bit

Device Select

Note: The MSB b7 is sent first.

X = 0 or 1.

Table 3B. Device Select Code (ST24FC21B)

3/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

AI01501

Bit 7

VCC

tVPU

SCL

SDA

VCLK

Bit 6

Bit 7

VCC

SCL

SDA

VCLK

Bit 6

Bit 4

Bit 0

Bit 5

Figure 3. Transmit Only Mode Waveforms

Mode

bit

ST24LC21B

ST24FC21

ST24FC21B

VCLK

ST24LW21
ST24FW21

Bytes

Initial Sequence

Current Address
Read

'1'

START, Device Select, RW = '1'

Random Address
Read

'0'

START, Device Select, RW = '0', Address,

'1'

reSTART, Device Select, RW = '1'

Sequential Read

'1'

1 to 128

Similar to Current or Random Mode

Byte Write

'0'

START, Device Select, RW = '0'

Page Write

'0'

START, Device Select, RW = '0'

Note: X = V

or V

Table 4. I

C Operating Modes

4/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don't Care bit.
As long as the SCL pin is held high, each byte of
the memory array is transmitted serially on the SDA
pin with an automatic address increment.
When the last byte is transmitted, the address
counter will roll-over to location 00h.
I

C Bidirectional Mode

The ST24xy21 can be switched from Transmit Only
mode to I

C Bidirectional mode by applying a valid

high to low transition on the SCL pin (see Figure 4).
� When the ST24LC21B (or the ST24FC21 or

the ST24FC21B) is in the I

C Bidirectional

mode, the VCLK input (pin 7) enables (or inhib-
its) the execution of any write instruction: if
VCLK = 1, write instructions are executed; if
VCLK = 0, write instructions are not executed.

� When the ST24LW21 (or the ST24FW21) is in

the I

C Bidirectional mode, the Write Control

(WC on pin 3) input enables (or inhibits) the
execution of any write instruction: if WC = 1,
write instructions are executed;if WC = 0,
write instructions are not executed.

The ST24xy21 is compatible with the I

C standard,

two wire serial interface which uses a bidirectional
data bus and serial clock. The ST24xy21 carries a
built-in 4 bit, unique device identification code
(1010) named Device Select code corresponding
to the I

C bus definition. The ST24LC21B carries a

unique device identification code (1010.0000 RW)

named Device Select code corresponding to the
I

C bus definition.

The ST24xy21 behaves as a slave device in the
I

C protocol with all memory operations synchro-

nized by the serial clock SCL. Read and write
operations are initiated by a START condition gen-
erated by the bus master. The START condition is
followed by a stream of 7 bits, plus one read/write
bit and terminated by an acknowledge bit.

When data is written into the memory, the
ST24xy21 responds to the 8 bits received by as-
serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it must
acknowledge the receipt of the data bytes in the
same way. Data transfers are terminated with a
STOP condition (see READ and WRITE descrip-
tions in the following pages).

Power On Reset: V

lock out write protect

In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V

voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V

drops down from the

operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V

must be applied before applying any logic signal.

Error Recovery Modes available in the
ST24FC21, ST24FC21B and the ST24FW21

AI01892

SCL

SDA

VCLK

Transmit Only Mode

MSB

ACK

START
CONDITION

- Temporary Bi-Directional Mode
(ST24FC21 and ST24FW21)
- Locked Bi-Directional Mode
(ST24LC21B and ST24LW21)

- Locked Bi-Directional
Mode (ST24FC21
and ST24FW21)

Figure 4. Transition from Transmit Only (DDC1) to Bi-directional (DDC2B) Mode Waveforms

5/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

AI01748

Switch Back to

Transmit-Only Mode

Memory Power On

Internal Address Pointer = 0

VCLK

YES

Send Data bit (MSB first) pointed

by the Address Pointer and

auto-increment pointed bit/byte

SCL

YES

SDA Hi-Z

VCLK Internal Counter = 0

Start Internal 2 sec Timer

SCL

YES

Reset VCLK Internal Counter

and Reset Internal Timer

Valid

C access

(START + Device Select)

YES

VCLK

YES

Increment VCLK Counter

Counter = 128

or Timer > 2 sec

YES

C communication idle

waiting for a Device Select byte

Reset Counter and Timer

Send Acknowledge

Respond to the Incoming

C Command

Transition

State

(VESA 2)

Transmit-Only Mode
(DDC1)

C Mode

(DDC2B)

Figure 5. Error Recovery Mechanism Flowchart for the ST24FC21, ST24FC21B and ST24FW21
products

6/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

AI01665

VCC

CBUS

SDA

MASTER

SCL

CBUS

100

CBUS (pF)

Maximum RP value (k

)

1000

fc = 400kHz

fc = 100kHz

Figure 6. Maximum R

Value versus Bus Capacitance (C

BUS

) for an I

C Bus

When the ST24FC21 (or the ST24FC21B or the
ST24FW21) first switches to the I

C mode (VESA

DDC2B mode), it enters a transition state which is
functionally identical to I

C operation. But, if the

ST24FC21 (or the ST24FC21B or the ST24FW21)
does not receive a valid I

C sequence, that is a

START condition followed by a valid Device Select
c o de ( 10 10X X X RW f o r S T 2 4F C 21 an d
ST24FW21; 1010000 RW for ST24FC21B), within
either 128 VCLK periods or a period of time of
t

RECOVERY

( appr ox imat ely 2 seconds), the

ST24FC21 (or the ST24FC21B or the ST24FW21)
will revert to the Transmit-Only mode (VESA DDC1
mode).
If the ST24FC21 (or the ST24FC21B or the
ST24FW21) decodes a valid I

C Device Select

code, it will lock into I

C mode. Under this condition,

signals applied on the VCLK input will not disturb
READ access from the ST24FC21 (or the
ST24FC21B or the ST24FW21). For WRITE ac-
cess, refer to the Signal Description paragraph.
When in the transition state, the count of VCLK
pulses and the internal 2 seconds timer are reset
by any activity on the SCL line. This means that,
after each high to low transition on SCL, the mem-
ory will re-initialise its transition state and will switch
back to Transmit-Only mode only after 128 more
VCLK pulses or after a new t

RECOVERY

delay.

SIGNAL DESCRIPTIONS

C Serial Clock (SCL). The SCL input pin is used

to synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V

to act as a pull up (see Figure 6).

Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR'ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V

to act as pull up (see Figure 6).

Transmit Only Clock (VCLK). The VCLK input pin
is used to synchronize data out when the ST24xy21
is in Transmit Only mode.

For the ST24LC21B and the ST24FC21 or
ST24FC21B Only, the VCLK offers also a Write
Enable (active high) function when the ST24LC21B
and the ST24FC21 or ST24FC21B are in I

C bidi-

rectional mode.

Write Control (WC). An hardware Write Control
feature (WC) is offered only on ST24LW21 and
ST24FW21 on pin 3. This feature is usefull to
protect the contents of the memory from any erro-
neous erase/write cycle. The Write Control signal
is used to enable (WC = V

) or disable (WC = V

)

the internal write protection. When unconnected,
the WC input is internally tied to V

by a 100k ohm

pull-down resistor and the memory is write pro-
tected.

DEVICE OPERATION

7/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance (SDA)

Input Capacitance (other pins)

Low-pass filter input time constant
(SDA and SCL)

200

500

Note: 1. Sampled only, not 100% tested.

Table 5. Input Parameters

(1)

= 25

�

C, f = 100 kHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

�

Output Leakage Current

OUT

SDA in Hi-Z

�

Supply Current

= 5V, f

= 400kHz

(Rise/Fall time < 10ns)

Supply Current

= 3.6V, f

= 400kHz

CC1

Supply Current (Standby)

= V

or V

= 5V, f

= 0

100

�

= V

or V

= 5V, f

= 400kHz

300

�

CC2

Supply Current (Standby)

= V

or V

= 3.6V, f

= 0

�

= V

or V

= 3.6V, f

= 400kHz

100

�

Input Low Voltage
(SCL, SDA, WC)

�0.3

0.3 V

Input High Voltage
(SCL, SDA, WC)

0.7 V

+ 1

High Level Threshold Voltage
(Schmitt Trigger on VLCK)

= 5.5V

1.4

2.1

= 4.5V

1.2

1.9

= 3.6V

1.7

Low Level Threshold Voltage
(Schmitt Trigger on VLCK)

= 5.5V

0.6

1.4

= 4.5V

0.5

1.2

= 3.6V

0.4

Hysteresis Voltage
(Schmitt Trigger on VLCK)

= 5.5V

0.4

1.5

= 4.5V

0.4

1.4

= 3.6V

0.35

1.3

Output Low Voltage

= 3mA, V

= 3.6V

0.4

= 6mA, V

= 5V

0.6

Table 6A. DC Characteristics (ST24LC21B, ST24LW21, ST24FC21 and ST24FW21)
(T

= �40 to 85

�

C; V

= 3.6V to 5.5V)

8/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Symbol

Parameter

Test Condition

Min

(1)

Max

(1)

Unit

Input Leakage Current

�

Output Leakage Current

OUT

SDA in Hi-Z

�

Supply Current

= 5V, f

= 400kHz

(Rise/Fall time < 10ns)

Supply Current

= 2.5V, f

= 400kHz

CC1

Supply Current (Standby)

= V

or V

= 5V, f

= 0

100

�

= V

or V

= 5V, f

= 400kHz

300

�

CC2

Supply Current (Standby)

= V

or V

= 2.5V, f

= 0

�

= V

or V

= 2.5V, f

= 400kHz

100

�

Input Low Voltage
(SCL, SDA, WC)

�0.3

0.3 V

Input High Voltage
(SCL, SDA, WC)

0.7 V

+ 1

High Level Threshold Voltage
(Schmitt Trigger on VLCK)

= 5.0V

1.2

1.9

= 2.5V

0.8

1.4

Low Level Threshold Voltage
(Schmitt Trigger on VLCK)

= 5.0V

0.6

1.7

= 2.5V

0.5

1.1

Output Low Voltage

= 2.1mA, V

= 2.5V

0.4

= 6mA, V

= 5V

0.6

Note 1: Preliminary results.

Table 6B. DC Characteristics (ST24FC21B)
(T

= �40 to 85

�

C; V

= 2.5 to 5.5V)

9/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Symbol

Alt

Parameter

Min

Max

Unit

CH1CH2

(1)

Clock Rise Time

300

CL1CL2

(1)

Clock Fall Time

300

DH1DH2

(1)

SDA Rise Time

300

DL1DL2

(1)

SDA Fall Time

300

CHDX

(2)

SU:STA

Clock High to Input Transition

600

CHCL

HIGH

Clock Pulse Width High

600

DLCL

HD:STA

Input Low to Clock Low (START)

600

CLDX

HD:DAT

Clock Low to Input Transition

�

CLCH

LOW

Clock Pulse Width Low

1.3

�

DXCX

SU:DAT

Input Transition to Clock Transition

100

CHDH

SU:STO

Clock High to Input High (STOP)

600

DHDL

BUF

Input High to Input Low (Bus Free)

1.3

�

CLQV

Clock Low to Data Out Valid

200

900

CLQX

Clock Low to Data Out Transition

200

SCL

Clock Frequency

400

kHz

Write Time

Notes: 1. Sampled only, not 100% tested.

2. For a reSTART condition, or following a write cycle.

Table 7. AC Characteristics, I

C Bidirectional Mode for Clock Frequency = 400kHz

= �40 to 85

�

C; V

= 3.6 to 5.5V or V

= 2.5 to 5.5V)

C Bus Background

The ST24xy21 supports the I

C protocol. This pro-

tocol defines any device that sends data onto the
bus as a transmitter and any device that reads the
data as a receiver. The device that controls the data
transfer is known as the master and the other as
the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24xy21 are always slave de-
vices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24xy21 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are not executing a START condition if
this START condition happens at any time inside a
byte. The ST24FC21B executes a START condi-
tion when this START condition happens at any
time inside a byte.

Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24xy21 and
the bus master. A STOP condition at the end of a
Read command (after the No ACK) forces the
standby state. A STOP condition at the end of a
Write command triggers the internal EEPROM
write cycle.

The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are not executing a STOP condition if
this STOP condition happens at any time inside a
byte. The ST24FC21B executes a STOP condition
when this STOP condition happens at any time
inside a byte.

Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.

Data Input. During data input, the ST24xy21 sam-
ple the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation

10/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Symbol

Alt

Parameter

Min

Max

Unit

CH1CH2

Clock Rise Time

�

CL1CL2

Clock Fall Time

300

DH1DH2

Input Rise Time

�

DL1DL1

Input Fall Time

300

CHDX

(1)

SU:STA

Clock High to Input Transition

4.7

�

CHCL

HIGH

Clock Pulse Width High

�

DLCL

HD:STA

Input Low to Clock Low (START)

�

CLDX

HD:DAT

Clock Low to Input Transition

�

CLCH

LOW

Clock Pulse Width Low

4.7

�

DXCX

SU:DAT

Input Transition to Clock Transition

250

CHDH

SU:STO

Clock High to Input High (STOP)

4.7

�

DHDL

BUF

Input High to Input Low (Bus Free)

4.7

�

CLQV

(2)

Clock Low to Next Data Out Valid

0.2

3.5

�

CLQX

Data Out Hold Time

200

SCL

Clock Frequency

100

kHz

Write Time

Notes: 1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP

conditions.

Table 8. AC Characteristics, I

C Bidirectional Mode for Clock Frequency = 100kHz

= �40 to 85

�

C; V

= 3.6V to 5.5V)

Symbol

Alt

Parameter

Min

Max

Unit

VCHQX

VAA

Output Valid from VCLK

500

VCHVCL

VHIGH

VCLK High Time

600

VCLVCH

VLOW

VCLK Low Time

1.3

�

CLQZ

VHZ

Mode Tansition Time

500

VPU

(1,2)

Transmit-only Power-up Time

VH1VH2

(2)

VCLK Rise Time

�

VL1VL2

(2)

VCLK Fall Time

�

RECOVERY

(2)

Recovery Time

1.5

3.5

sec

Notes: 1. Refer to Figure 3.

2. Sampled only, not 100% tested.

Table 9. AC Characteristics, Transmit-only Mode
(T

= �40 to 85

�

C; V

= 3.6V to 5.5V)

11/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

the SDA signal must be stable during the clock low
to high transition and the data must change ONLY
when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24xy21, the
master must initiate a START condition. Following
this, the master sends onto the SDA bus line 8 bits
(MSB first) corresponding to the Device Select
code (7 bits) and a READ or WRITE bit. The 4 most
significant bits of the Device Select code are the
device type identifier, corresponding to the I

C bus

definition. For these memories the 4 bits are fixed
as 1010b. The 8th bit sent is the read or write bit
(RW), this bit is set to '1' for read and '0' for write
operations. If a match is found, the corresponding

memory will acknowledge the identification on the
SDA bus during the 9th bit time.

Write Operations

Following a START condition the master sends a
Device Select code with the RW bit set to '0'. The
memory acknowledges this and waits for a byte
address. After receipt of the byte address the de-
vice again responds with an acknowledge.

In I

C bidirectional mode, any write command with

VCLK=0 (for the ST24LC21B and ST24FC21,
ST24FC21B) or with WC=0 (for the ST24LW21 and
ST24FW21) will not modify data and will be ac-
knowledged on data bytes, as shown in Figure 12.

Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the

WRITE Cycle

in Progress

AI01099B

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction
with RW = 0 already
decoded by ST24xxx

Figure 10. Write Cycle Polling using ACK

14/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

memory. The master then terminates the transfer
by generating a STOP condition.

Page Write. The Page Write mode allows up to 8
bytes to be written in a single write cycle, provided
that they are all located in the same 'row' in the
memory: that is the most significant memory ad-
dress bits are the same. The master sends from
one up to 8 bytes of data, which are each acknow-
ledged by the memory.

After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter 'roll-over' which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the

STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t

) is given in the

AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master. The sequence is as follows:
� Initial condition: a Write is in progress (see Fig-

ure 10).

STOP

START

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

START

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01893

STOP

DATA IN N

ACK

R/W

ACK

R/W

ACK

VCLK/WC

Figure 11. Write Modes Sequence

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

STOP

START

BYTE WRITE

CONTROL

BYTE

WORD ADDR

DATA

START

PAGE WRITE

WORD ADD n

DATA n

DATA n + 1

AI01894

ACK

VCLK/WC

CONTROL

BYTE

DATA n + 7

STOP

ACK

Figure 12. Inhibited Write when VCLK/WC = 0

� Step 1: the Master issues a START condition

followed by a Device Select byte (1st byte of
the new instruction).

� Step 2: if the memory is busy with the internal

write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the mem-
ory is ready to receive the second part of the
instruction (the first byte of this instruction was
already sent during Step 1).

Read Operations

On delivery, the memory content is set at all "1's"
(or FFh).

Current Address Read. The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends the Device Select code with the
RW bit set to '1'. The memory acknowledges this
and outputs the data byte addressed by the internal
byte address counter. This counter is then incre-
mented. The master must NOT acknowledge the
data byte output and terminates the transfer with a
STOP condition.

Random Address Read. A dummy write is per-
formed to load the address into the address
counter, see Figure 14. This is followed by a Re-
START condition send by the master and the De-
vice Select code is repeated with the RW bit set to
'1'. The memory acknowledges this and outputs the
addressed data byte. The master must NOT ac-
knowledge the data byte output and terminates the
transfer with a STOP condition.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last data byte
output, and MUST generate a STOP condition.
The output data is from consecutive byte ad-
dresses, with the internal byte address counter
automatically incremented after each byte output.
After a count of the last memory address, the
address counter will 'roll-over' and the memory will
continue to output data.
Acknowledge in Read Mode. In all read modes
the ST24xy21 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

AI01749

VSync

100nF

47k

+5V

SCL

SDA

+5V Monitor

VCLK

SCL

SDA

VSS

VCC

MONITOR

HOST

VGA Cable

Figure 13. Recommended Schematic for VESA 2.0 Specification

low during this time, the ST24xy21 terminate the
data transfer and switches to a standby state.

NOTE CONCERNING THE POWER SUPPLY
VOLTAGE IN THE VESA 2.0 SPECIFICATION

According to the VESA 2.0 specification, the
ST24xy21 can be supplied by either the MONITOR
or by the HOST (using +5V on the VGA cable pin
9) power supply. The easyest way to implement this
is to use 2 diodes as described in the following

schematic. The ST24xy21 supply voltage will be
decreased by 0.6V, which is the diode forward
voltage drop, and will be below 4.5V. Nevertheless,
the ST24xy21 remains operational and no input will
be damaged if the applied voltage on any input
complies with the Absolute Maximum Ratings val-
ues.
Under this condition, the threshold voltage of the
Schmitt-Trigger (pin 7) will be decreased (as in
Table 6).

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Family Range

ST24LC21B

VESA 1
WC on pin 7

ST24LW21

VESA 1
WC on pin 3

ST24FC21

VESA 2
WC on pin 7
Device Select=1010.xxx

ST24FC21B

VESA 2, 2.5V
WC on pin 7
Device Select=1010.000

ST24FW21

VESA 2
WC on pin 3

Package

PSDIP8
0.25mm Frame

SO8
150mil Width

Temperature Range

0 to 70

�

�40 to 85

�

Option

TR Tape & Reel

Packing

Example: ST24LC21B M 1 TR

ORDERING INFORMATION SCHEME

Devices are shipped from the factory with the memory content set at all "1's" (FFh).

For a list of available options (Package, etc...) or for further information on any aspect of this device, please
contact the STMicroelectronics Sales Office nearest to you.

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Information furnished is believed to be accurate and reliable. However, STMicroelectroni cs assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

All other names are the property of their respective owners

Purchase of I

C Components by STMicroelectronics, conveys a license under the Philips

C Patent. Rights to use these components in an I

C system, is granted provided that the system conforms to

the I

C Standard Specifications as defined by Philips.

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ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Part Number ST24FC21