Document Outline

• SS1103C Single-Chip Spread Spectrum Processor
• for
• Digital Cordless Phone External Specification
  • 1. General
  • 2. Main Features
    • 2.1. System Controller Functions
    • 2.2. Peripheral Controller Functions
    • 2.3. Baseband Module
    • 2.4. RF Device Interface
    • 2.5. Voice Module
  • 3. Pin Descriptions
    • 3.1. Spread Spectrum Transceiver Module
      • TABLE 1. Transceiver module pins
    • 3.2. RF Interface
      • TABLE 2. RF interface pins
    • 3.3. Serial Peripheral Interface
      • TABLE 3. Serial Peripheral Interface pins
    • 3.4. Serial I/O
    • 3.5. Voice Module
      • TABLE 4. Voice interface pins
    • 3.6. UART
      • TABLE 5. Base / Hanset control pins
    • 3.7. Keypad Control
      • TABLE 6. Key pad I/O pins
    • 3.8. Power Supply
      • TABLE 7. Power supply pins
    • 3.9. Miscellaneous
      • TABLE 8. Miscellaneous pins
  • 4. CPU
  • 5. Memory Organization
    • 5.1. Data Memory
    • 5.2. Program Memory
    • 5.3. EXTERNAL MEMORY MODE
  • 6. Special Function Registers
    • 6.1. Stack Pointer (SP)
    • 6.2. Data Pointer (DPTR)
    • 6.3. Program Status Word (PSW)
    • 6.4. Accumulator (ACC)
    • 6.5. B Register (B)
    • 6.6. Memory Size Register (MSIZ)
  • 7. Port Definition
    • 7.1. Overview
    • 7.2. Read-Modify-Write Feature
    • 7.3. PCR (Port Control Register)
    • 7.4. ZCR (Hi-Z Control Register)
    • 7.5. PAD Cell
    • 7.6. P0 (Port-0)
    • 7.7. P2 (Port-2)
    • 7.8. P1 (Port-1)
    • 7.9. P3 (Port-3)
    • 7.10. P.4 (Port-4)
      • 7.10.1 Overview
  • 8. Interrupt Control Block
    • 8.1. Overview
    • 8.2. External Interrupts
      • 8.2.1 Overview
      • 8.2.2 External Interrupt Control Register (XICR0)
    • 8.3. Interrupt Request Registers (INT0, INT1, INT2)
    • 8.4. Interrupt Source Enable Registers (ISE0, ISE1, ISE2)
    • 8.5. Interrupt Group Enable Register (IE)
    • 8.6. Interrupt Priority Register (IP)
    • 8.7. Interrupt Processing
  • 9. Power-Saving Modes
    • 9.1. Overview
    • 9.2. Mode Definition and Transition
      • 9.2.1 FastAll mode (a Clocking Mode)
      • 9.2.2 SlowAll mode (a Clocking Mode)
      • 9.2.3 StopAll mode (a Clocking Mode)
      • 9.2.4 FastPeri mode (a Clocking Mode)
      • 9.2.5 SlowPeri mode (a Clocking Mode)
      • 9.2.6 NorPin mode (a Pin State Mode)
      • 9.2.7 HIZ mode (a Pin State Mode)
    • 9.3. Power-Saving Control Register (PSCR)
    • 9.4. Stop Release Register (SREL)
  • 10. Direct Sequence Spread Spectrum Baseband Modem (SSTM)
    • 10.1. General
      • 10.1.1 Receiver
      • 10.1.2 Transmitter
      • 10.1.3 TDD Controller
      • 10.1.4 FIFOs
      • 10.1.5 Master Clock Generator
    • 10.2. Voice Full-Duplex Operation
    • 10.3. TDD Protocol
      • Burst Frame Structures
      • Receiver Lock State Machine
    • 10.4. System Delay
      • System Delay
    • 10.5. Timing Information
      • Typical Communication Link Start-Up. Full Duplex.
    • 10.6. Control Registers
    • 10.7. Configuration Information Bits and Registers Description
    • 10.8. Programming the SSTM
      • 10.8.1 Overview
      • 10.8.2 Read/Write the Signaling Word
      • 10.8.3 Read the S/N Ratio
      • 10.8.4 Error Detection and Control
      • 10.8.5 SSTM Parameters
  • 11. Voice Module
    • 11.1. General
    • 11.2. Control Registers
      • 11.2.1 VMINTCR Description
        • TABLE 9.
      • 11.2.2 Codec Eight Control Registers Index Table
        • TABLE 10. Control Registers Index
      • 11.2.3 Eight Control Registers Description
        • 1. Control Register 0
        • 2. Control Register 1 (ADPCM Coder/Decoder Setting)
        • 3. Control Register 2 PCM Block&Tx-Rx Gain Control Settigns
        • 4. Control Register 3 Side Tone and Tone Generator Control
        • 5. Control Register 4
        • 6. Control Register 5
        • 7. Control Register 6. VOX Control
        • 8. Control Register 7
    • 11.3. Serial Interface to the Eight CRs
    • 11.4. Voice Analog Circuits Interface
      • Figure 1. Voice Analog Interface Circuits
    • 11.5. Reset and Power Down
    • 11.6. VOX system
      • 11.6.1 General
      • 11.6.2 AC Characteristics
  • 12. RF Modue Interface
    • 12.1. SSTM RF Interface
      • PLLSW Timing (Full-Duplex Mode)
    • 12.2. Gain Control Module (GCM)
      • 12.2.1 Overview
      • 12.2.2 Digital to Analog Converter Specification
      • 12.2.3 Gain Control Module Control Register
    • 12.3. RSSI ADC Module
      • 12.3.1 Overview
      • 12.3.2 ADC Control Register
      • 12.3.3 ADC Data Register
    • 12.4. DI Comparator
      • 12.4.1 General Information
      • 12.4.2 Functional Description
        • TABLE 11. DI Comparator features
          • Figure 2. DI Comparator block diagram
      • 12.4.3 Comparator I/O signal names and descriptions
      • 12.4.4 Timing diagrams
        • Figure 3. Power-down register timing
        • Figure 4. Comparator output register timing
      • 12.4.5 Comparator I/O plot
        • Figure 5. DI Comparator plot
      • 12.4.6 Comparator Control Register
  • 13. Serial I/O Module
    • 13.1. Overview
    • 13.2. 8-bit Serial-Output Mode
    • 13.3. 8-bit Serial-Input Mode
    • 13.4. 8-bit Serial-I/O Mode
    • 13.5. SIO Control Register (SIOCR)
    • 13.6. SIO Shift Register (SIODAT)
    • 13.7. SIO Module Functional Description
      • 13.7.1 Serial In
      • 13.7.2 Serial Out
      • 13.7.3 Serial-I/O
      • 13.7.4 Voice Module Control
  • 14. SPI (Serial Peripheral Interface)
    • 14.1. Overview
    • 14.2. SPI Pin Description
    • 14.3. SPI Operation
    • 14.4. Serial Peripheral Control Register (SPI1CR)
    • 14.5. Serial Peripheral Status Register (SPI1SR)
    • 14.6. SPI Data Register (SPI1DAT)
  • 15. Universal Asynchronous Receiver Transmitter (UART)
    • 15.1. Features
    • 15.2. Baud Rate and UartTimer Matching Value
      • 15.2.1 For UART Mode 1 and Mode 3
        • TABLE 12.
      • 15.2.2 For UART Mode 0
      • 15.2.3 For UART Mode 2
    • 15.3. UART Control Register
      • TABLE 13.
    • 15.4. UART Counter Matching Register
  • 16. Keypad Control
    • 16.1. Overview
    • 16.2. Keypad Control Register
  • 17. Dial Pulse Generation
    • 17.1. General
    • 17.2. Pulse Dialing
    • 17.3. Flash Output Control
    • 17.4. DTMF Timing Control
    • 17.5. Mute Signals
    • 17.6. Dial Pulse/Flash Control Register
    • 17.7. Dial Pulse/Flash Data Register
    • 17.8. Dial Pulse/Flash Counter Register
  • 18. WatchDog Timer
    • 18.0.1 Overview
      • Figure 6. Watchdog timer block diagram
  • 19. Time Base Timer
    • 19.1. Overview
      • Figure 7. Time Base timer
    • 19.2. Time Base Timer Control Register (TBCR)
    • 19.3. TB-Timer Counter Register (TBCNT)
    • 19.4. TB-Timer Data Register (TBDAT)
  • 20. General Purpose Timer
    • 20.1. Overview
    • 20.2. Auto-Reload Mode
    • 20.3. Genral Purpose Timer Control Registers (CT2CR)
    • 20.4. C-Timer Counter Registers (CT2CH & CT2CL)
    • 20.5. C-Timer Data Register (CT2DH & CT2DL)
  • 21. SS1103 Reset
    • 21.1. Overview
    • 21.2. Power-On Reset (POR)
      • 21.2.1 General
      • 21.2.2 Operation
      • 21.2.3 Crystal Oscillator Start-Up Time
        • Figure 8. External Reset Asserted
        • Figure 9. Internal Reset Asserted (Nreset tied to Vcc)
        • Figure 10. Power On Reset functional diagram
  • 22. Low Battery Detect Module
    • 22.1. Oveview
    • 22.2. Low Battery Detect Module Control Register (LBDCR)