AIMM
M832G0115AP0
- 3 -
Rev. 1.0 (Jul. 2000)
The Samsung M832G0115AP is a 1M bit x 32 Synchro-
nous Graphic RAM based AGP in-line memory module.
The Samsung M832G0115AP consists of one 1M x 32 bit
Synchronous Graphic RAMs in 100pin QFP packages
mounted on a 132pin glass-epoxy substrate. The
M832G0115AP is a AGP In-line Memory Module and is
intended for mounting into 132-pin edge connector sock-
ets(AGP socket).
Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on
every clock cycle. Range of operating frequencies, pro-
grammable latencies and burst lengths allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
FEATURE
GENERAL DESCRIPTION
M832G0115AP0 SGRAM AGP In-Line Memory Module
1Mx32 SGRAM AIMM based on 1Mx32, 2K Refresh, 3.3V Synchronous Graphic RAMs
SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.
·
Performance range
* M832G0115AP0 : based on PQFP Component
· Burst Mode Operation
· Independent byte operation via DQM0 ~ 3
· Auto & Self Refresh Capability (2048 cycles / 32ms)
· LVTTL compatible inputs and outputs
· Single 3.3V
±
0.3V power supply
· MRS cycle with address key programs.
CAS Latency (2, 3)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
· Resistor Strapping Options for speed
· PCB : Height 1,400mil, single sided components
Part NO.
Frequency (t
CC
min)
M832G0115AP0-C7C
133MHz (7.5ns) @CL=2, tRCD/tRP=2CLK
M832G0115AP0-C70
133MHz (7.0ns) @CL=3, tRCD/tRP=3CLK
PIN CONFIGURATIONS (B Side / A Side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
B
NC
NC
NC
NC
GND
NC
NC
DQ27
Vcc
DQ28
DQ29
DQ30
GND
NC
DQ31
Vcc
DQM2
NC
GND
DQ23
DQ22
KEYWAY
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A
NC
TYPEDET
NC
NC
GND
NC
NC
NC
Vcc
DQM3
NC
DQ24
GND
NC
DQ25
Vcc
DQ26
NC
GND
WE
FSEL
KEYWAY
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
B
KEYWAY
KEYWAY
KEYWAY
DQ21
DQ20
Vcc
DQ19
DQ18
GND
NC
DQ17
V
DDQ
DQ16
DQ15
GND
DQ14
DQ13
V
DDQ
DQ12
NC
GND
NC
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A
KEYWAY
KEYWAY
KEYWAY
CLK0
CLK1*
Vcc
CAS
NC
GND
NC
RAS
V
DDQ
A0
A9
GND
A11
A10
V
DDQ
A8/AP*
NC
GND
NC
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
B
V
CC
DQ11
V
DDQ
NC
GND
NC
DQ10
V
DDQ
DQ9
DQ8
GND
DQM1
DQ0
V
DDQ
NC
DQ1
GND
DQ2
DQ3
V
DDQ
DQ4
NC
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
A
Vcc
A7
CS
NC
GND
A6
A1
V
DDQ
A5
A2
GND
A4
A3
V
DDQ
NC
DQ5
GND
DQ6
DQ7
V
DDQ
DQM0
NC
MODULE PIN NAMES
* These pins are not used in this module
and should be NC
Pin Name
Function
A0~A10
Address Input (multiplexed)
A11
SDRAM Bank Select (BA)
DQ0 ~ DQ31
Data Inputs / Outputs
CLK0,CLK1*
Clock Input
CS
Chip Select Input
CKE
CLK Enable
RAS
Row Address Storbe
CAS
Colume Address Strobe
WE
Write Enable
DQM
DQ Mask Enable
V
cc
Power Supply
V
ddq
Power supply for Data In/Out
GND
Ground(Vss)
NC
No Connection
KEYWAY*
KEYWAY
FSEL*
Memory Frequency Select
TYPEDET*
TYPEDET
AIMM
M832G0115AP0
- 4 -
Rev. 1.0 (Jul. 2000)
COMPONENT PIN CONFIGURATION DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t
SS
prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
10
, Column address : CA
0
~ CA
7
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
DQMi
Data Input/Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
DQi
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
DSF
Define Special Function
Not used. Must Connected to low
V
DD
/V
SS
Power Supply /Ground
Power Supply : +3.3V
±
0.3V/Ground
V
DDQ
/V
SSQ
Data Output Power /Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
N.C
No Connection
No connection
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