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DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF40160B
MSI
4-bit synchronous decade counter
with asynchronous reset
For a complete data sheet, please also download:
·
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
·
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
DESCRIPTION
The HEF40160B is a fully synchronous edge-triggered
4-bit decade counter with a clock input (CP), an overriding
asynchronous master reset (MR), four parallel data inputs
(P
0
to P
3
), three synchronous mode control inputs (parallel
enable (PE), count enable parallel (CEP) and count enable
trickle (CET)), buffered outputs from all four bit positions
(O
0
to O
3
) and a terminal count output (TC).
Operation is fully synchronous (except for the MR input)
and occurs on the LOW to HIGH transition of CP. When
PE is LOW, the next LOW to HIGH transition of CP loads
data into the counter from P
0
to P
3
regardless of the levels
of CEP and CET inputs.
When PE is HIGH, the next LOW to HIGH transition of CP
advances the counter to its next state only if both CEP and
CET are HIGH; otherwise, no change occurs in the state
of the counter. TC is HIGH when the state of the counter is
9 (O
0
= O
3
= HIGH, O
1
= O
2
= LOW) and when CET is
HIGH. A LOW on MR sets all outputs (O
0
to O
3
and TC)
LOW, independent of the state of all other inputs.
Multistage synchronous counting is possible without
additional components by using a carry look-ahead
counting technique; in this case, TC is used to enable
successive cascaded stages. CEP, CET and PE must be
stable only during the set-up time before the LOW to HIGH
transition of CP.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
January 1995
3
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
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Fig.2 Logic diagram.
January 1995
4
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
Fig.3 Pinning diagram.
PINNING
PE
parallel enable input
P
0
to P
3
parallel data inputs
CEP
count enable parallel input
CET
count enable trickle input
CP
clock input (LOW to HIGH, edge-triggered)
MR
master reset input (active LOW)
O
0
to O
3
parallel outputs
TC
terminal count output
HEF40160BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF40160BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40160BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
SYNCHRONOUS MODE SELECTION
Notes
1. MR = HIGH
2. H = HIGH state (the more positive voltage)
3. L = LOW state (the less positive voltage)
4. X = state is immaterial
PE
CEP
CET
MODE
L
X
X
preset
H
L
X
no change
H
X
L
no change
H
H
H
count
TERMINAL COUNT GENERATION
Note
1. TC = CET
.
O
0
.
O
1
.
O
2
.
O
3
CET
(O
0
O
1
O
2
O
3
)
TC
L
L
L
L
H
L
H
L
L
H
H
H
Fig.4 State diagram.
January 1995
5
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°
C; input transition times
20 ns
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°
C; C
L
= 50 pF; input transition times
20 ns
V
DD
V
TYPICAL FORMULA FOR P (
µ
W)
Dynamic power
5
1 200 f
i
+
(f
o
C
L
)
Ч
V
DD
2
where
dissipation per
10
5 600 f
i
+
(f
o
C
L
)
Ч
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
16 000 f
i
+
(f
o
C
L
)
Ч
V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP
O
n
5
110
220
ns
83 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
45
90
ns
34 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
5
115
230
ns
88 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
45
95
ns
34 ns
+
(0,23 ns/pF) C
L
15
35
65
ns
27 ns
+
(0,16 ns/pF) C
L
CP
TC
5
130
260
ns
103 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
55
105
ns
44 ns
+
(0,23 ns/pF) C
L
15
35
75
ns
27 ns
+
(0,16 ns/pF) C
L
5
140
280
ns
113 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
55
115
ns
44 ns
+
(0,23 ns/pF) C
L
15
40
80
ns
32 ns
+
(0,16 ns/pF) C
L
CET
TC
5
105
210
ns
78 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
50
100
ns
39 ns
+
(0,23 ns/pF) C
L
15
35
75
ns
27 ns
+
(0,16 ns/pF) C
L
5
90
185
ns
63 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
35
70
ns
24 ns
+
(0,23 ns/pF) C
L
15
25
50
ns
17 ns
+
(0,16 ns/pF) C
L
MR
O
n
5
120
245
ns
93 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
50
100
ns
39 ns
+
(0,23 ns/pF) C
L
15
35
70
ns
27 ns
+
(0,16 ns/pF) C
L
MR
TC
5
145
295
ns
118 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
60
120
ns
49 ns
+
(0,23 ns/pF) C
L
15
45
85
ns
37 ns
+
(0,16 ns/pF) C
L
January 1995
6
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°
C; C
L
= 50 pF; input transition times
20 ns
Output transition times
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
HIGH to LOW
10
t
THL
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
LOW to HIGH
10
t
TLH
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
Minimum clock
5
100
50
ns
see also waveforms
Figs 5, 6, 7 and 8
pulse width; LOW
10
t
WCPL
40
20
ns
15
30
15
ns
Minimum MR
5
100
50
ns
pulse width; LOW
10
t
WMRL
40
20
ns
15
30
15
ns
Recovery time
5
25
0
ns
for MR
10
t
RMR
15
0
ns
15
10
0
ns
Set-up times
5
110
55
ns
P
n
CP
10
t
su
40
20
ns
15
30
15
ns
5
120
60
ns
PE
CP
10
t
su
40
20
ns
15
25
10
ns
5
260
130
ns
CEP, CET
CP
10
t
su
100
50
ns
15
70
35
ns
Hold times
5
20
-
35
ns
P
n
CP
10
t
hold
10
-
10
ns
15
5
-
10
ns
5
15
-
45
ns
PE
CP
10
t
hold
5
-
15
ns
15
5
-
10
ns
5
25
-
105
ns
CEP, CET
CP
10
t
hold
15
-
35
ns
15
10
-
25
ns
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
January 1995
7
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
Maximum clock
5
2,5
5
MHz
pulse frequency
10
f
max
7
14
MHz
15
9
18
MHz
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
Fig.5
Waveforms showing
minimum CP and MR pulse
widths and MR to CP
recovery time.
Conditions
PE = LOW
P
0
to P
3
= HIGH
Fig.6
Waveforms
showing
set-up times
and hold times
for CEP and
CET inputs.
Conditions: PE = MR = HIGH.
January 1995
8
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
Note
Set-up and hold times are shown as positive values but may be specified as negative values.
Fig.7 Waveforms showing set-up times and hold times for P
n
inputs.
Conditions
PE = LOW
MR = HIGH
Fig.8 Waveforms showing set-up times and hold times for PE inputs.
Condition
MR = HIGH
January 1995
9
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
APPLICATION INFORMATION
An example of an application for the HEF40160B is:
·
Programmable decade counter.
Fig.9 Timing diagram.
January 1995
10
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
Fig.10 Synchronous multi-stage counting scheme.
NOTE
On the TC outputs, glitches can occur
during counting. In totally synchronous
mode they will not have any adverse
affect. However the TC output in
asynchronous mode can cause
problems.
Document Outline
- DESCRIPTION
- FAMILY DATA, IDD LIMITS category MSI
- PINNING
- SYNCHRONOUS MODE SELECTION
- TERMINAL COUNT GENERATION
- AC CHARACTERISTICS
- APPLICATION INFORMATION
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