©
Semiconductor Components Industries, LLC, 2003
May, 2003 - Rev. 12
1
Publication Order Number:
NBSG16/D
NBSG16
2.5V/3.3V SiGe Differential
Receiver/Driver with
RSECL* Outputs
*Reduced Swing ECL
The NBSG16 is a differential receiver/driver targeted for high
frequency applications. The device is functionally equivalent to the
EP16 and LVEP16 devices with much higher bandwidth and lower
EMI capabilities.
Inputs incorporate internal 50
W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), HSTL, LVTTL,
LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing
ECL), 400 mV.
The V
BB
and V
MM
pins are internally generated voltage supplies
available to this device only. The V
BB
is used as a reference voltage
for single-ended NECL or PECL inputs and the V
MM
pin is used as a
reference voltage for LVCMOS inputs. For all single-ended input
conditions, the unused complementary differential input is connected
to V
BB
or V
MM
as a switching reference voltage. V
BB
or V
MM
may
also rebias AC coupled inputs. When used, decouple V
BB
and V
MM
via a 0.01
mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
and V
MM
outputs should be left open.
·
Maximum Input Clock Frequency > 12 GHz Typical
·
Maximum Input Data Rate > 12 Gb/s Typical
·
120 ps Typical Propagation Delay
·
40 ps Typical Rise and Fall Times
·
RSPECL Output with Operating Range: V
CC
= 2.375 V to 3.465 V
with V
EE
= 0 V
·
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= -2.375 V to -3.465 V
·
RSECL Output Level (400 mV Peak-to-Peak Output), Differential
Output Only
·
50
W Internal Input Termination Resistors
·
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
·
V
BB
and V
MM
Reference Voltage Output
Device
Package
Shipping
ORDERING INFORMATION
NBSG16BA
4x4 mm
FCBGA-16
100 Units/Tray
NBSG16BAR2
4x4 mm
FCBGA-16
500/Tape & Reel
Board
Description
NBSG16BAEVB
NBSG16BA Evaluation Board
http://onsemi.com
NBSG16MN
3x3 mm
QFN-16
123 Units/Rail
NBSG16MNR2
3x3 mm
QFN-16
3000/Tape & Reel
*For further details, refer to Application Note
AND8002/D
FCBGA-16
BA SUFFIX
CASE 489
MARKING
DIAGRAM*
SG
16
LYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
SG16
ALYW
QFN-16
MN SUFFIX
CASE 485G
NBSG16
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2
Figure 1. BGA-16 Pinout (Top View)
V
EE
D
D
VTD
V
EE
V
BB
VTD
NC
NC
V
EE
V
CC
V
CC
V
MM
V
EE
Q
Q
A
B
C
D
1
2
3
4
V
EE
NC
NC
V
EE
V
EE
V
BB
V
MM
V
EE
V
CC
Q
Q
V
CC
VTD
D
D
VTD
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG16
Exposed Pad (EP)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
Description
C2
1
VTD
-
Internal 50
W
Termination Pin. See Table 2.
C1
2
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 k
W
to V
EE
and 36.5 k
W
to V
CC
.
B1
3
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted differential input. Internal 75 k
W
to V
EE
.
B2
4
VTD
-
Internal 50
W
Termination Pin. See Table 2.
A1,D1,A4,
D4
5,8,13,16
V
EE
-
Negative Supply Voltage
A2,A3
6,7
NC
-
No Connect
B3,C3
9,12
V
CC
-
Positive Supply Voltage
B4
10
Q
RSECL Output
Noninverted Differential Output. Typically Terminated with 50
W
to
V
TT
= V
CC
- 2 V
C4
11
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50
W
to V
TT
= V
CC
- 2 V
D3
14
V
MM
-
LVCMOS Reference Voltage Output. (V
CC
- V
EE
)/2
D2
15
V
BB
-
ECL Reference Voltage Output
N/A
-
EP
-
Exposed Pad. (Note 2)
1. The NC pins are electrically connected to the die and MUST be left open.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat-sinking conduit.
3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self-oscillation.
NBSG16
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3
50
W
50
W
VTD
D
D
VTD
V
MM
Q
Q
V
BB
V
EE
V
CC
Figure 3. Logic Diagram
75 k
W
75 k
W
36.5
KW
Table 2. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTD and VTD to V
CC
LVDS
Connect VTD and VTD together
AC-COUPLED
Bias VTD and VTD Inputs within (V
IHCMR
)
Common Mode Range
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL
The external voltage should be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL.
LVCMOS
V
MM
should be connected to the unused
complementary differential input.
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4
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor (D, D)
75 k
W
Internal Input Pullup Resistor (D)
36.5 k
W
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 100 V
Moisture Sensitivity (Note 1)
FCBGA-16
QFN-16
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
(Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
V
CC
Positive Power Supply
V
EE
= 0 V
3.6
V
V
EE
Negative Power Supply
V
CC
= 0 V
-3.6
V
V
I
Positive Input
Negative Input
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
3.6
-3.6
V
V
V
INPP
Differential Input Voltage
|D - D|
V
CC
- V
EE
w
2.8 V
V
CC
- V
EE
<
2.8 V
2.8
|V
CC
- V
EE
|
V
V
I
out
Output Current
Continuous
Surge
25
50
mA
mA
I
BB
V
BB
Sink/Source
1
mA
I
MM
V
MM
Sink/Source
1
mA
T
A
Operating Temperature Range
-40 to +85
°
C
T
stg
Storage Temperature Range
-65 to +150
°
C
q
JA
Thermal Resistance (Junction-to-Ambient)
(Note 3)
0 LFPM
500 LFPM
0 LFPM
500 LFPM
16 FCBGA
16 FCBGA
16 QFN
16 QFN
108
86
41.6
35.2
°
C/W
°
C/W
°
C/W
°
C/W
q
JC
Thermal Resistance (Junction-to-Case)
1S2P (Note 3)
2S2P (Note 4)
16 FCBGA
16 QFN
5
4.0
°
C/W
°
C/W
T
sol
Wave Solder
< 15 sec.
225
°
C
2. Maximum Ratings are those values beyond which device damage may occur.
3. JEDEC standard multilayer board - 1S2P (1 signal, 2 power)
4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NBSG16
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5
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT
V
CC
= 2.5 V; V
EE
= 0 V (Note 5)
-40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
17
23
29
17
23
29
17
23
29
mA
V
OH
Output HIGH Voltage (Note 6)
1450
1530
1575
1525
1565
1600
1550
1590
1625
mV
V
OUTPP
Output Voltage Amplitude
350
410
525
350
410
525
350
410
525
mV
V
IH
Input HIGH Voltage
(Single-Ended) (Note 7)
V
THR
+
75 mV
V
CC
-
1.0*
V
CC
V
THR
+
75 mV
V
CC
-
1.0*
V
CC
V
THR
+
75 mV
V
CC
-
1.0*
V
CC
V
V
IL
Input LOW Voltage
(Single-Ended) (Note 7)
V
EE
V
CC
-
1.4*
V
THR
-
75 mV
V
EE
V
CC
-
1.4*
V
THR
-
75 mV
V
EE
V
CC
-
1.4*
V
THR
-
75 mV
V
V
BB
PECL Output Voltage Reference
1080
1140
1200
1080
1140
1200
1080
1140
1200
mV
V
IHCMR
Input HIGH Voltage Common
Mode Range (Note 8)
(Differential Configuration)
1.2
2.5
1.2
2.5
1.2
2.5
V
V
MM
CMOS Output Voltage Reference
V
CC
/2
1100
1250
1400
1100
1250
1400
1100
1250
1400
mV
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@ V
IH
)
30
100
30
100
30
100
m
A
I
IL
Input LOW Current (@ V
IL
)
25
50
25
50
25
50
m
A
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to -0.965 V.
6. All loading with 50
W
to V
CC
-2.0 volts.
7. V
THR
is the voltage applied to the complementary input, typically V
BB
or V
MM
.
8. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
*Typicals used for testing purposes.
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT
V
CC
= 3.3 V; V
EE
= 0 V (Note 9)
-40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
17
23
29
17
23
29
17
23
29
mA
V
OH
Output HIGH Voltage (Note 10)
2250
2330
2375
2325
2365
2400
2350
2390
2425
mV
V
OUTPP
Output Voltage Amplitude
350
410
525
350
410
525
350
410
525
mV
V
IH
Input HIGH Voltage
(Single-Ended) (Note 11)
V
THR
+
75 mV
V
CC
-
1.0*
V
CC
V
THR
+
75 mV
V
CC
-
1.0*
V
CC
V
THR
+
75 mV
V
CC
-
1.0*
V
CC
V
V
IL
Input LOW Voltage
(Single-Ended) (Note 11)
V
EE
V
CC
-
1.4*
V
THR
-
75 mV
V
EE
V
CC
-
1.4*
V
THR
-
75 mV
V
EE
V
CC
-
1.4*
V
THR
-
75 mV
V
V
BB
PECL Output Voltage Reference
1880
1940
2000
1880
1940
2000
1880
1940
2000
mV
V
IHCMR
Input HIGH Voltage Common
Mode Range (Note 12)
(Differential Configuration)
1.2
3.3
1.2
3.3
1.2
3.3
V
V
MM
CMOS Output Voltage Reference
V
CC
/2
1500
1650
1800
1500
1650
1800
1500
1650
1800
mV
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@ V
IH
)
30
100
30
100
30
100
m
A
I
IL
Input LOW Current (@ V
IL
)
25
50
25
50
25
50
m
A
NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925 V to -0.165 V.
10. All loading with 50
W
to V
CC
- 2.0 V.
11. V
THR
is the voltage applied to the complementary input, typically V
BB
or V
MM
.
12. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
*Typicals used for testing purposes.
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6
Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V (Note 13)
-40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
17
23
29
17
23
29
17
23
29
mA
VOH
Output HIGH Voltage (Note 14)
-1050
-970
-925
-975
-935
-900
-950
-910
-875
mV
V
OUTPP
Output Voltage Amplitude
350
410
525
350
410
525
350
410
525
mV
V
IH
Input HIGH Voltage
(Single-Ended) (Note 15)
V
THR
+
75 mV
V
CC
-
1.0*
V
CC
V
THR
+
75 mV
V
CC
-
1.0*
V
CC
V
THR
+
75 mV
V
CC
-
1.0*
V
CC
V
V
IL
Input LOW Voltage
(Single-Ended) (Note 15)
V
EE
V
CC
-
1.4*
V
THR
-
75 mV
V
EE
V
CC
-
1.4*
V
THR
-
75 mV
V
EE
V
CC
-
1.4*
V
THR
-
75 mV
V
V
BB
NECL Output Voltage Reference
-1420
-1360
-1300
-1420
-1360
-1300
-1420
-1360
-1300
mV
V
IHCMR
Input HIGH Voltage Common
Mode Range (Note 16)
(Differential Configuration)
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V
V
MM
CMOS Output Voltage Reference
(Note 17)
V
MMT
-150
V
MMT
V
MMT
+ 150
V
MMT
-150
V
MMT
V
MMT
+ 150
V
MMT
-150
V
MMT
V
MMT
+ 150
mV
R
TIN
Internal Input Termination Resis-
tor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@ V
IH
)
30
100
30
100
30
100
m
A
I
IL
Input LOW Current (@ V
IL
)
25
50
25
50
25
50
m
A
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13. Input and output parameters vary 1:1 with V
CC
.
14. All loading with 50
W
to V
CC
-2.0 volts.
15. V
THR
is the voltage applied to the complementary input, typically V
BB
or V
MM
.
16. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
17. V
MM
typical = |V
CC
- V
EE
|/2 + V
EE
= V
MMT
*Typicals used for testing purposes.
Table 8. AC CHARACTERISTICS for FCBGA-16
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
-40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figure 4. F
max
/JITTER) (Note 18)
10.7
12
10.7
12
10.7
12
GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
90
110
130
100
120
140
105
125
145
ps
t
SKEW
Duty Cycle Skew (Note 19)
3
15
3
15
3
15
ps
t
JITTER
RMS Random Clock Jitter
f
in
< 10 GHz
Peak-to-Peak Data Dependent Jitter
f
in
< 10 Gb/s
0.2
TBD
1
0.2
TBD
1
0.2
TBD
1
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 20)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% - 80%)
30
45
75
20
40
65
20
40
65
ps
18. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50
W
to V
CC
- 2.0 V. Input edge rates 40 ps (20% - 80%).
19. See Figure 6. t
skew
= |t
PLH
- t
PHL
| for a nominal 50% differential clock input waveform.
20. V
INPP(max)
cannot exceed V
CC
- V
EE
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7
Table 9. AC CHARACTERISTICS for QFN-16
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
-40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figure 4. F
max
/JITTER) (Note 21)
10.7
12
10.7
12
10.7
12
GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
90
110
130
100
120
140
95
125
145
ps
t
SKEW
Duty Cycle Skew (Note 22)
3
15
3
15
3
15
ps
t
JITTER
RMS Random Clock Jitter
f
in
< 10 GHz
Peak-to-Peak Data Dependent Jitter
f
in
< 10 Gb/s
0.2
TBD
2
0.2
TBD
2
0.2
TBD
2
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 23)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% - 80%)
20
30
50
20
30
50
20
30
50
ps
21. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50
W
to V
CC
- 2.0 V. Input edge rates 40 ps (20% - 80%).
22. See Figure 6. t
skew
= |t
PLH
- t
PHL
| for a nominal 50% differential clock input waveform.
23. V
INPP(max)
cannot exceed V
CC
- V
EE
OUTPUT AMP
RMS JITTER
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) at Ambient Temperature (Typical)
OUTPUT VOL
T
AGE AMPLITUDE
(mV)
JITTER
OUT
ps (RMS)
700
600
500
400
300
200
100
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
9.5
8.5
7.5
6.5
3.5
2.5
5.5
4.5
0.5
-0.5
1.5
Q
Q
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8
Figure 5. 10.709 Gb/s Diagram (3.0 V, 25
5
C)
X = 17ps/Div Y = 70 mV/Div
Figure 6. AC Reference Measurement
D
D
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(D) - V
IL
(D)
V
OUTPP
= V
OH
(Q) - V
OL
(Q)
Driver
Device
Receiver
Device
Q
D
Figure 7. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices)
Q
D
V
TT
V
TT
= V
CC
- 2.0 V
50
W
50
W
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PACKAGE DIMENSIONS
FCBGA-16
BA SUFFIX
PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE
CASE 489-01
ISSUE O
0.20
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
D
E
M
A1
A2
A
0.10 Z
0.15 Z
ROTATED 90 CLOCKWISE
DETAIL K
_
5
VIEW M-M
e
3 X
S
M
X
0.15
Y
Z
0.08
Z
3
b
16 X
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
4
3
2
1
A
B
C
D
4
16 X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
DIM
MIN
MAX
MILLIMETERS
A
1.40 MAX
A1
0.25
0.35
A2
1.20 REF
b
0.30
0.50
D
4.00 BSC
E
4.00 BSC
e
1.00 BSC
S
0.50 BSC
K
-X-
-Y-
M
M
-Z-
NBSG16
http://onsemi.com
10
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE O
X
M
0.10 (0.004)
T
-T-
-X-
NOTE 3
SEATING
PLANE
L
A
M
-Y-
B
N
0.25 (0.010) T
0.25 (0.010) T
J
C
K
R
0.08 (0.003) T
G
E
H
F
P
D
Y
1
4
5
8
12
9
16
13
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
3.00 BSC
0.118 BSC
B
3.00 BSC
0.118 BSC
C
0.80
1.00
0.031
0.039
D
0.23
0.28
0.009
0.011
G
0.50 BSC
0.020 BSC
H
0.875
0.925
0.034
0.036
J
0.20 REF
0.008 REF
K
0.00
0.05
0.000
0.002
L
0.35
0.45
0.014
0.018
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
E
1.75
1.85
0.069
0.073
F
1.75
1.85
0.069
0.073
M
1.50 BSC
0.059 BSC
N
1.50 BSC
0.059 BSC
P
0.875
0.925
0.034
0.036
R
0.60
0.80
0.024
0.031
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