MSC5301B-02
¡ Semiconductor
1/15
GENERAL DESCRIPTION
The MSC5301B-02 is an LCD driver LSI with a built-in RAM. The device's bit mapping method
offers greater flexibility in which each bit of the display RAM controls each section on the LCD
panel. It can form a graphic display system of 64 x 8 dots in one chip. In addition, the display can
be expanded by using the additional LSIs.
FEATURES
· LCD driving voltage range
: 6 to 16V
· Operating power supply voltage range
: 5V
±
10%
· Display duty
: 1/8 (1/4 bias)
· Common output
: 8 outputs
· Segment output
: 64 outputs
· RAM capacity
: 8 x 64 = 512 bits
· Serial transfer clock frequency (f
SCK
)
: 500 kHz Max.
· Multichip configuration available
· Blanking available
· Built-in RC oscillation circuit
· Package:
100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name: MSC5310B-02GS-BK)
¡ Semiconductor
MSC5301B-02
LCD COMMON/SEGMENT DRIVER WITH RAM
E2B0018-27-Y2
This version: Nov. 1997
Previous version: Mar. 1996
MSC5301B-02
¡ Semiconductor
2/15
8-DOT COM DRV
(4-LEVEL DRV)
64-DOT SEG DRV
(4-LEVEL DRV)
3-8 DECODER
64-BIT LATCH
3-BIT LATCH
READ (3-BIT)
ADDRESS COUNTER
TIMING
GENERATOR
64-BIT SHIFT REGISTER
64-BIT LATCH
CHIP CTL
6-BIT LATCH
8-BIT SHIFT REGISTER
FRAM
IN/OUT
BLK
CTL
POR
CTL
OSC
INPUT
CTL
V
4
V
1
C0
C7
V
DSP
S63
S0
V
2
V
3
V
DSP
GND
V
CC
GND
OS1
OS2 f
BLK
POR
FRAM
V
CC
GND
RAM
RA
2
RA
1
RA
0
WA
2
WA
1
WA
0
WE
f
64 x 8 = 512 bits
LATCH
A / D
SI
SCK
CS0
CS1
BLOCK DIAGRAM
MSC5301B-02
¡ Semiconductor
3/15
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
NC
C0
NC
C1
NC
C2
NC
C3
NC
C4
NC
C5
NC
C6
NC
C7
V
4
V
1
CS0
CS1
LATCH
A/
D
SI
SCK
POR
BLK
FRM
OS1
OS2
f
V
CC
GND
V
DSP
V
2
V
3
S0
S1
S2
S3
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S52
S51
S50
S49
S48
S47
S46
S45
NC
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
NC: No connection
100-Pin Plastic QFP
MSC5301B-02
¡ Semiconductor
4/15
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
*1
V
DSP
>V
1
>V
2
V
3
>V
4
>GND
Parameter
Condition
Power Supply Voltage
*1
Symbol
Rating
Unit
Ta = 25°C
V
CC
0.3 to +6.5
V
Power Supply Voltage
Ta = 25°C
V
DSP
0.3 to +18.0
V
Input Voltage
Ta = 25°C
V
IN
0.3V £ V
IN
£ V
CC
+0.3
V
Input Voltage
Ta = 25°C
V
INDP
0.3 £ V
INDP
£ V
DSP
+0.3
V
Power Dissipation
Ta = 85°C
P
D
275
mW
Storage Temperature
--
T
STG
55 to +125
°C
Parameter
Condition
Power Supply Voltage
*1
Symbol
Range
Unit
GND = 0V
V
CC
4.5 to 5.5
V
Power Supply Voltage
GND = 0V
V
DSP
6.0 to 16.0
V
Operating Temperature
--
T
op
40 to +85
°C
Shift Frequency
--
f
SCK
25 to 500
kHz
Oscillation Frequency
--
f
f
1.92 to 8.0
kHz
Frame Frequency
--
f
FR
60 to 250
Hz
*1
V
DSP
>V
1
>V
2
V
3
>V
4
>GND
MSC5301B-02
¡ Semiconductor
5/15
ELECTRICAL CHARACTERISTICS
DC Characteristics
*1
Applicable to all input pins
*2
Applicable to LATCH, A/D, SI, SCK, BLK and POR pins
*3
Applicable to CS0, CS1, OS1 and FRAM pins
*4
Applicable to FRAM and
pins
*5
Applicable to C0 - C7 pins
*6
Applicable to S0 - S63 pins
*7
ff
= 3.2 kHz, f
SCK
= 200 kHz, no load, display pattern = checkers
V
DSP
= 16V, Current flows into V
CC
pin.
*8
ff = 3.2 kHz, f
SCK
= 200 kHz, no load, display pattern = checkers
V
DSP
= 16V, Current flows into V
DSP
pin.
*9
Applicable to OS1 pin
(V
CC
= 5V, Ta = 40 to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
V
IH
3.5
--
V
CC
V
"H" Input Voltage
*1
V
IL
0
--
1.5
V
"L" Input Voltage
*1
V
HS1
0.3
0.8
1.4
V
Hysteresis Voltage 1
*2
V
HS2
0.2
0.4
0.8
V
Hysteresis Voltage 2
*9
R
PU
10
35
60
kW
Pull-up Resistance
*2
V
PH
4.9
--
--
V
Pull-up Voltage
*2
I
IH
--
--
±10
mA
"H" Input Current
*3
I
IL
--
--
±10
mA
"L" Input Current
*3
V
OH
4.6
--
--
V
"H" Output Voltage
*4
V
OL
--
--
0.4
V
"L" Output Voltage
*4
V
DP
V
DSP
0.4
--
--
V
Common Driver
Output Voltage
V
1
V
1
0.4
--
V
1
+0.4
V
V
4
V
4
0.4
--
V
4
+0.4
V
V
SS
--
--
0.4
V
V
DP
V
DSP
0.4
--
--
V
Segment Driver
Output Voltage
V
2
V
2
0.4
--
V
2
+0.4
V
V
3
V
3
0.4
--
V
3
+0.4
V
V
SS
--
--
0.4
V
I
CC
--
--
6.0
mA
Supply Current 1
I
DSP
--
--
0.5
mA
Supply Current 2
*7
*8
V
I
= 0V
I
IN
< 1mA
V
CC
= 5.5V, V
IH
= 5.5V
V
CC
= 5.5V, V
IL
= 0V
I
O
= 0.4mA
I
O
= 1.6mA
V
DSP
= 10V
*5
V
DSP
= 10V
*6
V
CC
= 5.0V
V
CC
= 5.0V
I = 10mA
I = 10mA
I = ±10mA
I = ±10mA
I = ±10mA
I = ±10mA
I = +10mA
I = +10mA
MSC5301B-02
¡ Semiconductor
6/15
SCK
SI
LATCH
t
2
t
4
t
1
t
5
t
7
t
8
t
6
A/D
t
3
AC Characteristics
(V
CC
= 5V, Ta = 40 to +85°C)
Parameter
Condition
SCK Clock Period
Symbol
Min.
--
t
1
2
SI Data Setup Time
t
2
SI Data Hold Time
t
3
SCK-LATCH Time
t
4
LATCH Pulse Width
t
5
A/D Setup Time
t
6
Typ.
--
Max.
--
Unit
ms
--
1
--
--
ms
--
1
--
--
ms
--
1
--
--
ms
--
15
--
--
ms
--
1
--
--
ms
A/D Hold Time
t
7
--
1
--
--
ms
A/D-SCK Time
t
8
--
1
--
--
ms
POR, BLK Fall Time
t
9
--
--
--
20
ms
f, FRAM Rise Time
t
10
C
L
= 50 pF
--
--
0.3
ms
f, FRAM Fall Time
t
11
C
L
= 50 pF
--
--
0.3
ms
Frame Frequency
f
FR
*1
85
100
115
Hz
*1
The dispersion for external resistors and capacitors is not included.
R
S
= 1kW, R
T
= 15kW, C
T
= 0.01mF, V
CC
= 4.5V to 5.5V
MSC5301B-02
¡ Semiconductor
7/15
V
CC
POR, BLK
90%
10%
GND
V
DSP
f, FRAM
90%
10%
t
9
t
11
t
10
GND
V
1
V
4
GND
Frame A
Frame B
1/f
FR
C0
V
CC
1/f
FR
MSC5301B-02
¡ Semiconductor
8/15
FUNCTIONAL DESCRIPTION
Pin Functional Description
· OS1 (Pin 39), OS2 (Pin 40),
f (Pin 41)
These are pins for the RC oscillation circuit. Connect external resistors and a capacitor as shown
below. When inputting the external clock pulse, input it to OS1 pin. OS2 and f pins should be
left open.
CS0
L
H
L
H
CS1
L
L
H
H
Operation mode
Master mode
Slave mode
Slave mode
Slave mode
H : V
CC
level
L : GND level
The relation of frame frequency f
FR
and internal clock frequency ff is shown by the following
equation.
(RC oscillation frequency = internal clock frequency)
ff = 4 x 8 x f
FR
In addition, the relation of frame frequency f
FR
and frame synchronizing signal frequency
f
FRAM
is shown by the following equation.
f
FRAM
= f
FR
/2
· CS0 (Pin 30), CS1 (Pin 31)
Chip select input pins. Master and slave modes are determined by CS0 and CS1 as shown in
the table below. A maximum of 4 devices can be connected in this manner. Use the master mode
when using a single chip.
OS
1
OS
2
f
C
T
R
S
R
T
MSC5301B-02
¡ Semiconductor
9/15
· FRAM (Pin 38)
This is an input and output pin for the frame synchronizing signal to be used for master/slave
configuration. It becomes an output pin in master mode and an input pin in slave mode.
· SI (Pin 34)
This is a serial data input pin of address data (8 bits) and segment data (64 bits). A pull-up
resistor (10 kW - 60 kW) and the Schmitt circuit are contained. The serial data is shifted at the
rising edge of SCK.
· SCK (Pin 35)
This is a shift clock input pin of address data (8 bits) and segment data (64 bits). The serial data
is shifted at the rising edge of SCK pulse. A pull-up resistor (10 kW - 60 kW) and the Schmitt
circuit are contained.
· LATCH (Pin 32)
This is a latch pulse input pin of address data (8 bits) and segment data (64 bits). The latch data
comes through at "H" level of LATCH and the data just before "H" level is latched at "L" level.
A pull-up resistor (10 kW - 60 kW) and the Schmitt circuit are contained.
· A/D (Pin 33)
This is a data select signal input pin of address data (8 bits) and segment data (64 bits). "H" level
is set in the case of address 8-bit input and "L" level is set in the case of segment data 64-bit input.
A pull-up resistor (10 kW - 60 kW) and the Schmitt circuit are contained.
· V
DSP
(Pin 44), V
1
(Pin 29), V
2
(Pin 45), V
3
(Pin 46), V
4
(Pin 28), V
CC
(Pin 42), GND (Pin 43)
These are power supply pins for this LSI and bias power supply pins for LCD driving.
V
CC
, which is a power supply pin, is from 4.5V to 5.5V; GND, which is a ground pin, is 0V; V
DSP
,
which is an LCD driving power supply pin, is usually used in the range between 6V and 16V.
V
1
, V
2
, V
3
and V
4
are bias power supply pins for LCD driving and are usually used by
supplying bias voltage from an external source.
MSC5301B-02
¡ Semiconductor
10/15
· BLK (Pin 37)
This is an input pin to control the LCD panel display.
When a "H" level is input (or when this pin is open), the segment output pins S0 - S63 come to
the levels V
2
- V
3
and the LCD panel is turned off. In addition, during this period, the data read
from a display RAM is stopped but writing into the display RAM of address and segment data
inputted from the SI pin is available.
When this pin is changed from "H" level to "L", the frame synchronizing signal FRAM is output
within the 2 cycles of an internal clock ff, and it is synchronized at multi-chip. Then, the display
RAM address is set to "000". After 1/8 frame cycle from FRAM signal generation, the output
is applied from the "001" data of the display RAM address to the segment driver. Because the
display RAM contents are undefined at the time the power is turned on, keep this pin to "H"
level (or leave open) until writing data to the RAM is completed. A pull-up resistor (10kW -
60kW) and the Schmitt circuit are contained.
· POR (Pin 36)
This is a power-on-reset input pin. When a "H" level is input (or when this pin is open), the
common and segment outputs come to the static light-out state in no relation to the BLK pin
and the segment output pins S0 - S63 become V
3
level and the common output pins C0 - C8
become V
4
level.
When this pin is changed from "H" level to "L", the frame synchronizing signal FRAM is output
within the 2 cycles of an interval clock ff, and it is synchronized when multiple devices are
connected and is moreover dynamic-operated from the frame B . Then, the display RAM
address is set to "000". After 1/8 frame cycle from FRAM signal generation, the "001" data of
the display RAM address is output to the segment driver. However, because the BLK pin is
usually at "H" level when the power-on-reset is released, reading data from the display RAM
is stopped and light-out segment data is forcibly transferred to the segment output. A pull-up
resistor (10kW - 60kW) and the Schmitt circuit are contained.
· C0 (Pin 13) - C7 (Pin 27)
These are 8-output pins of the common driver which are used for LCD panel driving. The
outputs of 4 levels are obtained (V
DSP
and GND are select levels, and V
1
and V
4
are nonselect
levels).
· S0 (Pin 47) - S63 (Pin 11)
These are 64-output pins of segment driver which are used for LCD panel driving. The outputs
of 4 levels are obtained (V
DSP
and GND are select levels, which correspond to "1" of the display
RAM data, and V
2
and V
3
are nonselect levels, which correspond to "0" of the display RAM
data).
NOTES ON USE
Note the following when turning power on and off:
The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to
the LCD drivers with the logic power supply floating, excess current flows. This may damage
the IC. Be sure to carry out the following power-on and power-off sequences:
When turning power on:
First V
CC
ON, next V
DSP
, V
4
, V
3
, V
2
, V
1
ON. Or both ON at the same time.
When turning power off:
First V
DSP
, V
4
, V
3
, V
2
, V
1
OFF, next V
CC
OFF. Or both OFF at the same time.
MSC5301B-02
¡ Semiconductor
11/15
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
S63
S0
C0
C1
C2
C3
C4
C5
C6
C7
1/8 duty
Address
Data
Number of dots in X direction (64)
Relation Between LCD Screen Size and Display RAM
This LCD driver has a built-in RAM for the display of 8 ¥ 64 = 512 bits and the address
corresponds to the duty of the LCD.
The data corresponds to the number of dots in the X direction. The relation between the LCD
screen size and the display RAM is shown below.
Relation Between Frame Cycle and Display RAM Data
The output of the display RAM data corresponds to the segment output. The relation between
the frame cycle and the display RAM data is as follows:
Segment output
(Contents of RAM)
1 frame cycle
000
001
010
011
110
111
000
001
First line address
MSC5301B-02
¡ Semiconductor
12/15
Multiple Configuration
This LCD driver can form multiple configuration.
It is possible to form a maximum of 4 devices (a panel of up to 256 ¥ 8 dots in size can be formed)
by using chip select signals CS0 and CS1. The devices in multiple configuration must be
synchronized with one another. In this configuration, one device in the master mode, where the
original oscillation signal f and the synchronous signal FRAM are output, and the other devices
in the slave mode, where the original oscillation signal f and the synchronous signal FRAM are
input, are used in combination.
Refer to items CS0 and CS1 of the pin description on the mode setting method.
The original oscillation signal output pin f of the master mode devices is connected to the OS1
pin of the slave mode device and the synchronizing signal pin FRAM is also connected to the
FRAM pin of the slave mode device.
Connect SI, SCK, LATCH, A/D, POR and BLK of the master mode devices to SI, SCK, LATCH,
A/D, POR and BLK of each of the slave mode devices and connect them to CPU for control.
In addition, connect the devices so that V
DSP
, V
1
, V
2
, V
3
, V
4
and GND are shared between the
devices, and connect them to each voltage level divided by resistors.
Address Data Configuration
The lower address, which is the address of the display RAM, corresponds to the common sides
C0 - C7 of LCD panel. Dummy data 1 must be always set to "H".
The upper address corresponds to the logical state of chip select pins CS0 and CS1 and lower
address is set to the chip only with which corresponded.
For the chip to output the common signal (f, FRAM), set both of the upper address 2 bits to "L".
The 2 bits of dummy data can be set to either "L" or "H".
7
6
5
4
3
2
1
0
Dummy data 2
Upper address
Lower address
2 bits
2 bits
(MSB)
(LSB)
3 bits
1 bit
Dummy data 1
DM2
DM1
CS1
CS0
A2
A1
A0
DM0
MSC5301B-02
¡ Semiconductor
13/15
Serial Signal to be Input From CPU
The following signals are input from an external CPU to this LCD driver:
- Serial transfer clock
Æ
SCK
- Serial transfer data
Æ
SI
- Serial transfer latch
Æ
LATCH
- Serial data select
Æ
A/D
The operations are shown in the following table.
Timing for Serial Signal Transferred From CPU
Notes:
1. Be sure to set the address before writing the segment data to RAM. Then, write the segment
data to RAM.
2. While the POR pin is "H" (upon power-on reset), neither address data nor segment data can
be entered.
1
2
3
4
5
6
7
8
1
2
3
63 64
A/D
"H" at address data setting
"L" at segment data setting
SCK
SI
LATCH
A0 A1 A2 CS0 CS1 Dummy Dummy
S
63
S
62
S
61
S
1
S
0
Address data (8 bits)
Segment data (64 bits)
MSB
LSB
Address latch
signal
RAM write
signal
Dummy
(Always "H")
Mode
LATCH
SI
Address data
input mode
H
L
Segment data
input mode
Shifts at the
rising edge
Shifts at the
rising edge
8-bit address data is latched
at falling edge (level type)
64-bit segment data is latched
at falling edge (level type)
8-bit address data
Serial input from LSB side
64-bit segment data
The first segment data shifted into the shift
register corresponds to S63.
"1" : Light-on data, "0" : Light-out data
SCK
A/D
MSC5301B-02
¡ Semiconductor
14/15
Dynamic operation (normal operation)
Dynamic light-out state
Frame B
Frame B
Frame A
Frame A
Frame B
Frame B
Frame A
RAM address
0 - 7
Frame A
0 - 7
0
- 0
1
- 7
0
- 7
0
- 7
0
- 7
Segment signal
output
Common signal output
FRAM
f
(External R
and C)
BLK
POR
V
CC
Operation upon Power ON (When Single Device Used)
MSC5301B-02
¡ Semiconductor
15/15
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
QFP100-P-1420-0.65-BK
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.29 TYP.
Mirror finish
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