DS90LV110AT
1 to 10 LVDS Data/Clock Distributor with Failsafe
General Description
DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS
(Low Voltage Differential Signaling) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. The design allows connection of 1 input to
all 10 outputs. LVDS I/O enable high speed data transmis-
sion for point-to-point interconnects. This device can be used
as a high speed differential 1 to 10 signal distribution / fanout
replacing multi-drop bus applications for higher speed links
with improved signal quality. It can also be used for clock
distribution up to 200MHz.
The DS90LV110A accepts LVDS signal levels, LVPECL lev-
els directly or PECL with attenuation networks.
The LVDS outputs can be put into TRI-STATE by use of the
enable pin.
For more details, please refer to the Application Information
section of this datasheet.
Features
n
Low jitter 400 Mbps fully differential data path
n
145 ps (typ) of pk-pk jitter with PRBS = 2
23
-1 data
pattern at 400 Mbps
n
Single +3.3 V Supply
n
Balanced output impedance
n
Output channel-to-channel skew is 35ps (typ)
n
Differential output voltage (V
OD
) is 320mV (typ) with
100
termination load.
n
LVDS receiver inputs accept LVPECL signals
n
LVDS input failsafe
n
Fast propagation delay of 2.8 ns (typ)
n
Receiver open, shorted, and terminated input failsafe
n
28 lead TSSOP package
n
Conforms to ANSI/TIA/EIA-644 LVDS standard
Connection Diagram
20098205
Order Number DS90LV110ATMT
See NS Package Number MTC28
Block Diagram
20098201
October 2004
DS90L
V1
10A
T
1
t
o
1
0
L
VDS
Data/Clock
Distributor
with
Failsafe
© 2004 National Semiconductor Corporation
DS200982
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
-V
SS
)
-0.3V to +4V
LVCMOS/LVTTL Input Voltage
(EN)
-0.3V to (V
CC
+ 0.3V)
LVDS Receiver Input Voltage
(IN+, IN-)
-0.3V to +4V
LVDS Driver Output Voltage
(OUT+, OUT-)
-0.3V to +4V
Junction Temperature
+150°C
Storage Temperature Range
-65°C to +150°C
Lead Temperature
(Soldering, 4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
28L TSSOP
1.209 W
Package Derating
28L TSSOP
9.67 mW/°C above +25°C
JA
28L TSSOP
103.4 °C/Watt
ESD Rating:
(HBM, 1.5k
, 100pF)
>
4 kV
(EIAJ, 0
, 200pF)
>
250 V
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (V
DD
- V
SS
)
3.0
3.3
3.6
V
Receiver Input Voltage
0
V
DD
V
Operating Free Air Temperature
-40
+25 +85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS/LVTTL DC SPECIFICATIONS (EN)
V
IH
High Level Input Voltage
2.0
V
DD
V
V
IL
Low Level Input Voltage
V
SS
0.8
V
I
IH
High Level Input Current
V
IN
= 3.6V or 2.0V; V
DD
= 3.6V
±
7
±
20
µA
I
IL
Low Level Input Current
V
IN
= 0V or 0.8V; V
DD
= 3.6V
±
7
±
20
µA
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-0.8
-1.5
V
LVDS OUTPUT DC SPECIFICATIONS (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10)
V
OD
Differential Output Voltage
R
L
= 100
250
320
450
mV
R
L
= 100
, V
DD
= 3.3V, T
A
= 25°C
260
320
425
mV
V
OD
Change in V
OD
between Complimentary Output States
35
|mV|
V
OS
Offset Voltage (Note 3)
1.125
1.25
1.375
V
V
OS
Change in V
OS
between Complimentary Output States
35
|mV|
I
OZ
Output TRI-STATE Current
EN = 0V,
±
1
±
10
µA
V
OUT
= V
DD
or GND
I
OFF
Power-Off Leakage Current
V
DD
= 0V; V
OUT
= 3.6V or GND
±
1
±
10
µA
I
SA
,I
SB
Output Short Circuit Current
V
OUT+
OR V
OUT-
= 0V or V
DD
12
24
|mA|
I
SAB
Both Outputs Shorted (Note 4)
V
OUT+
= V
OUT-
6
12
|mA|
LVDS RECEIVER DC SPECIFICATIONS (IN)
V
TH
Differential Input High Threshold
V
CM
= +0.05V or +1.2V or +3.25V,
0
+100
mV
V
TL
Differential Input Low Threshold
V
DD
= 3.3V
-100
0
mV
V
CMR
Common Mode Voltage Range
V
ID
= 100mV, V
DD
= 3.3V
0.05
3.25
V
I
IN
Input Current
V
IN
= +3.0V, V
DD
= 3.6V or 0V
±
1
±
10
µA
V
IN
= 0V, V
DD
= 3.6V or 0V
±
1
±
10
µA
DS90L
V1
10A
T
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2
Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENT
I
CCD
Total Supply Current
R
L
= 100
, C
L
= 5 pF, 200 MHz,
125
160
mA
EN = High
No Load, 200 MHz, EN = High
80
125
mA
I
CCZ
TRI-STATE Supply Current
EN = Low
15
29
mA
Note 1: "Absolute Maximum Ratings" are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: All typical are given for V
CC
= +3.3V and T
A
= +25°C, unless otherwise stated.
Note 3: V
OS
is defined as (V
OH
+ V
OL
) / 2.
Note 4: Only one output can be shorted at a time. Don't exceed the package absolute maximum rating.
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T
LHT
Output Low-to-High Transition Time, 20% to 80%, Figure 4
(Note 5)
390
550
ps
T
HLT
Output High-to-Low Transition Time, 80% to 20%, Figure 4
(Note 5)
390
550
ps
T
DJ
LVDS Data Jitter, Deterministic
(Peak-to-Peak)(Note 6)
V
ID
= 300mV; PRBS=2
23
-1 data;
V
CM
= 1.2V at 400 Mbps (NRZ)
145
ps
T
RJ
LVDS Clock Jitter, Random (Note 6)
V
ID
= 300mV; V
CM
= 1.2V
at 200 MHz clock
2.8
ps
T
PLHD
Propagation Low to High Delay, Figure 5
2.2
2.8
3.6
ns
T
PHLD
Propagation High to Low Delay, Figure 5
2.2
2.8
3.9
ns
T
SKEW
Pulse Skew |T
PLHD
- T
PHLD
| (Note 5)
20
340
ps
T
CCS
Output Channel-to-Channel Skew, Figure 6 (Note 5)
35
91
ps
T
PHZ
Disable Time (Active to TRI-STATE) High to Z, Figure 1
3.0
6.0
ns
T
PLZ
Disable Time (Active to TRI-STATE) Low to Z, Figure 1
1.8
6.0
ns
T
PZH
Enable Time (TRI-STATE to Active) Z to High, Figure 1
10.0
23.0
ns
T
PZL
Enable Time (TRI-STATE to Active) Z to Low, Figure 1
7.0
23.0
ns
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 6: The measurement used the following equipment and test setup: HP8133A pattern/pulse generator), 5 feet of RG-142 cable with DUT test board and
HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with the RG-142 cable exhibit a T
DJ
= 26ps and T
RJ
= 1.3 ps
DS90L
V1
10A
T
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3
AC Timing Diagrams
20098204
FIGURE 1. Output active to TRI-STATE and TRI-STATE to active output time
20098215
FIGURE 2. LVDS Driver TRI-STATE Circuit
20098206
FIGURE 3. LVDS Output Load
20098209
FIGURE 4. LVDS Output Transition Time
DS90L
V1
10A
T
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4
AC Timing Diagrams
(Continued)
20098207
FIGURE 5. Propagation Delay Low-to-High and High-to-Low
20098208
FIGURE 6. Output 1 to 10 Channel-to-Channel Skew
DS90L
V1
10A
T
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5
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