Pin
Function
REF_CLK, REF_CLK
Differential Input Ref. Clock
FILP, FILN
Filter Pins (Positive & Negative)
V
CCA
, V
EEA
Analog V
CC
, V
EE
RST
Master Reset
FSEL2-0
LVPECL Frequency Select Pins
USYNC, USYNC
Diff. HSTL Sync Signal for PA-8000
PCLK1-2, PCLK1-2
Diff. HSTL Processor Clock Signal
RCLK, RCLK
Diff. HSTL Runway Clock Signal
RCLKLV, RCLKLV
Diff. LVPECL Clock Signal
Micrel-Synergy's SY89801A PLL based clock generator
provides, in a single chip, all the necessary clocks for Hewlett-
Packard's PA-8000 Microprocessor.
Utilizing Micrel-Synergy's advanced PLL technology, the
SY89801A accepts a Positive-ECL (PECL) reference clock
input at 100MHz-132MHz, and provides precisely aligned,
ultra-low-jitter ratios of frequencies necessary for the operation
of the processor. In addition, the SY89801A provides the
"USYNC" synchronizing signals as required by the PA-8000.
The frequency ratios are 1:1, 4:3, 3:2, 5:3 and 2:1.
To facilitate direct interfacing to the PA-8000, the SY89801A
operates across +3.3 volt and -1.9 volt supplies. The processor
clock (PCLK), runway clock (RCLK) , and USYNC outputs are
HSTL-compatible. Additionally, there is a PECL-compatible
runway clock output (RCLKLV). The SY89801A requires only
a simple external series-RC loop filter.
Coupling Micrel-Synergy's advanced PLL technology with
our proprietary ASSET bipolar process has produced a
Timing Generator IC which meets the stringent requirements
of the PA-8000
µ
P, while setting a new standard for
performance and flexibility.
FEATURES
s
3.3V, 1.9V power suppies
s
Differential LVPECL clock input
s
Differential HSTL/LVPECL outputs
s
Compatible with HP PA-8000 microprocessors
s
Low-jitter source for all PA-8000 required timing
signals
s
Available in 44-pin MQUAD package
DESCRIPTION
Rev.: E
Amendment: /0
Issue Date:
November 1998
ClockWorksTM
PRELIMINARY
SY89801A
HP PA-8000
CLOCK SOURCE
PIN CONFIGURATION
PIN NAMES
USYNC
VEEA
NC
NC
FILP
FILN
VCCA
NC
NC
NC
NC
NC
39
1
TOP VIEW
MQUAD
M44-1
2
3
4
5
6
44 43 42 41 40
38
37
36
35
34
33
32
31
30
29
23
22
21
20
19
18
24 25 26 27 28
7
8
9
10
11
12
13
14
15
16
17
VEE
NC
NC
REF_CLK
REF_CLK
VCC
RCLK
RCLK
RCLKLV
RCLKLV
VEE
VEE
PCLK1
PCLK1
PCLK2
PCLK2
VCC
USYNC
NC
NC
VCC
VCC
NC
NC
NC
RST
VEE
NC
FSEL0
FSEL1
FSEL2
VCC
1
3
ClockWorksTM
PRELIMINARY
SY89801A
Micrel
PECL DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
V
OH
Output HIGH Voltage
V
CC
1.075
--
V
CC
0.830
V
V
OL
Output LOW Voltage
V
CC
1.860
--
V
CC
1.570
V
V
IH
Input HIGH Voltage
V
CC
1.165
--
V
CC
0.880
V
V
IL
Input LOW Voltage
V
CC
1.810
--
V
CC
1.475
V
V
BB
PECL Threshold
--
V
CC
1.35
--
V
V
CC
= 3.3V
±
10%; V
EE
= 1.9V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
V
CC
Power Supply Voltage
3.0
--
3.6
V
V
EE
= 1.9V
I
CC
Power Supply Current (V
CC
)
--
250
321
mA
3.3V DC ELECTRICAL CHARACTERISTICS
V
CC
= V
CCA
= 3.3V
±
10%; V
EEA
= V
EE =
1.9V
Symbol
Parameter
Min.
Typ. Max. Min.
Typ. Max. Min.
Typ. Max. Unit
Condition
f
VCO
Maximum VCO Frequency
1320
--
--
1320
--
--
1320
--
--
MHz
f
MAX
Maximum PCLK Output Frequency
264
--
--
264
--
--
264
--
--
MHz
Maximum RCLK Output Frequency
132
--
--
132
--
--
132
--
--
MHz
t
skew
(2)
PCLK to PCLK
--
--
±
50
--
--
±
50
--
--
±
50
ps
Measured at
RCLK to RCLKLV
--
--
±
100
--
--
±
100
--
--
±
100
ps
differential
PCLK to RCLK
--
--
±
100
--
--
±
100
--
--
±
100
ps
crossover
PCLK (neg.) to USYNC
--
--
±
500
--
--
±
500
--
--
±
500
ps
tpe
Phase Error
--
--
±
250
--
--
±
250
--
--
±
250
ps
RCLK to REF_CLK
tj
(2)
Output Jitter
50
--
+50
50
--
+50
50
--
+50
ps
Peak to Peak,
Cycle to Cycle
tdc
(2)
Output Duty Cycle
49
--
51
49
--
51
49
--
51
%
tr
Rise/Fall Times
100
--
800
100
--
800
100
--
800
ps
tf
(20% to 80%)
AC ELECTRICAL CHARACTERISTICS
(1)
V
CC
= 3.3V
±
10%; V
EE
= 1.9V
NOTES:
1. All HSTL outputs terminated into 50 ohms in parallel with 3pf to GND.
2. t
skew
, tj, tdc, tr and tf are specified by HP for the PA-8000. This is our best information as of the date of this document.
T
A
= 0
°
C
T
A
= +25
°
C
T
A
= +70
°
C
(2)
HSTL DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
V
OH
Output HIGH Voltage
V
CC
2.3
--
V
CC
2.1
V
V
OL
Output LOW Voltage
V
CC
3.1
--
V
CC
2.9
V
V
CC
= 3.3V
±
10%; V
EE
= 1.9V
4
ClockWorksTM
PRELIMINARY
SY89801A
Micrel
The following table lists the various PCLK and RCLK
ratios supported by the SY89801A and the corresponding
PCLK, RCLK, FB and VCO frequencies. The table is
arranged in order of increasing PCLK:RCLK ratio. The
table was designed to balance several constraints:
VCO
÷
ratios
FSEL <2:0>
PCLK:RCLK
fPCLK (MHz)
fRCLK (MHz)
VCO/P:VCO/R
fVCO (MHz)
000
1:1
100-132
100-132
8:8
800-1056
001
4:3
133.3-176
100-132
6:8
800-1056
010
3:2
150-198
100-132
4:6
600-792
011
5:3
166.7-220
100-132
6:10
1000-1320
100
2:1
200-264
100-132
4:8
800-1056
101
1:1
100-132
100-132
6:6
600-792
110
1:1
100-132
100-132
10:10
1000-1320
111
n/a
n/a
n/a
n/a
n/a
APPLICATIONS INFORMATION
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY89801AMC
M44-1
Commercial
SY89801AMCA
(1)
M44-1
Commercial
LOOP FILTER COMPONENT SELECTION
R
C1
filp
filn
R
= 500
±
10%
C1 = 1000pF
±
10%
NOTES:
1. "A" denotes enhanced 200MHz testing.
s
2.5:1 VCO frequency range
s
Maximum system frequency of 120MHz plus 10%
margin
s
Maximum output frequency of 264MHz
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