DEVICES INCORPORATED

LSH32

32-bit Cascadable Barrel Shifter

Special Arithmetic Functions

08/16/2000LDS.32-Q

configured such that any contiguous
16-bit field (including wraparound of
the 32 inputs) may be presented to the
output pins under control of the shift
code field (wrap mode). Alterna-
tively, the wrap feature may be
disabled, resulting in zero or sign bit
fill, as appropriate (fill mode). The
shift code control assignments and the
resulting input to output mapping for
the wrap mode are shown in Table 1.

Essentially the LSH32 is configured as
a left shift device. That is, a shift code
of 00000

results in no shift of the

input field. A code of 00001

provides

an effective left shift of 1 position, etc.
When viewed as a right shift, the shift
code corresponds to the two's com-
plement of the shift distance, i.e., a
shift code of 11111

) results in a

right shift of one position, etc.

When not in the wrap mode, the
LSH32 fills bit positions for which
there is no corresponding input bit.
The fill value and the positions filled
depend on the RIGHT/LEFT (R/L)
direction pin. This pin is a don't care
input when in wrap mode. For left
shifts in fill mode, lower bits are filled
with zero as shown in Table 2. For
right shifts, however, the SIGN input
is used as the fill value. Table 3
depicts the bits to be filled as a
function of shift code for the right shift
case. Note that the R/L input changes
only the fill convention, and does not
affect the definition of the shift code.

In fill mode, as in wrap mode, the shift
code input represents the number of
shift positions directly for left shifts,
but the two's complement of the shift
code results in the equivalent right
shift. However, for fill mode the R/L
input can be viewed as the most

32-bit Input, 32-bit Output Multi-
plexed to 16 Lines

u Full 0-31 Position Barrel Shift

Capability

u Integral Priority Encoder for 32-bit

Floating Point Normalization

u Sign-Magnitude or Two's Comple-

ment Mantissa Representation

u 32-bit Linear Shifts with Sign or

Zero Fill

u Independent Priority Encoder

Outputs for Block Floating Point

u 68-pin PLCC, J-Lead

FEATURES

DESCRIPTION

LSH32

32-bit Cascadable Barrel Shifter

DEVICES INCORPORATED

The LSH32 is a 32-bit high speed
shifter designed for use in floating
point normalization, word pack/
unpack, field extraction, and similar
applications. It has 32 data inputs,
and 16 output lines. Any shift
configuration of the 32 inputs, includ-
ing circular (barrel) shifting, left shifts
with zero fill, and right shift with sign
extend are possible. In addition, a
built-in priority encoder is provided
to aid floating point normalization.

SHIFT ARRAY

The 32 inputs to the LSH32 are
applied to a 32-bit shift array. The 32
outputs of this array are multiplexed
down to 16 lines for presentation at
the device outputs. The array may be

LSH32 B

LOCK

IAGRAM

MS/LS

32-bit

BARREL

SHIFT

ARRAY

2:1

32:5

PRIORITY

ENCODE

SIGN I

-I

NORM

RIGHT/LEFT

FILL/WRAP

2:1

-Y

-SO

-SI

DEVICES INCORPORATED

LSH32

32-bit Cascadable Barrel Shifter

Special Arithmetic Functions

08/16/2000LDS.32-Q

ffs2

significant bit of a 6-bit two's comple-
ment shift code, comprised of R/L
concatenated with the SI

lines.

Thus a positive shift code (R/L = 0)
results in a left shift of 031 positions,
and a negative code (R/L = 1) a right
shift of up to 32 positions. The LSH32
can thus effectively select any contigu-
ous 32-bit field out of a (sign extended
and zero filled) 96-bit "input."

OUTPUT MULTIPLEXER

The shift array outputs are applied to
a 2:1 multiplexer controlled by the
MS/LS select line. This multiplexer
makes available at the output pins
either the most significant or least
significant 16 outputs of the shift
array.

PRIORITY ENCODER

The 32-bit input bus drives a priority
encoder which is used to determine
the first significant position for
purposes of normalization. The
priority encoder produces a five-bit
code representing the location of the
first non-zero bit in the input word.
Code assignment is such that the
priority encoder output represents the
number of shift positions required to
left align the first non-zero bit of the
input word. Prior to the priority
encoder, the input bits are individu-
ally exclusive OR'ed with the SIGN
input. This allows normalization in
floating point systems using two's
complement mantissa representation.
A negative value in two's complement
representation will cause the exclusive
OR gates to invert the input data to
the encoder. As a result the leading
significant digit will always be "1."
This affects only the encoder inputs;
the shift array always operates on the
raw input data. The priority encoder
function table is shown in Table 4.

ABLE

RAP

ODE

HIFT

ODE

EFINITIONS

Shift Code

· · ·

00000

· · ·

00001

· · ·

00010

· · ·

00011

· · ·

01111

· · ·

10000

· · ·

10001

· · ·

10010

· · ·

11100

· · ·

11101

· · ·

11110

· · ·

11111

· · ·

ABLE

ILL

ODE

HIFT

ODE

EFINITIONS

-- L

EFT

HIFT

Shift Code

· · ·

00000

· · ·

00001

· · ·

00010

· · ·

00011

· · ·

01111

· · ·

10000

· · ·

10001

· · ·

10010

· · ·

11100

· · ·

11101

· · ·

11110

· · ·

11111

· · ·

DEVICES INCORPORATED

LSH32

32-bit Cascadable Barrel Shifter

Special Arithmetic Functions

08/16/2000LDS.32-Q

NORMALIZE MULTIPLXER

The NORM input, when asserted
results in the priority encoder output
driving the internal shift code inputs
directly. It is exactly equivalent to
routing the SO

outputs back to

the SI

inputs. The NORM input

provides faster normalization of 32-bit
data by avoiding the delay associated
with routing the shift code off chip.
When using the NORM function, the
LSH32 should be placed in fill mode,
with the R/L input low.

APPLICATIONS EXAMPLES

Normalization of mantissas up to 32
bits can be accomplished directly by a
single LSH32. The NORM input is
asserted, and fill mode and left shift
are selected. The normalized mantissa
is then available at the device output
in two 16-bit segments, under the
control of the output data multiplexer
select, the MS/LS.

If it is desirable to avoid the necessity
of multiplexing output data in 16-bit
segments, two LSH32 devices can be
used in parallel. Both devices receive
the same input word, with the MS/LS
select line of one wired high, and the
other low. Each device will then
independently determine the shift
distance required for normalization,
and the full 32 bits of output data will
be available simultaneously.

ABLE

ILL

ODE

HIFT

ODE

EFINITIONS

-- R

IGHT

HIFT

ABLE

RIORITY

NCODER

UNCTION

ABLE

· · ·

Shift Code

· · ·

00000

· · ·

00001

· · ·

00010

· · ·

01111

· · ·

10000

· · ·

10001

· · ·

11110

· · ·

11111

· · ·

11111

Shift Code

· · ·

00000

· · ·

00001

· · ·

00010

· · ·

00011

· · ·

01111

· · ·

10000

· · ·

10001

· · ·

10010

· · ·

11100

· · ·

11101

· · ·

11110

· · ·

11111

· · ·

DEVICES INCORPORATED

LSH32

32-bit Cascadable Barrel Shifter

Special Arithmetic Functions

08/16/2000LDS.32-Q

ffs4

LONG-WORD NORMALIZATION
(MULTIPLE CYCLES)

Normalization of floating point
mantissas longer than 32 bits can be
accomplished by cascading LSH32
units. When cascading for normaliza-
tion, the device inputs are overlapped
such that each device lower in priority
than the first shares 16 inputs with its
more significant neighbor. Fill mode
and left shift are selected, however,
internal normalization (NORM) is not
used. The most significant result half
of each device is enabled to the
output. The shift out (SO

) lines

of the most significant slice are
connected to the shift in lines of all

clock normalization requiring shifts
longer than 16 bits can be accom-
plished by a bank-select technique
described below.

SINGLE CYCLE LONG-WORD
NORMALIZATION

An extension of the above concept is a
single clock normalization of long
words (potentially requiring shifts of
more than 15 places). The arrange-
ment of LSH32s required is shown in
Figure 1. Cascading of LSH32 units is
accomplished by connecting the SI

input lines of each unit to the SO

outputs of the most significant

device in the row as before. Essen-

slices, including the first. The excep-
tion is that all SI

lines are grounded,

limiting the shift distance to 16
positions. The shift distance required
for normalization is produced by the
priority encoder in the most signifi-
cant slice. The priority encoder will
produce the shift code necessary to
normalize the input word if the
leading non-zero digit is found in the
upper 16 bits. If this is the case, the
number of shift positions necessary to
accomplish normalization is placed on
the SO

outputs for use by all

slices, and the appropriate 015 bit
shift is accomplished. If the upper 16
bits are all zero, then the maximum
shift of 15 places is executed. Single

IGURE

INGLE

YCLE

ONG

-W

ORD

ORMALIZATION

SING

LSH32

LSH32

3-0

4-0

LSH32

-I

-Y

MSBs

PRIORITY

ENCODE

2:4

DECODE

-I

3-0

4-0

3-0

4-0

3-0

4-0

-Y

DEVICES INCORPORATED

LSH32

32-bit Cascadable Barrel Shifter

Special Arithmetic Functions

08/16/2000LDS.32-Q

tially the LSH32s are arranged in
multiple rows or banks such that the
inputs to successive rows are left-
shifted by 16 positions. The outputs
of each row are multiplexed onto a
three-state bus. The normalization
problem then reduces to selecting
from among the several banks that
one which has the first non-zero bit
of the input value among its 16 most
significant positions. If the most
significant one in the input file was
within the upper 16 locations of a
given bank, the SO

output of the

most significant slice in that bank will
be low. Single clock normalization
can thus be accomplished simply by
enabling onto the three-state output
bus the highest priority bank in which
this condition is met. In this way the
input word will be normalized
regardless of the number of shift
positions required to accomplish this.

The number of shift positions can be
determined simply by concatenation
of the SO

outputs of the most

significant slice in the selected row
with the encoded Output Enable-bits
determining the row number. Note
that lower rows need not be fully
populated. This is because they
represent left shifts in multiples of 16
positions, and the lower bits of the
output word will be zero filled. In
order to accomplish this zero fill, the
least significant device in each row is
always enabled, and the row select is
instead connected to the SI

input.

This will force the shift length of the
least significant device to a value
greater than 15 whenever the row
containing that device is not selected.
This results in zero fill being accom-
plished by the equivalently positioned
slice in a higher bank, as shown in the
diagram.

BLOCK FLOATING POINT

With a small amount of external logic,
block floating point operations are
easily accomplished by the LSH32.
Data resulting from a vector operation
are applied to the LSH32 with the
NORM-input deasserted. The SO

outputs fill then represent the

normalization shift distance for each
vector element in turn. By use of an
external latch and comparator, the
maximum shift distance encountered
across all elements in the vector is
saved for use in the next block opera-
tion (or block normalization). During
this subsequent pass through the data,
the shift code saved from the previous
pass is applied uniformly across all
elements of the vector. Since the
LSH32 is not used in the internal
normalize mode, this operation can be
pipelined, thereby obtaining the
desired shift distance for the next pass
while simultaneously applying the
normalization required from the
previous pass.

Part Number LSH32