Key Features
N Auto-selectable LVD or single-ended termination
N 3.0pF maximum disabled output capacitance
N Fast response, no external capacitors required
N Compatible with active negation drivers
N 15µA supply current in disconnect mode
N Logic command disconnects all termination lines
N DIFFSENSE line driver
N Ground driver integrated for single-ended
operation
N Current limit and thermal protection
N Hot-swap compatible (single-ended)
N Compatible with SCSI, SPI-2, SPI-3, SPI-4
ULTRA160 and ULTRA320
N Pin compatible with DS2119
Block Diagram
9-Line UL
9-Line UL
TRA3 L
TRA3 L
VD/SE
VD/SE
SCSI T
SCSI T
er
er
minat
minat
or
or
The IMP2119 is a multimode SCSI terminator that conforms to the SCSI
Parallel Interconnect-2 (SPI-2) specification developed by the T10 stan-
dards committee for low voltage differential (LVD) termination.
Multimode compatibility permits the use of legacy devices on the bus
without hardware alterations. Automatic mode selection is achieved
through voltage detection on the diffsense line.
The IMP2119 delivers the ultimate in SCSI bus performance while saving
component cost and board area. Elimination of the external capacitors
also mitigates the need for a lengthy capacitor selection process. The indi-
vidual high bandwidth drivers also maximize channel separation and
reduce channel to channel noise and cross talk. The high bandwidth
architecture insures ULTRA3 performance.
When the IMP2119 is enabled, the differential sense (DIFFSENSE) pin
supplies a voltage between 1.2V and 1.4V. In application, this pin is tied
to the DIFFSENSE input of the corresponding LVD transceivers. This
action enables the LVD transceiver function. DIFFSENSE is capable of
supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places
the IMP2119 in a high impedance state indicating the presence of an
HVD device. Tying the pin LOW places the part in a single-ended mode
while also signaling the multimode transceiver to operate in a single-
ended mode.
Recognizing the needs of portable and configurable peripherals, the
IMP2119 have a TTL compatible sleep/disable mode. During this
sleep/disable mode, power dissipation is reduced to a meager 15
µA
while also placing all outputs in a high impedance state. Also during
sleep/disable mode, the DIFFSENSE function is disabled
and is placed in a high impedance state.
Another key feature of the IMP2119 is the master/slave
function. Driving this pin HIGH or floating the pin enables
the 1.3V DIFFSENSE reference. Driving the pin LOW dis-
ables the on board DIFFSENSE reference and enables use
of an external master reference device.
Power ON & MODE Delay
Internal V
REF
1.30V
LVD
1.25V
200
52.5
1.07mA
1.07mA
20
52.5
SE
2.2V
Power ON
Power ON
SE 2.85V, 22.5mA
Latch
SE
DISC/HVD
LVD
SE
LVD(-) / SE
1 of 9
LVD(+) / SE
(Pseudo-GND)
SE
HVD
LVD
HVD
DIFF_CAP
DIFFSENSE
M/S
ISO
TPWR
LVD
Window
Comp.
LVD
SE
10mA
HVD
20k
MODE Control & Delay
5241/42 01 eps
IMP2
IMP2
1
1
1
1
9
9
IMP2
IMP2
1
1
1
1
9
9
© 2002 IMP, Inc.
Data Communications 1
D
ATA
C
OMMUNICATIONS
2
408-432-9100/www.impweb.com © 2002 IMP, Inc.
Ordering Information
Absolute Maximum Ratings
1
Thermal Data
Pin Configuration
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +7V
Operating Junction Temperature
Plastic (DB, PW Packages) . . . . . . . . . . . . . 150
°C
Storage Temperature Range . . . . . . . . . . . . . . 65
°C to 150°C
Note:
1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Lead Temperature (Soldering, 10 sec.) . . . . . . 300
°C
PW Package:
Thermal Resistance Junction-to-Ambient,
JA
. . . . . . 100
°C/W
1
2
3
4
28
27
26
25
5
6
7
8
NC
R1P
R1N
R2P
R2N
HS GND
R3P
R 3 N
TPWR
NC
R 9 N
R9P
R 8 N
R8P
HS GND
R7N
24
23
22
21
9
10
20
19
11
12
13
14
R4P
R 4 N
R5P
R 5 N
ISO
GND
R 6 N
R7P
R6P
DIFF_CAP
DIFFSENSE
MASTER/SLAVE
18
17
16
15
IMP2119
TSSOP-28
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
JA
).
The
JA
numbers are guidelines for the thermal performance of
the device/pc-board system. No ambient airflow is assumed.
r
e
b
m
u
N
t
r
a
P
e
g
n
a
R
e
r
u
t
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r
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p
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e
T
e
g
a
k
c
a
P
W
P
C
9
1
1
2
P
M
I
0°
0
7
o
t
C
°C
P
O
S
S
T
c
i
t
s
a
l
P
n
i
p
-
8
2
)
T
/
W
P
C
9
1
1
2
P
M
I
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e
.
i
(
.
r
e
b
m
u
n
t
r
a
p
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r
e
t
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l
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e
p
p
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,
l
e
e
R
d
n
a
e
p
a
T
r
o
F
:
e
t
o
N
s
p
e
.
2
0
t
_
2
4
/
1
4
2
5
PW Package
IMP2
IMP2
1
1
1
1
9
9
IMP2
IMP2
1
1
1
1
9
9
4
408-432-9100/www.impweb.com © 2002 IMP, Inc.
Unless otherwise specified, these specifications apply over the operating ambient temperature range of 0
°C T
A
70°C. TermPwr = 4.75V.
ISO : IMP2119 = LOW. Low duty cycle pulse testing techniques are used which maintain
junction and case temperatures equal to the ambient temperature.
r
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>
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2
µ
A
V
E
N
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T
,
V
4
o
t
V
0
=
A
2
= 5°C
V
0
.
2
ISO >
1
TPWR
V
,
V
0
=
E
N
I
L
V
7
.
2
=
y
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1
=
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1
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=
0
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5
0
.
5
1
A
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F
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(
K
N
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V
F
F
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V
5
7
.
2
=
0
0
2
µ
A
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(
K
A
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L
V
0
.
2
>
ISO
0
1
µ
A
T
A
2
= 5°C
n
o
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S
r
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t
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T
d
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C
,
n
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=
s
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n
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r
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a
n
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m
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e
t
ll
A
E
V
A
L
S
/
R
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T
S
A
M
V
0
=
7
0
1
A
m
,
V
2
.
0
=
s
e
n
il
r
o
t
a
n
i
m
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e
t
ll
A
E
V
A
L
S
/
R
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T
S
A
M
V
0
=
4
1
2
6
2
2
V
0
.
2
>
T
C
E
N
N
O
C
S
I
D
5
1
5
3
µ
A
e
g
a
t
l
o
V
h
g
i
H
t
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p
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u
O
r
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T
V
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6
.
2
5
8
.
2
V
t
n
e
r
r
u
C
t
u
p
t
u
O
I
O
V
T
U
O
V
2
.
0
=
1
2
3
2
4
2
A
m
t
n
e
r
r
u
C
k
n
i
S
I
K
N
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S
V
T
U
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s
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n
il
ll
a
,
V
4
=
5
4
5
6
A
m
e
c
n
a
t
i
c
a
p
a
C
t
u
p
t
u
O
C
O
V
0
.
2
>
ISO
5
.
2
F
p
t
n
e
r
r
u
C
e
g
a
k
a
e
L
I
K
A
E
L
V
0
.
2
>
ISO
2
µ
A
V
T
U
O
T
,
V
4
o
t
V
0
=
A
2
= 5°C
V
0
.
2
ISO >
I
TPWR
,
V
0
=
E
N
I
L
T
,
V
7
.
2
=
A
2
= 5°C
e
c
n
a
d
e
p
m
I
r
e
v
i
r
D
d
n
u
o
r
G
Z
G
A
m
1
=
I
0
0
1
n
w
o
d
t
u
h
S
l
a
m
r
e
h
T
0
5
1
°C
Recommended Operating Conditions
2
Electrical Characteristics
Note: 3. Open circuit fallsafe voltage.
IMP2
IMP2
1
1
1
1
9
9
IMP2
IMP2
1
1
1
1
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