1
QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2000
1999 Integrated Device Technology, Inc.
DSC - 5848
c
QS532807
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS CLOCK
DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
IN
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
8
O
9
O
10
FEATURES:
-
JEDEC compatible LVTTL level
-
10 low skew clock outputs
-
Clock input is 5V tolerant
-
Pinout and function compatible with QS5807
-
25
on-chip resistors available for low noise
-
Input hysteresis for better noise margin
-
Guaranteed low skew:
·
0.35ns output skew (same bank)
·
0.6ns output skew (different bank)
·
0.75ns part-to-part skew
-
Available in QSOP and SOIC packages
DESCRIPTION:
The QS532807 clock driver/buffer circuit can be used for clock
buffering schemes where low skew is a key parameter. The QS532807
offers ten non-inverting outputs. Designed in IDT's proprietary QCMOS
process, these devices provide low propagation delay buffering with on-
chip skew of 0.35ns for same-transition, same bank signals. The
QS532807 has on-chip series termination resistors for lower noise clock
signals. The QS532807 series resistor version is recommended for
driving unterminated lines with capacitive loading and other noise
sensitive clock distribution circuits. These clock buffer products are
designed for use in high-performance workstations, embedded and
personal computing systems. Several devices can be used in parallel
or scattered throughout a system for guaranteed low skew, system-wide
clock distribution networks.
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INDUSTRIAL TEMPERATURE RANGE
QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
PIN CONFIGURATION
QSOP/ SOIC
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
IN
G ND
O
1
G ND
V
C C
G ND
G ND
G ND
O
2
O
3
O
4
O
5
O
6
O
7
O
8
O
9
O
10
V
C C
V
C C
V
C C
SO 20-2
SO 20-8
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
Unit
V
TERM(2)
Supply Voltage to Ground
0.5 to +4.6
V
DC Output Voltage V
OUT
0.5 to V
CC
+0.5
V
V
TERM(3)
DC Input Voltage V
IN
0.5 to +7
V
V
AC
AC Input Voltage (pulse width
20ns)
-3
V
I
OUT
DC Output Current V
IN
< 0
-20
mA
DC Output Current Max. Sink Current/Pin
120
mA
T
STG
Storage Temperature
65 to +150
°C
T
J
Junction Temperature
150
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz, V
IN
= 0V)
QSOP
SOIC
Pins
Typ.
Max.
(1)
Typ.
Max.
(1)
Unit
C
IN
3
6
5
7
pF
NOTE:
1. This parameter is guaranteed but not production tested.
PIN DESCRIPTION
Pin Names
I/O
Description
IN
I
Clock Input
Ox
O
Clock Outputs
3
QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH for All Inputs
2
1.7
5.5
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW for All Inputs
0.5
--
0.8
V
V
IC
Clamp Diode Voltage
(3)
Vcc = Min., I
IN
= -18mA
--
0.7
1.2
V
V
OH
Output HIGH Voltage
Vcc = Min., I
OH
= -100
µ
A
Vcc - 0.2
--
--
V
Vcc = Min., I
OH
= -8mA
2.4
--
--
Vcc = Min., I
OL
= 100
µ
A
--
--
0.2
V
OL
Output LOW Voltage
Vcc = Min., I
OL
= 6mA
--
--
0.4
V
Vcc = Min., I
OL
= 8mA
--
--
0.5
I
IN
Input Leakage Current
Vcc = Max., V
IN
= V
CC
or GND
--
--
±1
µ
A
I
OFF
Input Power Off Leakage
Vcc = 0V, V
IN
= V
CC
or GND
--
--
±1
µ
A
I
OS
Short Circuit Current
(2,3)
Vcc = Max., V
OUT
= GND
60
195
--
mA
I
ODH
Output HIGH Current
Vcc = 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
50
80
200
mA
I
ODL
Output LOW Current
Vcc = 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
50
112
200
mA
V
T
Input Hysteresis
V
TLH
- V
THL
for All Inputs
--
0.2
--
V
R
OUT
Output Resistance
(4)
Vcc = Min., I
OL
= 12mA
--
28
--
NOTES:
1. Typical values are at V
CC
= 3.3V, T
A
= 25°C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
4. Output resistance represents the total output impedance of the logic device and includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or Vcc
0.01
100
µ
A
I
CC
Supply Current per Input HIGH
V
CC
= Max., V
IN
= 3V
Input toggling at 50% duty cycle
0.1
30
µ
A
I
CCD
Dynamic Power Supply Current per Output
(1)
V
CC
= Max., outputs Enabled
60
90
µ
A/MHz
I
C
Total Power Supply Current Examples
(1,3)
V
CC
= Max.,
Input at 50% duty cycle
f
I
= 10MHz
V
IN
= GND or Vcc
6
10
mA
V
CC
= Max.,
Input at 50% duty cycle
f
I
= 2.5MHz
V
IN
= GND or Vcc
1.5
3
NOTES:
1. Guaranteed by design but not tested. C
L
= 0pF.
2. Typical values are for reference only. Conditions are V
CC
= 3.3V, T
A
= 25°C.
3. I
C
= I
CC
+ (
I
CC
)(D
H
)(N
T
) + I
CCD
(f
O
)(N
O
)
where:
D
H
= Input Duty Cycle
N
T
= Number of TTL HIGH inputs at D
H
(one)
f
O
= Output Frequency
N
O
= Number of outputs at f
O
(ten)
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INDUSTRIAL TEMPERATURE RANGE
QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
C
LOAD
= 50pF (no resistor)
Symbol
Parameter
(1)
Min.
Max.
Unit
t
SK(01)
Skew between all outputs, same transition
--
0.5
ns
t
SK(P)
Pulse Skew; skew between opposite transitions of the same output (t
PHL
- t
PLH
)
--
0.5
ns
t
SK(T)
Part-to-part skew
(2)
--
1
ns
t
PLH
t
PHL
Propagation Delay
(3)
IN to Ox
1.5
5.2
ns
t
R
Output Rise Time, 0.8V to 2V
--
2
ns
t
F
Output Fall Time, 2V to 0.8V
--
2
ns
NOTES:
1. Skew parameters are guaranteed across temperature range, but not tested.
2. t
SK(T)
only applies to devices of the same transition, part type, temperature, power supply voltage, loading, and package.
3. The propagation delay range indicated by Min. and Max. specifications results from process and environmental variables. These propagation delays
do not imply limit skew.
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QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
50pF
V
IN
Pulse
G enerator
DU T
50
V
C C
V
O UT
Pulse generator for all puls es: f
1.0M Hz; t
F
2.5ns; t
R
2.5ns
INPU T
PART 1 O UTP UT
PART 2 O UTP UT
t
P LH 1
t
P HL 1
t
P LH 2
t
P HL 2
t
SK(t)
t
SK(t)
1.5V
3 V
0 V
V
O H
1.5V
1.5V
V
O H
V
O L
V
O L
t
SK (t)
=
t
PLH 2
-
t
PLH 1
or
t
PHL 2
-
t
PH L1
INPUT
OUTPUT
2V
0.8V
1.5V
3 V
0 V
V
O H
1.5V
V
O L
t
P L H
t
PH L
t
R
t
F
INPU T
OUTPUT
t
P LH
t
P H L
1.5V
3 V
0 V
V
O H
1.5V
V
O L
t
SK (p)
=
t
PHL
-
t
P LH L
INPUT
OUTPUT 1
t
P LH 1
1.5V
3 V
0 V
V
O H
1.5V
1.5V
V
O H
V
O L
V
O L
OUTPUT 2
t
P HL1
t
SK (0 1)
t
SK(0 1)
t
P LH 2
t
P HL 2
t
SK(01)
=
t
PLH 2
-
t
PLH 1
or
t
PHL 2
-
t
PHL1
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
PULSE SKEW -- t
SK(P)
OUTPUT SKEW -- t
SK(O1)
PART-TO-PART SKEW -- t
SK(T)
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INDUSTRIAL TEMPERATURE RANGE
QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
2975 Stender Way
800-345-7015 or 408-727-6116
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.
XXXX
Device Type
X
Package
SO
Q
532807
Guaranteed Low Skew CMOS Clock Driver/Buffer
QS
Small Outline IC (300 mil) (SO20-2)
Quarter-size Small Outline Package (SO20-8)
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