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Part Number ICS950806

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Integrated
Circuit
Systems, Inc.
ICS950806
Third party brands and names are the property of their respective owners.
Advance Information
Block Diagram
950806 Rev - 06/13/01
Recommended Application
CK-408 clock with driven mode only for Almador - M chipset
with P4 processor. Programmable for group to group skew.
Output Features:
·
3 Differential CPU Clock Pairs @ 3.3V
·
7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
·
3 PCI_F (3.3V) @ 33.3MHz
·
1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
·
1 REF (3.3V) @ 14.318MHz
·
5 3V66 (3.3V) @ 66.6MHz
·
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
·
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
or 66.6MHz
Features:
·
Provides standard frequencies and additional 5% and
10% over-clocked frequencies
·
Supports spread spectrum modulation:
No spread, Center Spread (±0.35%, ±0.5%, or ±0.75%),
or Down Spread (-0.5%, -1.0%, or -1.5%)
·
Offers adjustable PCI early clock via I
2
C interface
·
Selectable 1X or 2X strength for REF via I
2
C interface
·
Efficient power management scheme through PD#,
CLK_STOP# and PCI_STOP#.
·
Uses external 14.318MHz crystal
·
Stop clocks and functional control available through
I
2
C interface.
Key Specifications:
·
CPU Output Jitter <150ps
·
3V66 Output Jitter <250ps
·
66MHz Output Jitter (Buffered Mode Only) <100ps
·
CPU Output Skew <100ps
Pin Configuration
56-Pin 300mil SSOP
240mil 6.10 mm. Body, 0.50 mm. pitch TSSOP
Frequency Generator with 200MHz Differential CPU Clocks
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
* These inputs have 120K internal pull-up resistor to VDD.
1. Includes internal selectabel 10K resistor for adjustable PCI
early clock.
2. Internal pull-down to ground.
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
E_PCICLK1/PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
66MHz_OUT0/3V66_2
66MHz_OUT1/3V66_3
66MHz_OUT2/3V66_4
66MHz_IN/3V66_5
*PD#
VDDA
GND
Vtt_PWRGD#
2
2
E_PCICLK3/
REF
FS1
FS0
CLK_STOP#*
OP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL
I REF
GND
FS2
48MHz_USB/FS3
48MHz_DOT
VDD48
GND
3V66_1/VCH_CLK/FS4
PCI_STOP#*
3V66_0/FS5
VDD3V66
GND
SCLK
SDATA
2
2
2
ICS950806
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Functionality
66MHz_O UT
(2:0)
66MHz_IN
PCICLK_F
3V66 (4:2)
3V66_5
PCICLK
FS 2 FS 1 FS 0
MHz
MHz
MHz
MHz
MHz
0
0
0
66.66
66.66
66.66
66.66
33.33
0
0
1
100.00
66.66
66.66
66.66
33.33
0
1
0
200.00
66.66
66.66
66.66
33.33
0
1
1
133.33
66.66
66.66
66.66
33.33
1
0
0
66.66
66.66
66M Hz_IN
Inp ut
66M Hz_IN/2
1
0
1
100.00
66.66
66M Hz_IN
Inp ut
66M Hz_IN/2
1
1
0
200.00
66.66
66M Hz_IN
Inp ut
66M Hz_IN/2
1
1
1
133.33
66.66
66M Hz_IN
Inp ut
66M Hz_IN/2
CPUCLK
3V66
Bit
PLL2
PLL1
Spread
Spectrum
48MHz_USB
PCICLK (6:4, 2, 0)
E_PCICLK (1, 3)/PCICLK (1, 3)
3V66 (5:2,0)
66MHz_OUT (2:0)
48MHz_DOT
3V66_1_VCH_CLK
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
66MHz
DIVDER
PD#
CLK_STOP#
PCI_STOP#
MULTSEL
SDATA
SCLK
V _PWRED#
FS (5:0)
tt
I REF
66MHz_IN
Control
Logic
Config.
Reg.
REF
3
3
5
2
5
3
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK_F (2:0)
Stop
Stop
2
ICS950806
Advance Information
Pin Configuration
Power Groups
(Analog)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR
(Digital)
VDDPCI
VDD3V66
VDDCPU
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ICS950806
Advance Information
Maximum Allowed Current
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Host Swing Select Functions
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PCI Slect Functions
1
K
L
C
I
C
P
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3
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1
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.
1
Note:
E_PCICLK1 = 10K
resistor
E_PCICLK3 = 10K
resistor
0 = No resistor
1 = 10K
pull-up to VDD
4
ICS950806
Advance Information
Frequency Select Table 1
Frequency Select Table 2
Bit
66MHz _O UT
(2:0)
66MHz_IN
PC IC LK_F
3V66 (4:2)
3V66_5
PC IC LK
FS 5:3
FS 2 FS 1 FS 0
MHz
MHz
MHz
MHz
MHz
0
0
0
66.66
66.66
66.66
66.66
33.33
Standard Clocking
0
0
1
100.00
66.66
66.66
66.66
33.33
Standard Clocking
0
1
0
200.00
66.66
66.66
66.66
33.33
Standard Clocking
0
1
1
133.33
66.66
66.66
66.66
33.33
Standard Clocking
1
0
0
66.66
66.66
66M H z_IN
Inp ut
66M H z_IN /2
Standard Clocking
1
0
1
100.00
66.66
66M H z_IN
Inp ut
66M H z_IN /2
Standard Clocking
1
1
0
200.00
66.66
66M H z_IN
Inp ut
66M H z_IN /2
Standard Clocking
1
1
1
133.33
66.66
66M H z_IN
Inp ut
66M H z_IN /2
Standard Clocking
0
0
0
70.00
70.00
70.00
70.00
35.00
5% O ver-clocking
0
0
1
105.00
70.00
70.00
70.00
35.00
5% O ver-clocking
0
1
0
T ristate
T ristate
T ristate
T ristate
T ristate
T ristate
0
1
1
140.00
70.00
70.00
70.00
35.00
5% O ver-clocking
1
0
0
70.00
70.00
66M H z_IN
Inp ut
66M H z_IN /2
5% O ver-clocking
1
0
1
105.00
70.00
66M H z_IN
Inp ut
66M H z_IN /2
5% O ver-clocking
1
1
0
T est
T est
T est
T est
T est
T est
1
1
1
140.00
70.00
66M H z_IN
Inp ut
66M H z_IN /2
5% O ver-clocking
0
0
0
73.32
73.32
73.32
73.32
36.66
10% O ver-clocking
0
0
1
110.00
73.32
73.32
73.32
36.66
10% O ver-clocking
0
1
0
T ristate
T ristate
T ristate
T ristate
T ristate
T ristate
0
1
1
146.60
73.32
73.32
73.32
36.66
10% O ver-clocking
1
0
0
73.32
73.32
66M H z_IN
Inp ut
66M H z_IN /2
10% O ver-clocking
1
0
1
110.00
73.32
66M H z_IN
Inp ut
66M H z_IN /2
10% O ver-clocking
1
1
0
T est/2
T est/4
T est/4
T est/4
T est/8
T est
1
1
1
146.60
73.32
66M H z_IN
Inp ut
66M H z_IN /2
10% O ver-clocking
D e scription
Bit
C PUC LK
3V66
C locking Mode
From
000 to 101
(See T able 2)
110
(See T able 2)
111
(See T able 2)
Note:
FS2 controls 3V66, 66MHz_OUT (2:0), 3V66 (4:2), 66MHz_IN/3V66_5, PCICLK_F, and PCICLK clocks for
either buffered or unbuffered (PLL-driven) modes.
Note:
Default settings: FS (2:0) = left floating (unconnected).
Note:
Default settings: FS (5:3) = 000
Bit
FS 5
FS 4 FS3
0
0
0
Standard Clocking
No Spread (default) or +0.4%
0
0
1
Standard Clocking
0 to -0.5%, Down Spread
0
1
0
Standard Clocking
0 to -1.0%, Down Spread
0
1
1
Standard Clocking
0 to -1.5%, Down Spread
1
0
0
Standard Clocking
0.5%, Center Spread
1
0
1
Standard Clocking
0.75%, Center Spread
1
1
0
5% Over-clocking
0.35%, Center Spread
1
1
1
10% Over-clocking
0.35%, Center Spread
Des cription
CPUCLK, 3V66,
66MHz_OUT (2:0)/3V66
(4:2), 66MHz_IN/3V66_5,
PCICLK_F, and PCICLK
(controlled by FS 2:0)
(See Table 1)
Bit
Spread S election
5
ICS950806
Advance Information
Byte 0: Control Register
Notes:
1. For Byte1, Bits (3:7) refer to tables 4, 5, and 6.
2. R= Read only RW= Read and Write
3. PWD = Power on Default
4. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via I
2
C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I
2
C Byte 0 Bit3. In Software mode it is not allowed to pull the external
PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions.
The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these modes.
In Hardware mode the I
2
C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
2
C Byte 0 Bit 3 = 0)].
5. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC
off, and external resistor termination will bring CPUCLKC low.
Byte 1: Control Register
t
i
B
#
n
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P
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P
3
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2
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0
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4
5
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0
S
F
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R
1
t
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5
5
1
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1
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9
3
3
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3
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4
3
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3
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1
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C
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C
P
=
0
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C
I
C
P
=
1
4
t
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B
5
3
4
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e
r
(
4
S
F
5
t
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B
5
3
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C
V
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1
_
6
6
V
3
0
W
R
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H
M
8
4
/
z
H
M
6
6
t
c
e
l
e
S
H
C
V
z
H
M
8
4
=
1
,
z
H
M
6
6
=
0
6
t
i
B
3
3
5
S
F
0
p
u
r
e
w
o
p
n
o
d
e
l
p
m
a
s
n
i
p
5
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
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f
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R
7
t
i
B
-
d
e
l
b
a
n
E
d
a
e
r
p
S
0
W
R
n
O
d
a
e
r
p
S
=
1
,
f
f
O
d
a
e
r
p
S
=
0
Note: For PCI_STOP#, refer to table 3
t
i
B
#
n
i
P
e
m
a
N
D
W
P
3
e
p
y
T
2
n
o
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t
p
i
r
c
s
e
D
0
t
i
B
1
5
,
2
5
0
T
K
L
C
U
P
C
0
C
K
L
C
U
P
C
1
W
R
d
e
l
b
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E
=
1
,
d
e
l
b
a
s
i
D
=
0
5
1
t
i
B
8
4
,
9
4
1
T
K
L
C
U
P
C
1
C
K
L
C
U
P
C
1
W
R
d
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l
b
a
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=
1
,
d
e
l
b
a
s
i
D
=
0
5
2
t
i
B
4
4
,
5
4
2
T
K
L
C
U
P
C
2
C
K
L
C
U
P
C
1
W
R
d
e
l
b
a
n
E
=
1
,
d
e
l
b
a
s
i
D
=
0
5
3
t
i
B
1
5
,
2
5
0
C
/
T
K
L
C
U
P
C
l
o
r
t
n
o
C
0
W
R
#
P
O
T
S
_
U
P
C
f
o
n
o
i
t
r
e
s
s
a
h
t
i
w
0
C
/
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
s
w
o
l
l
A
g
n
i
n
n
u
r
e
e
r
F
=
1
g
n
i
n
n
u
r
e
e
r
f
t
o
N
=
0
4
t
i
B
5
3
,
3
3
1
/
0
_
6
6
V
3
1
W
R
e
d
o
m
1
/
0
_
6
6
V
3
g
n
i
n
n
u
r
e
e
r
F
=
1
g
n
i
n
n
u
r
e
e
r
f
t
o
N
=
0
5
t
i
B
,
2
2
,
1
2
4
2
,
3
2
5
/
4
/
3
/
2
_
6
6
V
3
1
W
R
e
d
o
m
5
/
4
/
3
/
2
_
6
6
V
3
g
n
i
n
n
u
r
e
e
r
F
=
1
g
n
i
n
n
u
r
e
e
r
f
t
o
N
=
0
6
t
i
B
8
4
,
9
4
1
C
/
T
K
L
C
U
P
C
l
o
r
t
n
o
C
0
W
R
#
P
O
T
S
_
U
P
C
f
o
n
o
i
t
r
e
s
s
a
h
t
i
w
1
C
/
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
s
w
o
l
l
A
g
n
i
n
n
u
r
e
e
r
F
=
1
g
n
i
n
n
u
r
e
e
r
f
t
o
N
=
0
7
t
i
B
4
4
,
5
4
2
C
/
T
K
L
C
U
P
C
l
o
r
t
n
o
C
0
W
R
#
P
O
T
S
_
U
P
C
f
o
n
o
i
t
r
e
s
s
a
h
t
i
w
2
C
/
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
s
w
o
l
l
A
g
n
i
n
n
u
r
e
e
r
F
=
1
g
n
i
n
n
u
r
e
e
r
f
t
o
N
=
0