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Part Number ICS950211

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Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Block Diagram
Pin Configuration
Recommended Application:
Brookdale and Brookdale -G chipset with P4 processor.
Output Features:
·
3 - Pairs of differential CPU clocks (differential current mode)
·
5 - 3V66 @ 3.3V
·
10 - PCI @ 3.3V
·
2 - 48MHz @ 3.3V fixed
·
1 - REF @ 3.3V, 14.318MHz
·
1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz
Features/Benefits:
·
Programmable output frequency.
·
Programmable output divider ratios.
·
Programmable output rise/fall time.
·
Programmable output skew.
·
Programmable spread percentage for EMI control.
·
Watchdog timer technology to reset system
if system malfunctions.
·
Programmable watch dog safe frequency.
·
Support I
2
C Index read/write and block read/write operations.
·
Uses external 14.318MHz crystal.
Key Specifications:
·
CPU Output Jitter <150ps
·
3V66 Output Jitter <250ps
·
CPU Output Skew <100ps
Programmable Timing Control HubTM for P4TM
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
56-Pin 300-mil SSOP & 240-mil TSSOP
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
Frequency Table
For additional frequency selections please refer to Byte 0.
* For 950211BF version, this frequency is 166.66MHz.
4
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PLL2
PLL1
Spread
Spectrum
48MHz_USB
PCICLK (6:0)
3V66 (5:2, 0)
48MHz_DOT
3V66_1/VCH_CLK
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
WDEN
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
SDATA
SCLK
Vtt_PWRGD#
FS (4:0)
I REF
Control
Logic
Config.
Reg.
REF
3
3
7
5
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK_F (2:0)
Stop
Stop
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
#
VDDA
GND
*Vtt_PWRGD#
1
1
1
*PD
REF
FS1
FS0
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
I REF
GND
FS2
48MHz_USB/FS3**
48MHz_DOT
AVDD48
GND
3V66_1/VCH_CLK/FS4**
PCI_STOP#*
3V66_0
VDD
GND
SCLK
SDATA
1
ICS950211
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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18
19
20
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48
47
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41
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39
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37
36
35
34
33
32
31
30
29
2
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Pin Description
The ICS950211 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR
memory. It provides all necessary clock signals for such a system.
The ICS950211 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
General Description
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Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Maximum Allowed Current
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3
Host Swing Select Functions
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4
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
General I
2
C serial interface information
How to Write:
· Controller (host) sends a start bit.
· Controller (host) sends the write address D2
(H)
· ICS clock will
acknowledge
· Controller (host) sends the begining byte location = N
· ICS clock will
acknowledge
· Controller (host) sends the data byte count = X
· ICS clock will
acknowledge
· Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
· ICS clock will
acknowledge each byte one at a time
· Controller (host) sends a Stop bit
How to Read:
· Controller (host) will send start bit.
· Controller (host) sends the write address D2
(H)
· ICS clock will
acknowledge
· Controller (host) sends the begining byte
location = N
· ICS clock will
acknowledge
· Controller (host) will send a separate start bit.
· Controller (host) sends the read address D3
(H)
· ICS clock will
acknowledge
· ICS clock will send the data byte count = X
· ICS clock sends
Byte N + X -1
· ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
· Controller (host) will need to acknowledge each byte
· Controllor (host) will send a not acknowledge bit
· Controller (host) will send a stop bit
*See notes on the following page
.
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X By
t
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X By
t
e
ACK
ACK
5
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Byte 0: Functionality and frequency select register (Default=0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
2. For 950211BF version, this frequency is 166.66MHz.
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4
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b
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W
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1
0
6
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
t
i
B
#
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B
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4
5
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B
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1
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l
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=
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=
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6
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c
a
b
d
a
e
R
4
S
F
3
ti
B
-
X
k
c
a
b
d
a
e
R
3
S
F
2
ti
B
-
X
k
c
a
b
d
a
e
R
2
S
F
1
ti
B
-
X
k
c
a
b
d
a
e
R
1
S
F
0
ti
B
-
X
k
c
a
b
d
a
e
R
0
S
F
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
-
X
)
k
c
a
b
d
a
e
R
(
L
E
S
T
L
U
M
6
ti
B
8
1
1
6
_
K
L
C
I
C
P
5
ti
B
7
1
1
5
_
K
L
C
I
C
P
4
ti
B
6
1
1
4
_
K
L
C
I
C
P
3
ti
B
3
1
1
3
_
K
L
C
I
C
P
2
ti
B
2
1
1
2
_
K
L
C
I
C
P
1
ti
B
1
1
1
1
_
K
L
C
I
C
P
0
ti
B
0
1
1
0
_
K
L
C
I
C
P
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
-
1
)
e
l
b
a
T
l
o
r
t
n
o
C
.
q
e
r
F
.
c
n
y
s
A
e
e
S
(
1
ti
b
l
o
r
t
n
o
c
.
q
e
r
f
.
c
n
y
s
A
6
ti
B
-
X
d
e
v
r
e
s
e
R
5
ti
B
3
3
1
0
_
6
6
V
3
4
ti
B
5
3
1
K
L
C
_
H
C
V
/
1
_
6
6
V
3
3
ti
B
4
2
1
5
_
6
6
V
3
2
ti
B
3
2
1
4
_
6
6
V
3
1
ti
B
2
2
1
3
_
6
6
V
3
0
ti
B
1
2
1
2
_
6
6
V
3
7
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Byte 7: Revision ID and Device ID Register
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
X
1
*
e
l
b
a
p
p
o
t
S
=
1
;
g
n
i
n
n
u
R
e
e
r
F
=
0
,l
o
r
t
n
o
C
g
n
i
n
n
u
R
e
e
r
F
0
C
/
T
K
L
C
U
P
C
6
ti
B
X
1
*
e
l
b
a
p
p
o
t
S
=
1
;
g
n
i
n
n
u
R
e
e
r
F
=
0
,l
o
r
t
n
o
C
g
n
i
n
n
u
R
e
e
r
F
1
C
/
T
K
L
C
U
P
C
5
ti
B
X
1
*
e
l
b
a
p
p
o
t
S
=
1
;
g
n
i
n
n
u
R
e
e
r
F
=
0
,l
o
r
t
n
o
C
g
n
i
n
n
u
R
e
e
r
F
2
C
/
T
K
L
C
U
P
C
4
ti
B
X
1
)
d
e
v
r
e
s
e
R
(
3
ti
B
X
1
)
d
e
v
r
e
s
e
R
(
2
ti
B
X
1
)
d
e
v
r
e
s
e
R
(
1
ti
B
X
1
)
d
e
v
r
e
s
e
R
(
0
ti
B
X
1
)
d
e
v
r
e
s
e
R
(
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
7
D
I
e
c
i
v
e
D
0
e
c
i
v
e
d
l
a
u
d
i
v
i
d
n
i
n
o
d
e
s
a
b
e
b
ll
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w
s
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l
a
v
D
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c
i
v
e
D
.
e
s
a
c
s
i
h
t
n
i
"
H
1
0
"
6
ti
B
6
D
I
e
c
i
v
e
D
0
5
ti
B
5
D
I
e
c
i
v
e
D
0
4
ti
B
4
D
I
e
c
i
v
e
D
0
3
ti
B
3
D
I
e
c
i
v
e
D
0
2
ti
B
2
D
I
e
c
i
v
e
D
0
1
ti
B
1
D
I
e
c
i
v
e
D
0
0
ti
B
0
D
I
e
c
i
v
e
D
1
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
3
ti
B
D
I
n
o
i
s
i
v
e
R
X
n
o
i
s
i
v
e
r
s
'
e
c
i
v
e
d
l
a
u
d
i
v
i
d
n
i
n
o
d
e
s
a
b
e
b
ll
i
w
s
e
u
l
a
v
D
I
n
o
i
s
i
v
e
R
6
ti
B
2
ti
B
D
I
n
o
i
s
i
v
e
R
X
5
ti
B
1
ti
B
D
I
n
o
i
s
i
v
e
R
X
4
ti
B
0
ti
B
D
I
n
o
i
s
i
v
e
R
X
3
ti
B
3
ti
B
D
I
r
o
d
n
e
V
0
)
d
e
v
r
e
s
e
R
(
2
ti
B
2
ti
B
D
I
r
o
d
n
e
V
0
)
d
e
v
r
e
s
e
R
(
1
ti
B
1
ti
B
D
I
r
o
d
n
e
V
0
)
d
e
v
r
e
s
e
R
(
0
ti
B
0
ti
B
D
I
r
o
d
n
e
V
1
)
d
e
v
r
e
s
e
R
(
Asynchronous Frequency Control Table
Byte 4
Byte 3
3V66 [0:3]
PCI_F [1:2]
PCICK [0:6]
Note
Bit 7
Bit 4
0
0
66.01 MHz
33.005 MHz
From Fix PLL (no
spread)
0
1
75.44 MHz
37.72 MHz
From Fix PLL (no
spread)
1
0
66.66 MHz
33.33 MHz
From main PLL
(Default)
1
1
88.01 MHz
44.005 MHz
From Fix PLL (no
spread)
* This functionality is only available in BF version.
8
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Byte 10: Programming Enable bit 8 Watchdog Control Register
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Byte 9: Watchdog Timer Count Register
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
7
D
W
0
·
X
o
t
d
n
o
p
s
e
r
r
o
c
s
ti
b
8
e
s
e
h
t
f
o
n
o
it
a
t
n
e
s
e
r
p
e
r
l
a
m
i
c
e
d
e
h
T
e
d
o
m
m
r
a
l
a
o
t
s
e
o
g
ti
e
r
o
f
e
b
ti
a
w
ll
i
w
r
e
m
it
g
o
d
h
c
t
a
w
e
h
t
s
m
0
9
2
s
i
p
u
r
e
w
o
p
t
a
tl
u
a
f
e
D
.
g
n
it
t
e
s
e
f
a
s
e
h
t
o
t
y
c
n
e
u
q
e
r
f
e
h
t
t
e
s
e
r
d
n
a
.
s
d
n
o
c
e
s
3
.
2
=
s
m
0
9
2
·
8
6
ti
B
6
D
W
0
5
ti
B
5
D
W
0
4
ti
B
4
D
W
0
3
ti
B
3
D
W
1
2
ti
B
2
D
W
0
1
ti
B
1
D
W
0
0
ti
B
0
D
W
0
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
8
v
i
d
N
X
8
ti
b
r
e
d
i
v
i
d
N
6
ti
B
6
v
i
d
M
X
e
h
t
o
t
d
s
o
p
s
e
r
r
o
c
)
0
:
6
(
v
i
d
M
f
o
n
o
it
a
t
n
e
s
e
r
p
s
e
r
l
a
m
i
c
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d
e
h
T
e
h
t
o
t
l
a
u
q
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s
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p
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w
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p
t
a
tl
u
a
f
e
D
.
e
u
l
a
v
r
e
d
i
v
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d
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n
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r
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f
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r
.
n
o
it
c
e
l
e
s
s
t
u
p
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d
e
h
c
t
a
l
5
ti
B
5
v
i
d
M
X
4
ti
B
4
v
i
d
M
X
3
ti
B
3
v
i
d
M
X
2
ti
B
2
v
i
d
M
X
1
ti
B
1
v
i
d
M
X
0
ti
B
0
v
i
d
M
X
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
m
a
r
g
o
r
P
e
l
b
a
n
E
0
ti
b
e
l
b
a
n
E
g
n
i
m
m
a
r
g
o
r
P
1
0
e
t
y
B
r
o
s
e
h
c
t
a
l
W
H
y
b
d
e
t
c
e
l
e
s
e
r
a
s
e
i
c
n
e
u
q
e
r
F
.
g
n
i
m
m
a
r
g
o
r
p
o
n
=
0
I
ll
a
e
l
b
a
n
e
=
2
.
g
n
i
m
a
r
g
o
r
p
C
6
ti
B
e
l
b
a
n
E
D
W
0
.
ti
b
e
l
b
a
n
E
g
o
d
h
c
t
a
W
.
e
l
b
a
n
E
=
1
,
e
l
b
a
s
i
d
=
0
.
e
u
l
a
v
d
e
h
c
t
a
l
N
E
D
W
e
ti
r
w
r
e
v
o
ll
i
w
ti
b
s
i
h
T
5
ti
B
m
r
a
l
A
D
W
0
s
u
t
a
t
s
m
r
a
l
a
=
1
l
a
m
r
o
n
=
0
s
u
t
a
t
S
m
r
a
l
A
g
o
d
h
c
t
a
W
4
ti
B
4
F
S
0
e
f
a
s
e
h
t
e
r
u
g
if
n
o
c
ll
i
w
s
ti
b
e
s
e
h
t
o
t
g
n
it
i
r
W
.
s
ti
b
y
c
n
e
u
q
e
r
f
e
f
a
s
g
o
d
h
c
t
a
W
e
l
b
a
t
4
:
7
,
2
ti
B
0
e
t
y
B
o
t
g
n
i
d
n
o
p
s
r
r
o
c
y
c
n
e
u
q
e
r
f
3
ti
B
3
F
S
0
2
ti
B
2
F
S
0
1
ti
B
1
F
S
0
0
ti
B
0
F
S
0
Byte 8: Byte Count Read Back Register
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
7
e
t
y
B
0
w
o
h
d
n
a
t
n
u
o
c
e
t
y
b
e
r
u
g
if
n
o
c
ll
i
w
r
e
t
s
i
g
e
r
s
i
h
t
o
t
g
n
it
ir
W
:
e
t
o
N
s
i
tl
u
a
f
e
d
,
k
c
a
b
d
a
e
r
e
b
ll
i
w
s
e
t
y
b
y
n
a
m
F
0
H
.
s
e
t
y
b
5
1
=
6
ti
B
6
e
t
y
B
0
5
ti
B
5
e
t
y
B
0
4
ti
B
4
e
t
y
B
0
3
ti
B
3
e
t
y
B
1
2
ti
B
2
e
t
y
B
1
1
ti
B
1
e
t
y
B
1
0
ti
B
0
e
t
y
B
1
9
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Byte 14: Spread Spectrum Control Register
Byte 15: Output Divider Control Register
Byte 13: Spread Spectrum Control Register
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
7
S
S
X
d
a
e
r
p
s
e
h
t
m
a
r
g
o
r
p
ll
i
w
ti
b
)
0
:
2
1
(
m
u
r
t
c
e
p
S
d
a
e
r
p
S
e
h
T
e
h
t
n
o
d
e
s
a
b
d
e
t
a
l
u
c
l
a
c
e
b
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t
s
d
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e
n
t
n
e
c
e
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p
d
a
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r
p
S
.
e
g
a
t
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p
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d
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a
t
n
u
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m
a
g
n
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d
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p
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,
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f
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n
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y
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C
V
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d
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F
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f
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D
.
y
c
n
e
u
q
e
r
f
6
ti
B
6
S
S
X
5
ti
B
5
S
S
X
4
ti
B
4
S
S
X
3
ti
B
3
S
S
X
2
ti
B
2
S
S
X
1
ti
B
1
S
S
X
0
ti
B
0
S
S
X
t
i
B
e
m
a
N
D
W
P
n
o
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t
p
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r
c
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D
7
t
i
B
d
e
v
r
e
s
e
R
X
d
e
v
r
e
s
e
R
6
t
i
B
d
e
v
r
e
s
e
R
X
d
e
v
r
e
s
e
R
5
t
i
B
d
e
v
r
e
s
e
R
X
d
e
v
r
e
s
e
R
4
t
i
B
2
1
S
S
X
2
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
1
1
S
S
X
1
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
0
1
S
S
X
0
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
9
S
S
X
9
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
8
S
S
X
8
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
3
v
i
D
U
P
C
X
4
e
s
e
h
t
a
i
v
d
e
r
u
g
i
f
n
o
c
e
b
n
a
c
o
i
t
a
r
r
e
d
i
v
i
d
k
c
o
l
c
2
U
P
C
o
t
r
e
f
e
r
e
l
b
a
t
n
o
i
t
c
e
l
e
s
r
e
d
i
v
i
d
r
o
F
.
y
ll
a
u
d
i
v
i
d
n
i
s
t
i
b
.
r
e
d
i
v
i
d
S
F
d
e
h
c
t
a
l
s
i
p
u
r
e
w
o
p
t
a
t
l
u
a
f
e
D
.
1
e
l
b
a
T
6
t
i
B
2
v
i
D
U
P
C
X
5
t
i
B
1
v
i
D
U
P
C
X
4
t
i
B
0
v
i
D
U
P
C
X
3
t
i
B
3
v
i
D
U
P
C
X
a
i
v
d
e
r
u
g
i
f
n
o
c
e
b
n
a
c
o
i
t
a
r
r
e
d
i
v
i
d
k
c
o
l
c
]
0
:
1
[
U
P
C
r
e
f
e
r
e
l
b
a
t
n
o
i
t
c
e
l
e
s
r
e
d
i
v
i
d
r
o
F
.
y
ll
a
u
d
i
v
i
d
n
i
s
t
i
b
4
e
s
e
h
t
.
r
e
d
i
v
i
d
S
F
d
e
h
c
t
a
l
s
i
p
u
r
e
w
o
p
t
a
t
l
u
a
f
e
D
.
1
e
l
b
a
T
o
t
2
t
i
B
2
v
i
D
U
P
C
X
1
t
i
B
1
v
i
D
U
P
C
X
0
t
i
B
0
v
i
D
U
P
C
X
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
7
v
i
d
N
X
e
h
t
o
t
d
n
o
p
s
e
r
r
o
c
)
0
:
8
(
v
i
d
N
f
o
n
o
i
t
a
t
n
e
s
e
r
p
e
r
l
a
m
i
c
e
d
e
h
T
e
h
t
o
t
l
a
u
q
e
s
i
p
u
r
e
w
o
p
t
a
t
l
u
a
f
e
D
.
e
u
l
a
v
r
e
d
i
v
i
d
O
C
V
.
1
1
e
t
y
B
n
i
d
e
t
a
c
o
l
s
i
8
v
i
d
N
e
c
i
t
o
N
.
n
o
t
c
e
l
e
s
s
t
u
p
n
i
d
e
h
c
t
a
l
6
t
i
B
6
v
i
d
N
X
5
t
i
B
5
v
i
d
N
X
4
t
i
B
4
v
i
d
N
X
3
t
i
B
3
v
i
d
N
X
2
t
i
B
2
v
i
d
N
X
1
t
i
B
1
v
i
d
N
X
0
t
i
B
0
v
i
d
N
X
10
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Byte 17: Output Divider Control Register
Byte 18: Group Skew Control Register
Byte 19: Group Skew Control Register
Table 1
Table 2
)
2
:
3
(
v
i
D
0
0
1
0
0
1
1
1
)
0
:
1
(
v
i
D
0
0
2
/
4
/
8
/
6
1
/
1
0
3
/
6
/
2
1
/
4
2
/
0
1
5
/
0
1
/
0
2
/
0
4
/
1
1
7
/
4
1
/
8
2
/
6
5
/
)
2
:
3
(
v
i
D
0
0
1
0
0
1
1
1
)
0
:
1
(
v
i
D
0
0
4
/
8
/
6
1
/
2
3
/
1
0
3
/
6
/
2
1
/
4
2
/
0
1
5
/
0
1
/
0
2
/
0
4
/
1
1
7
/
4
1
/
8
2
/
6
5
/
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
V
N
I
_
6
6
V
3
X
ti
b
n
o
i
s
r
e
v
n
I
e
s
a
h
P
]
2
:
3
[
6
6
V
3
6
ti
B
V
N
I
_
6
6
V
3
X
ti
b
n
o
i
s
r
e
v
n
I
e
s
a
h
P
6
6
V
3
5
ti
B
V
N
I
_
U
P
C
X
ti
b
n
o
i
s
r
e
v
n
I
e
s
a
h
P
2
K
L
C
U
P
C
4
ti
B
V
N
I
_
U
P
C
X
ti
b
n
o
i
s
r
e
v
n
I
e
s
a
h
P
]
0
:
1
[
K
L
C
U
P
C
3
ti
B
d
e
v
r
e
s
e
R
X
4
e
s
e
h
t
a
i
v
d
e
r
u
g
if
n
o
c
e
b
n
a
c
o
it
a
r
r
e
d
i
v
i
d
k
c
o
l
c
]
0
:
1
[
6
6
V
3
.
1
e
l
b
a
T
o
t
r
e
f
e
r
e
l
b
a
t
n
o
it
c
e
l
e
s
r
e
d
i
v
i
d
r
o
F
.
y
ll
a
u
d
i
v
i
d
n
i
s
ti
b
.
r
e
d
i
v
i
d
S
F
d
e
h
c
t
a
l
s
i
p
u
r
e
w
o
p
t
a
tl
u
a
f
e
D
2
ti
B
d
e
v
r
e
s
e
R
X
1
ti
B
d
e
v
r
e
s
e
R
X
0
ti
B
d
e
v
r
e
s
e
R
X
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
1
w
e
k
S
_
U
P
C
0
o
t
t
c
e
p
s
e
r
h
ti
w
2
T
/
C
K
L
C
U
P
C
e
h
t
y
a
l
e
d
s
ti
b
2
e
s
e
h
T
)
0
:
1
(
T
/
C
K
L
C
U
P
C
s
p
0
5
7
=
1
1
s
p
0
0
5
=
0
1
s
p
0
5
2
=
1
0
s
p
0
=
0
0
6
ti
B
0
w
e
k
S
_
U
P
C
1
5
ti
B
d
e
v
r
e
s
e
R
0
d
e
v
r
e
s
e
R
4
ti
B
d
e
v
r
e
s
e
R
0
d
e
v
r
e
s
e
R
3
ti
B
1
w
e
k
S
_
U
P
C
0
e
h
t
y
a
l
e
d
s
ti
b
2
e
s
e
h
T
)
0
:
1
(
T
/
C
K
L
C
U
P
C
o
t
t
c
e
p
s
e
r
h
ti
w
k
c
o
l
c
2
T
/
C
K
L
C
U
P
C
s
p
0
5
2
=
1
0
s
p
0
=
0
0
s
p
0
5
7
=
1
1
s
p
0
0
5
=
0
1
2
ti
B
0
w
e
k
S
_
U
P
C
1
1
ti
B
d
e
v
r
e
s
e
R
0
d
e
v
r
e
s
e
R
0
ti
B
d
e
v
r
e
s
e
R
0
d
e
v
r
e
s
e
R
t
i
B
e
m
a
N
D
W
P
e
c
n
e
u
q
e
S
g
n
i
m
m
a
r
g
o
r
P
7
ti
B
l
o
r
t
n
o
c
s
ti
b
4
e
s
e
h
T
)
1
:
3
(
6
6
V
3
-
U
P
C
1
0
0 0 0
s
p
0
d
e
v
r
e
s
e
R
6
ti
B
1
0
1 0 0
s
p
0
5
1
d
e
v
r
e
s
e
R
5
ti
B
1
1
0 0 0
s
p
0
0
3
d
e
v
r
e
s
e
R
4
ti
B
1
1
1 0 0
s
p
0
5
4
d
e
v
r
e
s
e
R
3
ti
B
l
o
r
t
n
o
c
s
ti
b
4
e
s
e
h
T
0
_
6
6
V
3
-
U
P
C
1
1
1 0 1
s
p
0
0
6
d
e
v
r
e
s
e
R
2
ti
B
1
1
1 1 0
s
p
0
5
7
d
e
v
r
e
s
e
R
1
ti
B
1
1
1 1 1
s
p
0
0
9
d
e
v
r
e
s
e
R
0
ti
B
1
d
e
v
r
e
s
e
R
d
e
v
r
e
s
e
R
Byte 16: Output Divider Control Register
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
3
v
i
D
I
C
P
X
a
i
v
d
e
r
u
g
if
n
o
c
e
b
n
a
c
o
it
a
r
r
e
d
i
v
i
d
k
c
o
l
c
]
2
:
3
[
6
6
V
3
r
e
f
e
r
e
l
b
a
t
n
o
it
c
e
l
e
s
r
e
d
i
v
i
d
r
o
F
.
y
ll
a
u
d
i
v
i
d
n
i
s
ti
b
4
e
s
e
h
t
.
r
e
d
i
v
i
d
S
F
d
e
h
c
t
a
l
s
i
p
u
r
e
w
o
p
t
a
tl
u
a
f
e
D
.
1
e
l
b
a
T
o
t
6
ti
B
2
v
i
D
I
C
P
X
5
ti
B
1
v
i
D
I
C
P
X
4
ti
B
0
v
i
D
I
C
P
X
3
ti
B
3
v
i
D
6
6
V
3
X
a
i
v
d
e
r
u
g
if
n
o
c
e
b
n
a
c
o
it
a
r
r
e
d
i
v
i
d
k
c
o
l
c
]
0
:
1
[
6
6
V
3
r
e
f
e
r
e
l
b
a
t
n
o
it
c
e
l
e
s
r
e
d
i
v
i
d
r
o
F
.
y
ll
a
u
d
i
v
i
d
n
i
s
ti
b
4
e
s
e
h
t
.
r
e
d
i
v
i
d
S
F
d
e
h
c
t
a
l
s
i
p
u
r
e
w
o
p
t
a
tl
u
a
f
e
D
.
1
e
l
b
a
T
o
t
2
ti
B
2
v
i
D
6
6
V
3
X
1
ti
B
1
v
i
D
6
6
V
3
X
0
ti
B
0
v
i
D
6
6
V
3
X
11
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Byte 20: Group Skew Control Register
Byte 21: Slew Rate Control Register
Byte 22: Slew Rate Control Register
Byte 23: Slew Rate Control Register
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
1
w
e
l
S
F
E
R
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
F
E
R
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
6
ti
B
0
w
e
l
S
F
E
R
0
5
ti
B
1
w
e
l
S
)
4
:
6
(
I
C
P
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
4
:
6
(
I
C
P
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
4
ti
B
0
w
e
l
S
)
4
:
6
(
I
C
P
0
3
ti
B
)
1
:
3
(
I
C
P
1
w
e
l
S
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
1
:
3
(
I
C
P
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
2
ti
B
)
1
:
3
(
I
C
P
0
w
e
l
S
0
1
ti
B
0
I
C
P
1
w
e
l
S
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
0
I
C
P
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
0
ti
B
0
I
C
P
0
w
e
l
S
0
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
d
e
v
r
e
s
e
R
X
d
e
v
r
e
s
e
R
6
ti
B
d
e
v
r
e
s
e
R
X
5
ti
B
1
w
e
l
S
H
C
V
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
H
C
V
k
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
4
ti
B
0
w
e
l
S
H
C
V
0
3
ti
B
1
w
e
l
S
B
S
U
8
4
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
B
S
U
8
4
k
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
2
ti
B
0
w
e
l
S
B
S
U
8
4
0
1
ti
B
1
w
e
l
S
T
O
D
8
4
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
T
O
D
8
4
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
0
ti
B
0
w
e
l
S
T
O
D
8
4
0
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
1
w
e
l
S
F
I
C
P
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
0
:
1
(
2
F
I
C
P
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
6
ti
B
0
w
e
l
S
F
I
C
P
0
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
0
:
1
(
1
F
I
C
P
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
5
ti
B
1
w
e
l
S
F
I
C
P
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
0
:
1
(
F
I
C
P
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
4
ti
B
0
w
e
l
S
F
I
C
P
0
3
ti
B
1
w
e
l
S
_
)
2
:
3
(
6
6
V
3
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
2
:
3
(
6
6
V
3
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
2
ti
B
1
w
e
l
S
_
)
2
:
3
(
6
6
V
3
0
1
ti
B
1
w
e
l
S
_
)
0
:
1
(
6
6
V
3
1
.
s
ti
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
0
:
1
(
6
6
V
3
k
a
e
w
=
0
1
;l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
0
ti
B
0
w
e
l
S
_
)
0
:
1
(
6
6
V
3
0
t
i
B
e
m
a
N
D
W
P
e
c
n
e
u
q
e
S
g
n
i
m
m
a
r
g
o
r
P
7
ti
B
l
o
r
t
n
o
c
s
ti
b
4
e
s
e
h
T
)
0
:
6
(I
C
P
-
U
P
C
1
0
0 0 0
s
p
0
d
e
v
r
e
s
e
R
6
ti
B
1
0
1 0 0
s
p
0
5
1
d
e
v
r
e
s
e
R
5
ti
B
1
1
0 0 0
s
p
0
0
3
d
e
v
r
e
s
e
R
4
ti
B
1
1
1 0 0
s
p
0
5
4
d
e
v
r
e
s
e
R
3
ti
B
l
o
r
t
n
o
c
s
ti
b
4
e
s
e
h
T
)
0
:
1
(
F
I
C
P
-
U
P
C
1
1
1 0 1
s
p
0
0
6
d
e
v
r
e
s
e
R
2
ti
B
1
1
1 1 0
s
p
0
5
7
d
e
v
r
e
s
e
R
1
ti
B
1
1
1 1 1
s
p
0
0
9
d
e
v
r
e
s
e
R
0
ti
B
1
d
e
v
r
e
s
e
R
d
e
v
r
e
s
e
R
12
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND ­0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . ­65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
-5
5
mA
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
mA
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
mA
Operating
C
L
= 0 pF; Select @ 66M
100
mA
Supply Current
C
L
= Full load
360
mA
IREF=2.32
25
mA
IREF= 5mA
45
mA
Input frequency
F
i
V
DD
= 3.3 V;
14.318
MHz
Pin Inductance
L
pin
7
nH
C
IN
Logic Inputs
5
pF
C
out
Out put pin capacitance
6
pF
C
INX
X1 & X2 pins
27
36
45
pF
Transition Time
1
T
trans
To 1st crossing of target Freq.
3
mS
Settling Time
1
T
s
From 1st crossing to 1% target Freq.
3
mS
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
3
mS
t
PZH
,t
PZH
output enable delay (all outputs)
1
10
nS
t
PLZ
,t
PZH
output disable delay (all outputs)
1
10
nS
1
Guaranteed by design, not 100% tested in production.
Input Capacitance
1
Delay
I
DD3.3OP
Power Down
Supply Current
I
DD3.3PD
13
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Electrical Characteristics - PCICLK
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
= 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Frequency
F0
1
33.33
MHz
Output Impedance
R
DSN1
1
V
O
= V
DD
*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.55
V
Output High Current
I
OH1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
-33
-33
mA
Output Low Current
I
OL1
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
30
38
mA
Rise Time
t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
1.52
2
ns
Fall Time
t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
1.45
2
ns
Duty Cycle
d
t1
1
V
T
= 1.5 V
45
51.5
55
%
Skew
t
sk1
1
V
T
= 1.5 V
155
500
ps
Jitter
t
jcyc-cyc
1
V
T
= 1.5 V
123
250
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Current Source
Output Impedance
Z
O
V
O
= V
X
3000
Output High Voltage
V
OH
0.71
1.2
V
Output High Current
I
OH
-13.92
mA
Rise Time
1
t
r
V
OL
= 20%, V
OH
= 80%
175
700
ps
Differential Crossover
Voltage
1
V
X
Note 3
45
50
55
%
Duty Cycle
1
d
t
V
T
= 50%
45
49.4
55
%
Skew
1
, CPU to CPU
t
sk
V
T
= 50%
40
100
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc
V
T
= V
X
90
150
ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
V
R
= 475W +1%; IREF = 2.32mA; I
OH
= 6*IREF
14
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Electrical Characteristics - 3V66
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Frequency
F
O1
66.66
MHz
Output Impedance
R
DSP1
1
V
O
= V
DD
*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.4
V
Output High Current
I
OH1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
-33
-33
mA
Output Low Current
I
OL1
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
30
38
mA
Rise Time
t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
3
2
ns
Fall Time
t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
1.3
2
ns
Duty Cycle
d
t1
1
V
T
= 1.5 V
45
52
55
%
Skew
t
sk1
1
V
T
= 1.5 V
155
500
ps
Jitter
tjcyc-cyc
1
V
T
= 1.5 V
150
250
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
= 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Frequency
F
O
1
V
O
= V
DD
*(0.5)
48
MHz
Output Impedance
R
DSN1
1
V
O
= V
DD
*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.55
V
Output High Current
I
OH1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
-29
-23
mA
Output Low Current
I
OL1
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
29
27
mA
48DOT Rise Time
t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
0.6
1
ns
48DOT Fall Time
t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
0.7
1
ns
VCH 48 USB
Rise Time
t
r
1
V
OL
= 0.4 V, V
OH
= 2.4 V
1
1.1
2
ns
VCH 48 USB
Fall Time
tf
1
V
OH
= 2.4 V, V
OL
= 0.4 V
1
1.2
2
ns
48 DOT to 48 USB
Skew
tskew
1
VT=1.5V
1
ns
Duty Cycle
d
t1
1
V
T
= 1.5 V
45
50.1
55
%
Jitter
t
jcyc-cyc
1
V
T
= 1.5 V
130
350
ps
1
Guaranteed by design, not 100% tested in production.
15
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Electrical Characteristics - REF
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=10-20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Frequency
F
O1
MHz
Output Impedance
R
DSP1
1
V
O
= V
DD
*(0.5)
20
60
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.4
V
Output High Current
I
OH1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
-29
-23
mA
Output Low Current
I
OL1
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
29
27
mA
Rise Time
t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V
1
4
ns
Fall Time
t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V
1
4
ns
Duty Cycle
d
t1
1
V
T
= 1.5 V
45
53
55
%
Jitter
t
jcyc-cyc
V
T
= 1.5 V
500
ps
1
Guaranteed by design, not 100% tested in production.
16
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
17
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
3V66
PCICLK_F and PCICLK
Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3V66
3V66
3V66 pin to pin skew
0
155
500
ps
PCI
PCI
PCI_F and PCI pin to pin skew
0
302
500
ps
3V66 to PCI
S
3V66-PCI
3V66 leads 33MHz PCI
1.5
1.7
3.5
ns
1
Guaranteed by design, not 100% tested in production.
PD# Functionality
#
P
O
T
S
_
U
P
C
T
U
P
C
C
U
P
C
6
6
V
3
T
U
O
_
z
H
M
6
6
F
_
K
L
C
I
C
P
K
L
C
I
C
P
K
L
C
I
C
P
T
O
D
/
B
S
U
z
H
M
8
4
1
l
a
m
r
o
N
l
a
m
r
o
N
z
H
M
6
6
N
I
_
z
H
M
6
6
N
I
_
z
H
M
6
6
N
I
_
z
H
M
6
6
z
H
M
8
4
0
t
l
u
M
*
f
e
r
i
t
a
o
l
F
w
o
L
w
o
L
w
o
L
w
o
L
w
o
L
18
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2
C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#
P
O
T
S
_
U
P
C
T
U
P
C
C
U
P
C
1
l
a
m
r
o
N
l
a
m
r
o
N
0
t
l
u
M
*
f
e
r
i
t
a
o
l
F
19
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Ordering Information
ICS950211yFLF-T
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0°
8°
0°
8°
MIN
MAX
MIN
MAX
56
18.31
18.55
.720
.730
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45°
h x 45°
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
Example:
Designation for tape and reel packaging
RoHS Compliant
Package Type
 F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
 ICS = Standard Device
ICS XXXX y F LF- T
20
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Ordering Information
ICS950211yGLF-T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
- C -
- C -
b
c
L
aaa
C
240 mil TSSOP Package
Example:
Designation for tape and reel packaging
RoHS Compliant
Package Type
 G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
 ICS = Standard Device
ICS XXXX y G LF- T
MIN
MAX
MIN
MAX
A
--
1.20
--
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
E
E1
6.00
6.20
.236
.244
e
L
0.45
0.75
.018
.030
N
a
0°
8°
0°
8°
aaa
--
0.10
--
.004
VARIATIONS
MIN
MAX
MIN
MAX
56
13.90
14.10
.547
.555
10-0039
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
0.50 BASIC
0.020 BASIC
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
21
Integrated
Circuit
Systems, Inc.
ICS950211
0465E--05/17/05
Revision History
Rev. Issue
Date Description
Page
#
E
5/17/2005
1. Updated Description on Byte 13.
2. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant".
9,19-20