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Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-46
Block Diagram
Pentium/Pro
TM
System Clock Chip
9148-46 Rev E 4/20/99
Pin Configuration
28 pin SSOP
Pentium is a trademark on Intel Corporation.
Generates system clocks for CPU, PCI, 14.314 MHz,
48 and 24MHz.
Supports single or dual processor systems
Skew from CPU (earlier) to PCI clock 1 to 4ns
Separate 2.5V and 3.3V supply pins
2.5V outputs: CPU
3.3V outputs: PCI, REF
No power supply sequence requirements
28 pin SSOP
Spread Sectrum operation optional for PLL1
CPU frequencies to 100MHz are supported.
The ICS9148-46 is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
Companion SDRAM buffers are ICS9179-03, and -12.
There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.
The I
2
C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
Clock outputs include two CPU (2.5V or 3.3V), five PCI (3.3V),
two REF (3.3V), one 48MHz, and one selectable 48_24MHz.
Ground Groups
GND = Ground Source Core, CPUCLK (0:1)
GND1 = REF(0:1), X1, X2
GND2 = PCICLK_F, PCICLK (0:5)
GND3=48MHz, 24/48MHz
Power Groups
VDD = Supply for PLL core
VDD1 = REF(0:1), X1, X2
VDD2 = PCICLK_F, PCICLK (0:3)
VDD3 = 48MHz, 24/48MHz
VDDL = CPUCLK (0:1)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9148-46
Pin Descriptions
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3
ICS9148-46
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Read:
4
ICS9148-46
Note: PWD = Power-Up Default
Byte 3: Functionality & Frequency Select
& Spread Slect Register
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 4:
Notes: 1 = Enabled; 0 = Disabled, outputs held low
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Notes: 1 = Enabled; 0 = Disabled, outputs held low
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Notes: 1 = Enabled; 0 = Disabled, outputs held low
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ICS9148-46
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= V
DDL
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+0.3
V
Input Low Voltage
V
IL
V
SS
-0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
0.1
5
µ
A
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
2.0
µ
A
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
-100
µ
A
Operating
I
DD3.3OP66
C
L
= 0 pF; Select @ 66MHz
60
170
mA
Supply Current
I
DD3.3OP100
C
L
= 0 pF; Select @ 100MHz
66
170
mA
Power Down
I
DD3.3PD
C
L
= 0 pF; With input address to Vdd or GND
3
650
µ
A
Supply Current
Input frequency
F
i
V
DD
= 3.3 V;
14.318
MHz
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
36
45
pF
Transition Time
1
T
trans
To 1st crossing of target Freq.
3
ms
Settling Time
1
T
s
From 1st crossing to 1% target Freq.
5
ms
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
3
ms
Skew
1
T
AGP-PCI1
V
T
= 1.5 V;
1
3.5
4
ns
1
Guaranteed by design, not 100% tested in production.
Input Capacitance
1
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating
I
DD2.5OP 66
C
L
= 0 pF; Select @ 66.8 MHz
16
72
mA
Supply Current
I
DD2.5OP 100
C
L
= 0 pF; Select @ 100 MHz
23
100
mA
Power Down Supply
Current
I
DD2.5PD
C
L
= 0 pF; With input address to
Vdd or GND
10
100
µ
A
t
CP U-AGP
0
0.5
1
ns
t
CP U-P CI2
V
T
= 1.5 V; V
TL
= 1.25 V
1
2.6
4
ns
1
Guaranteed by design, not 100% tested in production.
Skew
1
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