DS07-16310-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-Bit Microcontroller

CMOS

FR30 Series

MB91F127/F128

DESCRIPTION

This model, designed on the basis of 32-bit RISC CPU (FR30 series), is a standard single-chip micro controller
with built-in I/O resources and bus control functions. The functions are suitable for built-in control that requires
high-speed CPU processing.
MB91F127 includes 256 Kbytes built-in flash memory and 14 Kbytes built-in RAM. MB91F128 includes 510 Kbytes
built-in flash memory and 14 Kbytes built-in RAM.
The specifications of the devices are best suited for applications requiring high-level CPU processing capabilities,
such as navigation system, high-performance FAX, and printer controller.

FEATURES

FR-CPU

ˇ 32-bit RISC (FR30), load/store architecture, 5-step pipeline
ˇ Operating frequency : Internal 25 MHz
ˇ General register : 32bit x 16 registers
ˇ 16-bit fixed-length instructions (primitives), 1 instruction/1 cycle
ˇ Instructions of memory-to-memory transfer, bit processing, and barrel shift : Instructions suitable for built-in

control

(Continued)

PACKAGE

100 pin, Plastic LQFP

(FPT-100P-M05)

MB91F127/F128

ˇ Function entry/exit instructions, multi load/store instruction for register data : High-level language compatible

instructions

ˇ Register interlock functions : Simple description of assembler language
ˇ Branch instructions with delay slot : Reduced overhead on branching process
ˇ Built-in multiplier/ Supporting at instruction level

Signed 32-bit multiplying : 5 cycles
Signed 16-bit multiplying : 3 cycles

ˇ Interrupt (saving PC and PS) : 6 cycles, 16 priority levels

Bus interface

ˇ Maximum of 25 MHz internal operation rate
ˇ 25-bit address bus (32 MB space)
ˇ 16-bit address output, 8/16-bit data input/output
ˇ Basic bus cycle : 2-clock cycle
ˇ Chip selection outputs specifiable in a minimum of 64 Kbytes steps : 6 outputs
ˇ Automatic wait cycle : Specifiable flexibly from 0 cycle to 7 cycles for each area
ˇ Supporting time-division input/output interface for address/data (for area 1 only)
ˇ Unassigned data/address terminals are available as input/output ports
ˇ Supporting little endian mode (selecting one area from area 1 to area 5)

DMAC (DMA controller)

ˇ 8 channels
ˇ Transfer factor : Interrupt request of built-in resources
ˇ Transfer sequence : Step transfer/Block transfer/Burst transfer/Consecutive transfer
ˇ Transfer data length : Selectable among 8 bits, 16 bits, and 32 bits
ˇ Pausing is allowed by interrupt request

UART

ˇ 3 channels
ˇ Full-duplex double buffer
ˇ Data length : 7 to 9 bits (no parity), 6 to 8 bits (with parity)
ˇ Asynchronous (start-stop synchronization) or CLK synchronous communication is selectable
ˇ Multi processor mode
ˇ Built-in 16-bit timer (U-Timer) used as a baud-rate generator : Generates an arbitrary baud rate
ˇ External clock is available as a transfer clock
ˇ Error detection : parity, frame, and overrun

A/D converter (sequential transducer)

ˇ 8/10-bit resolution, 8 channels
ˇ Sequential comparison and transducer : At 25 MHz, 5.2

ˇ Built-in sample and hold circuit
ˇ Conversion mode : Selectable among single conversion, scan conversion, and repeat conversion
ˇ Activation : Selectable among software, external trigger, and built-in timer

Reload timer

ˇ 16-bit timer : 3 channels
ˇ Internal clock : 2-clock cycle resolution, selectable among 2/8/32 dividing and external clock

(Continued)

MB91F127/F128

(Continued)

Other interval timers

ˇ 16-bit timer : 3 channels (U-Timer)
ˇ PPG timer : 4 channels
ˇ 16-bit OCU : 4 channels, ICU : 4 channels, Free-run timer : 1 channel
ˇ Watchdog timer: 1 channel

Flash memory 510 KB

ˇ 510 KB FLASH ROM: Read/Write/Erase is allowed with a same power

Built- in RAM 14 KB

ˇ D-bus RAM 12 KB, C-bus RAM 2 KB

Bit search module

ˇ Position of a first bit that changes between "1" and "0" is searched in one cycle, within an MSB of one word.

Interrupt controller

ˇ External interrupt input : Normal interrupt

6 (INT0 to INT5)

ˇ Internal interrupt factors : UART, DMAC, A/D, Reload timer, UTIMER, delay interrupt, PPG, ICU, and OCU
ˇ Priority levels are programmable (16 levels)

Reset factors

ˇ Power-on reset/watchdog timer/software reset/external reset

Low power consumption mode

ˇ Sleep/stop mode

Clock control

ˇ Built-in PLL circuit, selectable among 1-multiplication, and 2-multiplication
ˇ Gearing function : Operation clock frequencies are freely and independently specifiable for CPU and

peripherals.
Gear clocks are selectable among 1/1, 1/2, 1/4, and 1/8 (or among 1/2, 1/4, 1/8, and 1/16).
Upper limit of peripheral operations is 25 MHz.

Others

ˇ Package : LQFP-100
ˇ CMOS technology : 0.35

ˇ Power supply voltage : 3.3 V

0.3 V

SERIES CONFIGURATION

Model name

MB91F127

MB91F128

MB91FV129

Outline

Quantity production

Evaluation product

FLASH memory

256 KB

510 KB

D-bus RAM

12 KB

16 KB

C-bus RAM

2 KB

MB91F127/F128

PIN ASSIGNMENT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

PG5/OC1
PG6/OC2
PG7/OC3

VCC

PA6/CLK

PA5/CS5/SC1

PA4/CS4/SI1

PA3/CS3/SO1

PA2/CS2
PA1/CS1
PA0/CS0

P86/ALE

HST
RST
VSS

MD0
MD1
MD2

P80/RDY

P81/BGRNT/IN0

P82/BRQ/IN1

P83/RD

P84/WR0
P85/WR1

P20/D16

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

PJ3/AN3
PJ2/AN2
PJ1/AN1
PJ0/AN0
AVSS/AVRL
AVRH
AVCC
P70/A24/FRCK/TCI2
P67/A23/IN3
P66/A22/IN2
VSS
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A09
P50/A08

100

PG4/OC0

PG3/OCPA3

PG2/OCPA2

PG1/OCPA1

PG0/OCPA0

PE0/INT0

PE1/INT1

VCC

VSS

PE2/INT2

PE3/INT3

PE4/INT4/TCI1

PE5/INT5/SC0

PE6/SI0

PE7/SO0

PF3/SC2/ATG

PF2/SO2

PF1/SI2

PF0/TCI0

PJ7/AN7

PJ6/AN6

PJ5/AN5

PJ4/AN4

P21/D17

P22/D18

P23/D19

P24/D20

P25/D21

P26/D22

P27/D23

P30/D24

P31/D25

P32/D26

P33/D27

P34/D28

P35/D29

P36/D30

VSS

P37/D31

P40/A00

VCC

P41/A01

P42/A02

P43/A03

P44/A04

P45/A05

P46/A06

P47/A07

(TOP VIEW)

(FPT-100P-M05)

MB91F127/F128

PIN DESCRIPTION

Note that the numbers in the table are not pin numbers on a package.

(Continued)

No.

Pin name

Input/output

circuit type

Description

1
2
3
4
5
6
7
8

D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27

Bit 16 through bit 23 of external data bus.
The terminals are available as general I/O ports (P20 through
P27) when external bus width is specified at 8 bits or in single-
chip mode.

10
11
12
13
14
15
16

D24/P30
D25/P31
D26/P32
D27/P33
D28/P34
D29/P35
D30/P36
D31/P37

Bit 24 through bit 31 of external data bus.
The terminals are available as general I/O ports (P30 through
P37) when the terminals are not used.

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

A00/P40
A01/P41
A02/P42
A03/P43
A04/P44
A05/P45
A06/P46
A07/P47
A08/P50
A09/P51
A10/P52
A11/P53
A12/P54
A13/P55
A14/P56
A15/P57

Bit 00 through bit 15 of external address bus.
The terminals are available as general I/O ports (P40 through
P47 and P50 through P57) when the terminals are not used as
address buses.

33
34
35
36
37
38
39
40

A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65

A22/P66/IN2
A23/P67/IN3

Bit 16 through bit 23 of external address bus.
The terminals are available as general I/O ports (P60 through
P67) when the terminals are not used as address busses.
[IN2,IN3]: Input terminals of input capture.
This function is active when input capture is operating.

MB91F127/F128

(Continued)

No.

Pin name

Input/output

circuit type

Description

A24/P70/FRCK/

TCI2

Bit 24 of external address bus.
[P70] A24, FRCK and TCI2 are available as general input ports
when they are not used.
[FRCK] External clock input of free-run timer. This function is
active when external clock input of free-run timer is used.
[TCI2] External clock input of timer 2. This function is active
when external clock input of timer 2 is used.

RDY/P80

External ready input. Enter "0" when bus cycle under execution
does not complete. This terminal is available as general input/
output port when it is not used.

BGRNT/P81/IN0

External bus open receive output. This terminal outputs "L"
when an external bus is released. This terminal is available as
general input/output port when it is not used.
[IN0] Input capture input.
This function is active when input capture is under input opera-
tion.

BRQ/P82/IN1

External bus open request input. Enter "1" when releasing exter-
nal bus. This terminal is available as general input/output port
when it is not used.
[IN1] Input capture input.
This function is active when input capture is under input opera-
tion.

RD/P83

External bus read strobe.
This terminal is available as general input/output port when it is
not used.

WR0/P84

External bus write strobe.Control signals and data bus byte po-
sitions are related as the following :

WR1/P85

48
49
50

CS0/PA0
CS1/PA1
CS2/PA2

Chip select 0 output (Low active)
Chip select 1 output (Low active)
Chip select 2 output (Low active)
[PA0,1,or 2] Available as general input/output ports when CS0,
CS1 and CS2 are not used.

Note : WR1 is set to Hi-z during resetting.

For using with 16-bit bus width, use an external pull-up
resistor.

[P84 or P85] Available as general input/output ports when WR0
and WR1 are not used.

16-bit bus

width

8-bit bus width

Single chip

mode

D31 to D24

WR0

(port allowed)

D23 to D16

WR1

(port allowed)

MB91F127/F128

(Continued)

No.

Pin name

Input/output

circuit type

Description

51
52
53

CS3/PA3/SO1

CS4/PA4/SI1

CS5/PA5/SC1

Chip select 3, 4, 5 output (Low active).
[PA3,4,5] Available as general input/output ports when channel
1 of chip select UART is not used.
[SO1,SI1,SC1] Data output, data input, and clock terminals of
UART1. Active when UART1 operation is allowed.

CLK/PA6

System clock output. Outputs a same clock as the same fre-
quency of external bus operation.
[PA6] Available as general input/output ports it is not used.

55
56
57
58
59
60
61
62

OCPA0/PG0
OCPA1/PG1
OCPA2/PG2
OCPA3/PG3

OC0/PG4
OC1/PG5
OC2/PG6
OC3/PG7

[OCPA0 to 3] PPG timer outputs. The function is active when
PPG timer output is allowed.
[OC0 to 3] Output comparison output. The function is active
when output comparison output is allowed. [PB0-7] Available as
general input/output ports it is not used.

63
64
65

MD0
MD1
MD2

Mode terminals 0 through 2. The terminals specify basic opera-
tion mode of MCU.
Use the terminals by connecting them directly to VCC or VSS.

66
67

X0
X1

Clock (oscillation) input.
Clock (oscillation) output.

RST

External reset input.

HST

Hardware standby input.

P86/ALE

[ALE] Address latch signal output. The function is active when
ALE output of EPCR is allowed.

71
72

INT0/PE0
INT1/PE1
INT2/PE2
INT3/PE3

[INT0,1,2,3] External interrupt request inputs. The input is used
whenever necessary if external interrupt is allowed. Output of
other functions must be suspended if not on purpose.

[PE0,1,2,3] General input/output port

75
76

INT4/PE4/TCI1

INT5/PE5/SC0

[INT4,5] External interrupt request inputs.The input is used
whenever necessary if concerned external interrupt is allowed.
Output of other functions must be suspended if not on purpose.
[TCI1] External clock input of timer 1. [SC0] Clock input of
UART0.

[PE4,5] General input/output port

SI0/PE6

[SI0] Data input of UART0.This function is active when data in-
put of UART0 is allowed.

[PE6]General input/output port

SO0/PE7

[SO0] Data output of UART0.This function is active when data
output of UART0 is allowed.

[PE7] General input/output port

MB91F127/F128

(Continued)

Note : Most of the above terminals multiplex inputs and outputs of I/O ports and resources, as indicated as "XXXX/

PXX". If the outputs of ports and resources conflict with each other on the terminals, resources take prefer-
ences.

No.

Pin name

Input/output

circuit type

Description

PF0/TCI0

[TCI0] External clock input of timer 0.

[PF0] General input/output port

SI2/PF1

[SI2] Data input of UART2.This function is active when data in-
put of UART2 is allowed.

[PF1] General input/output port

SO2/PF2

[SO2] Data output of UART2.This function is active when data
output of UART2 is allowed.

[PF2] General input/output port. This function is active when
data output of UART2 is disallowed.

SC2/PF3/ATG

[SC2] Clock input of UART2
[ATG]External trigger input of A/D converter The input is used
whenever necessary if a function concerned is selected.
Output of other functions must be suspended if not on purpose.

[PF3] General input/output port

83 to 90

AN0/PJ0
AN1/PJ1
AN2/PJ2
AN3/PJ3
AN4/PJ4
AN5/PJ5
AN6/PJ6
AN7/PJ7

[AN0 to AN7] Analog input of A/D converter.
This function is active when analog input is specified in AIC reg-
ister.

[PJ0 through PJ7] General input/output ports

AVCC

VCC power supply for A/D converter

AVRH

Reference voltage of A/D converter (high potential side). Be
sure to turn on or off this terminal with a potential higher than
AVRH applied to VCC.

AVSS/AVRL

A/D converter VSS power source and reference voltage (low po-
tential side).

94 to 96

VCC

Power sources of digital circuits. Be sure to connect power
source to all terminals when the device is used.

97 to 100

VSS

Ground level of digital circuits.

MB91F127/F128

INPUT/OUTPUT CIRCUIT TYPE

Type

Circuit

Remarks

ˇ For 25 MHz system
ˇ Oscillation feedback register :

Approx. 1M

ˇ Standby control is available.

ˇ CMOS level input
ˇ High-voltage control is avail-

able for FLASH test.

ˇ CMOS level hysteresis input
ˇ Standby control is not avail-

able.

ˇ CMOS level output
ˇ CMOS level hysteresis input
ˇ Standby control is available

ˇ Standby control is available
ˇ CMOS level output
ˇ CMOS level hysteresis input
ˇ Analog input

Clock input

STANDBY

Diffused resistor

Control

signal

Mode input

P-channel transistor

N-channel transistor

CMOS

Digital input

Diffused

resistor

Digital output

Digital input

Diffused

resistor

STANDBY

Digital output

Digital input

Diffused

resistor

Analog input

STANDBY

MB91F127/F128

HANDLING DEVICES

Preventing latch up

On a CMOS IC, latch up may occur when a voltage higher than VCC or a voltage lower than VSS is applied to
input terminal or output terminal, or when a voltage exceeding rated level is applied across VCC and VSS. Latch
up causes drastic increase of power source current, which may result in destruction of the element by heat.
Take extra care not to exceed maximum rating in use. Also, take extra care so that analog terminal does not
exceed digital power source.

Treatment of unused input terminals

Leaving unused terminals open may cause malfunction. Apply pull-up or pull-down treatment on unused
terminals.

External reset input

Complete resetting of internal system requires inputting "L" level signal to RST terminal for a minimum of
5 machine cycles.

Notes on using external clock

When using an external clock, supply a clock signal to X0 terminal and supply its antiphase clock to X1 terminal
simultaneously. In this case, do not use STOP mode (oscillation stop mode). (Because X1 terminal halts with
"H" output under STOP status.)

Under a 12.5 MHz frequency, the device operates with a clock supplied to X0 terminal only.

Figures show examples of using an external clock.

Example of using external clock (normal)

Note : STOP mode (oscillation stop mode) is not available.

Example of using external clock (allowed under operation at 12.5 MHz or lower frequency)

OPEN

MB91F127/F128

Connecting power supply terminals (VCC, VSS)

If two or more VCC, VSS terminals are used, the terminals to be placed under the same potentials are connected
with each other internally for preventing malfunctions such as latch up. However, for reducing unwanted radiation,
preventing malfunctions of strobe signals and observing total power and current ratings, be sure to connect all
of these terminals to power supply and ground externally.

Connecting power supply to VCC - VSS in impedance as low as possible is desirable.

Crystal oscillator circuit

Noises around X0 and X1 terminals causes malfunction of the device. Design printed wiring so that X0, X1,
and crystal oscillator (or ceramic oscillator), and bypass capacitor to the ground are aligned as close as possible
one another. Also the wiring of those elements should not cross with other wiring if possible. Printed wiring
with ground wires around X0 and X1 terminals ensures more stable operations. Such designing is strongly
recommended.

Treating NC terminals

Be sure to leave NC terminals open.

Mode terminals (MD0 through MD2)

Do not connect the mode terminals directly to VCC or VSS.

For preventing malfunctions caused by noises, make printed traces between the mode terminals and VCC or
VSS as short as possible, and connect the elements in lower impedance.

Turning power on

Be sure to turn on the power of the device with RST terminal placed under "L" level. Ensure a period at a
minimum of 5 cycles of internal operation clock before placing the terminal under "H" level.

10. Terminal status upon turning on power

Status upon turning on the power is indefinite. Upon turning on the power, oscillation starts and the circuit is
initialized.

11. Oscillation input upon turning on power

Upon turning on the power, be sure to input a clock signal until oscillation stabilizing wait status is released.

12. Initializing power-on reset

The device includes some built-in registers that are initialized only with power-on reset operation. For initializing
the registers, perform power-on reset by turning on the power again.

13. Recovery from Sleep/Stop status

For recovering from Sleep/Stop status initiated by a program in C-Bus RAM, reset the device instead of
recovering by an interrupt process.

MB91F127/F128

BLOCK DIAGRAM

FR CPU

RAM (12 Kbytes)

DMA controller

(8 ch.)

Bit search module

Clock control unit
(Watchdog timer)

Interrupt control unit

UART (3 ch)

Reload timer (3 ch)

PPG

ICU, OCU

Free run timer

Port E, F, G, J

10-bit

A/D converter

(8 ch.)

Bus converter (32 bits - 16 bits)

Bus converter

(Harvard - Princeton)

Bus

controller

Port2, 3, 4, 5, 6,

7, 8, A

RAM (2 Kbytes)

Flash memory

MB91F127:256 KB
MB91F128:510 KB

D-b

us (32 bits)

R-b

us (16 bits)

C-b

us (32 bits)

I-b

us (16 bits)

X0
X1

RST
HST

INT0 to

INT5

AN0 to AN7

AVCC

AVSS/AVRL

AVRH

ATG

SI0 to SI2

SO0 to SO2

SC0 to SC2

TCI0 to TCI2

OC0 to OC3

IN0 to IN3

FRCK

OCPA0 to OCPA3

D16 to D31
A00 to A24
RD
WR0, WR1
RDY
CLK
BRQ
BGRNT
CS0 to CS5

ALE

3
3
3

16
25

Notes :

Terminals are described in functional groups (actual terminals are partially multiplexed).

For using REALOS, perform time management by external interrupt or built-in timer.

MB91F127/F128

CPU CORE MEMORY SPACE

ˇ MB91F127

0000 0000

0000 0400

0000 0800

0000 1000

0000 4000

0001 0000

FFFF FFFF

0001 0000

0008 0000

0008 0800

0010 0000

FFFF FFFF

I/O

FLASH ROM

256 KB

FLASH ROM

256 KB

000C 0000

External ROM

External bus mode

Internal ROM

External bus mode

Single-chip mode

Access inhibit

Internal RAM

12 KB

Access inhibit

External area

Access inhibit

Internal RAM

12 KB

Access inhibit

Internal RAM

12 KB

Access inhibit

External area

Internal RAM

2 KB

Internal RAM

2 KB

Access inhibit

Direct

addressing

areas

I/O map

External area

Access inhibit

Note : External area is not accessible in single-chip mode. When accessing to external areas, select the internal

ROM external bus mode in mode register.

Direct addressing areas

The areas described below are used for I/O processes. The areas, referred to as "direct addressing areas,"
allow specifying an operand address directly by an instruction. The direct addressing areas varies as the
following, depending on size of the data to be accessed.
ˇ Byte-data access : 0 to 0FF

ˇ Half-word data access : 0 to 1FF

ˇ Word-data access : 0 to 3FF

Access inhibit

MB91F127/F128

ˇ MB91F128

0000 0000

0000 0400

0000 0800

0000 1000

0000 4000

0001 0000

FFFF FFFF

0001 0000

0008 0000

0008 0800

0010 0000

FFFF FFFF

I/O

FLASH ROM

510 KB

FLASH ROM

510 KB

External ROM

External bus mode

Internal ROM

External bus mode

Single-chip mode

Access inhibit

Internal RAM

12 KB

Access inhibit

External area

Access inhibit

Internal RAM

12 KB

Access inhibit

Internal RAM

12 KB

Access inhibit

External area

Internal RAM

2 KB

Internal RAM

2 KB

Access inhibit

Direct

addressing

areas

I/O map

External area

Access inhibit

Note : External area is not accessible in single-chip mode. When accessing to external areas, select the internal

ROM external bus mode in mode register.

Direct addressing areas

ˇ Half-word data access : 0 to 1FF

ˇ Word-data access : 0 to 3FF

MB91F127/F128

LEGEND OF I/O MAP

Note : Register bit values indicate initial values as shown below :

"1" : Initial value"1"

"0" : Initial value"0"

"X" : Initial value "X"

"-"

: Register does not exist physically in this position.

address

Internal resource

000000

PDR3 [R/W]

XXXXXXXX

PDR2 [R/W]

XXXXXXXX

- - - - - - - -

Port Data Register

Read/write attribute

Initial register value after reset

Register name (the register listed in the first column is at address 4n, the register listed in
the second column is at address 4n

1, - - - )

Leftmost register address (the first column register is on the MSB side of data in word access mode)

MB91F127/F128

I/O MAP

(Continued)

Address

Register

Internal resource

+
+
+
+

000000

PDR3 [R/W]

XXXXXXXX

PDR2 [R/W]

XXXXXXXX

Port data Register

000004

PDR7 [R/W]

- - - - - - - X

PDR6 [R/W]

XXXXXXXX

PDR5 [R/W]

XXXXXXXX

PDR4 [R/W]

XXXXXXXX

000008

PDRA [R/W]

XXXXXXXX

PDR8[R/W]

- - XXXXXX

00000C

000010

PDRE [R/W]

XXXXXXXX

PDRF [R/W]

XXXXXXXX

000014

PDRG [R/W]

XXXXXXXX

PDRJ [R/W]

XXXXXXXX

000018

Reserved

00001C

SSR [R/W]

00001- 00

SIDR [R/W]

XXXXXXXX

SCR [R/W]

00000100

SMR [R/W]

00 - - 0 - 00

UART0

000020

SSR [R/W]

00001- 00

SIDR [R/W]

XXXXXXXX

SCR [R/W]

00000100

SMR [R/W]

00 - - 0 - 00

UART1

000024

SSR [R/W]

00001- 00

SIDR [R/W]

XXXXXXXX

SCR [R/W]

00000100

SMR [R/W]

00 - - 0 - 00

UART2

000028

TMRLR [W]

XXXXXXXX XXXXXXXX

TMR [W]

XXXXXXXX XXXXXXXX

Reload Timer 0

00002C

TMCSR [R/W]

- - - - 0000 00000000

000030

TMRLR [W]

XXXXXXXX XXXXXXXX

TMR [W]

XXXXXXXX XXXXXXXX

Reload Timer 1

000034

TMCSR [R/W]

- - - - 0000 00000000

000038

Reserved

00003C

TMRLR [W]

XXXXXXXX XXXXXXXX

TMR [W]

XXXXXXXX XXXXXXXX

Reload Timer 2

000040

TMCSR [R/W]

- - - - 0000 00000000

000044

IPCP1[R]

XXXXXXXX XXXXXXXX

IPCP0[R]

XXXXXXXX XXXXXXXX

16 bit ICU

000048

IPCP3[R]

XXXXXXXX XXXXXXXX

IPCP2[R]

XXXXXXXX XXXXXXXX

00004C

ICS23[R/W]

00000000

ICS01[R/W]

00000000

000050

ADCR [W]

00101-XX XXXXXXXX

ADCS [R/W]

000000000 00000000

A/D converter

(Serially com-

pared)

MB91F127/F128

(Continued)

Address

Register

Internal resource

+
+
+
+

000054

OCCP1[R/W]

XXXXXXXX XXXXXXXX

OCCP0[R/W]

XXXXXXXX XXXXXXXX

16 bit OCU

000058

OCCP3[R/W]

XXXXXXXX XXXXXXXX

OCCP2[R/W]

XXXXXXXX XXXXXXXX

00005C

Reserved

000060

000064

OCS2, 3[R/W]

XXX00000 0000XX00

OCS0, 1[R/W]

XXX00000 0000XX00

16 bit OCU

000068

Reserved

00006C

TCDT [R/W]

00000000 00000000

TCCS [R/W]

0 - - - - - - - 00000000

Free run timer

000070

Reserved

000074

Reserved

000078

UTM/UTIMR [R/W]

00000000 00000000

UTIMC[R/W]

0 - - 00001

U-Timer0

00007C

UTM/UTIMR [R/W]

00000000 00000000

UTIMC[R/W]

0 - - 00001

U-Timer1

000080

UTM/UTIMR [R/W]

00000000 00000000

UTIMC[R/W]

0 - - 00001

U-Timer2

000084

Reserved

000088

00008C

Reserved

000090

000094

EIRR [R/W]

00000000

ENIR [R/W]

00000000

External interrupt/

NMI

000098

EHVR [R/W]

- - - - 0000

ELVR [R/W]

00000000

MB91F127/F128

(Continued)

Address

Register

Internal resource

+
+
+
+

00009C

Reserved

0000A0

0000A4

0000A8

0000AC

0000B0

0000B4

0000B8

0000BC

0000C0

0000C4

0000C8

0000CC

0000D0

DDRE [W]

00000000

DDRF [W]

00000000

Port direction

0000D4

AIC3[W]

11111111

A/D converter

0000D8

DDRG [W]

00000000

DDRJ [W]
00000000

Port direction reg-

ister

0000DC

GCN1 [R/W]

00110010 00010000

- - - - - - - -

GCN2[R/W]

00000000

PPG ctl

0000E0

PTMR0 [R]

11111111 11111111

PCSR0 [W]

XXXXXXXX XXXXXXXX

PPG0

0000E4

PDUT0 [W]

XXXXXXXX XXXXXXXX

PCNH0[R/W]

0000000 -

PCNL0[R/W]

00000000

0000E8

PTMR1 [R]

11111111 11111111

PCSR1 [W]

XXXXXXXX XXXXXXXX

PPG1

0000EC

PDUT1 [W]

XXXXXXXX XXXXXXXX

PCNH1[R/W]

0000000 -

PCNL1[R/W]

00000000

0000F0

PTMR2 [R]

11111111 11111111

PCSR2 [W]

XXXXXXXX XXXXXXXX

PPG2

0000F4

PDUT2 [W]

XXXXXXXX XXXXXXXX

PCNH2[R/W]

0000000 -

PCNL2[R/W]

00000000

0000F8

PTMR3 [R]

11111111 11111111

PCSR3 [W]

XXXXXXXX XXXXXXXX

PPG3

0000FC

PDUT3 [W]

XXXXXXXX XXXXXXXX

PCNH3[R/W]

0000000 -

PCNL3[R/W]

00000000

MB91F127/F128

(Continued)

Address

Register

Internal resource

+
+
+
+

000100

0001FC

Reserved

000200

DPDP [R/W]

- - - - - - - - - - - - - - - - - - - - - - - - -0000000

DMAC

000204

DACSR [R/W]

00000000 00000000 00000000 00000000

000208

DATCR [R/W]

- - - - - - - - - - XX0000 - - XX0000 - - XX0000

00020C

000210

0002FC

Reserved

000300

0003EC

Reserved

0003F0

BSD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit search module

0003F4

BSD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8

BSDC [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FC

BSRR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

MB91F127/F128

(Continued)

Address

Register

Internal resource

+
+
+
+

000400

ICR00 [R/W]

- - -11111

ICR01[R/W]

- - -11111

ICR02[R/W]

- - -11111

ICR03[R/W]

- - -11111

Interrupt controller

000404

ICR04[R/W]

- - -11111

ICR05[R/W]

- - -11111

ICR06[R/W]

- - -11111

ICR07[R/W]

- - -11111

000408

ICR08 [R/W]

- - -11111

ICR09[R/W]

- - -11111

ICR10[R/W]

- - -11111

ICR11[R/W]

- - -11111

00040C

ICR12[R/W]

- - -11111

ICR13[R/W]

- - -11111

ICR14[R/W]

- - -11111

ICR15[R/W]

- - -11111

000410

ICR16[R/W]

- - -11111

ICR17[R/W]

- - -11111

ICR18[R/W]

- - -11111

ICR19[R/W]

- - -11111

000414

ICR20[R/W]

- - -11111

ICR21[R/W]

- - -11111

ICR22[R/W]

- - -11111

ICR23[R/W]

- - -11111

000418

ICR24 [R/W]

- - -11111

ICR25[R/W]

- - -11111

ICR26[R/W]

- - -11111

ICR27[R/W]

- - -11111

00041C

ICR28[R/W]

- - -11111

ICR29[R/W]

- - -11111

ICR30[R/W]

- - -11111

ICR31[R/W]

- - -11111

000420

ICR32[R/W]

- - -11111

ICR33[R/W]

- - -11111

ICR34[R/W]

- - -11111

ICR35[R/W]

- - -11111

000424

ICR36[R/W]

- - -11111

ICR37[R/W]

- - -11111

ICR38[R/W]

- - -11111

ICR39[R/W]

- - -11111

000428

ICR40[R/W]

- - -11111

ICR41[R/W]

- - -11111

ICR42[R/W]

- - -11111

ICR43[R/W]

- - -11111

00042C

ICR44[R/W]

- - -11111

ICR45[R/W]

- - -11111

ICR46[R/W]

- - -11111

ICR47[R/W]

- - -11111

000430

DICR [R/W]

- - - - - - - 0

HRCL [R/W]

- - -11111

Delay interrupt

000434

00047C

Reserved

000480

RSRR/WTCR

[R/W]

1XXXX - 00

STCR [R/W]

000111- -

PDDR [R/W]

- - - - 0000

CTBR [W]

XXXXXXXX

Clock controller

block

000484

GCR [R/W]

110011 - 1

WPR [W]

XXXXXXXX

000488

PTCR [R/W]

00 - - 0 - - -

PLL controller

block

00048C

0005FC

Reserved

MB91F127/F128

(Continued)

Note : Do not issue RMW instructions to a register with write-only bit.

Data in "Reserved" or "-" area is indefinite.

Address

Register

Internal resource

+
+
+
+

000600

DDR3 [W]

00000000

DDR2 [W]

00000000

Data direction reg-

ister

000604

DDR7 [W]

- - - - - - - 0

DDR6 [W]

00000000

DDR5 [W]

00000000

DDR4 [W]

00000000

000608

DDRA [W]

-0000000

DDR8 [W]

- - 000000

00060C

ASR1 [W]

00000000 00000001

AMR1 [W]

00000000 00000000

External bus inter-

face

000610

ASR2 [W]

00000000 00000010

AMR2 [W]

00000000 00000000

000614

ASR3 [W]

00000000 00000011

AMR3 [W]

00000000 00000000

000618

ASR4 [W]

00000000 00000100

AMR4 [W]

00000000 00000000

00061C

ASR5 [W]

00000000 00000101

AMR5 [W]

00000000 00000000

000620

AMD0 [R/W]

- - - XX111

AMD1 [R/W]

0 - - 00000

AMD32[R/W]

00000000

AMD4 [R/W]

0 - - 00000

000624

AMD5[R/W]

0 - - 00000

DSCR [W]

00000000

RFCR [R/W]

--XXXXXX 00 - - - 000

000628

EPCR0 [W]

- - 1 - 1100 -1111111

EPCR1 [W]

- - - - - - - 1 11111111

00062C

DMCR4 [R/W]

00000000 0000000-

DMCR5 [R/W]

00000000 0000000-

000630

0007BC

Reserved

0007C0

FSTR [R/W]

000XXXX0

Flash memory

0007C4

0007F8

Reserved

0007FC

LER [W]

- - - - - 000

MODR [W]

XXXXXXXX

Little endian regis-

ter mode register

RMW instructions (RMW : Read modify write)

AND Rj, @Ri

OR Rj, @Ri

EOR Rj, @Ri

ANDH Rj, @Ri

ORH Rj, @Ri

EORH Rj, @Ri

ANDB Rj, @Ri

ORB Rj, @Ri

EORB Rj, @Ri

BANDL #u4, @Ri BORL #u4, @Ri

BEORL #u4, @Ri

BANDH #u4, @Ri BORH #u4, @Ri

BEORH #u4, @Ri

MB91F127/F128

INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS

(Continued)

Interrupt causes

Interrupt number

Interrupt level

TBR default

Address*

Decimal

Hexadecimal

Offset

Reset

3FC

000FFFFC

Reserved by system

3F8

000FFFF8

Reserved by system

3F4

000FFFF4

Reserved by system

3F0

000FFFF0

Reserved by system

3EC

000FFFEC

Reserved by system

3E8

000FFFE8

Reserved by system

3E4

000FFFE4

Reserved by system

3E0

000FFFE0

Reserved by system

3DC

000FFFDC

Reserved by system

3D8

000FFFD8

Reserved by system

3D4

000FFFD4

Reserved by system

3D0

000FFFD0

Reserved by system

3CC

000FFFCC

Reserved by system

3C8

000FFFC8

Undefined instruction exception

3C4

000FFFC4

NMI request

15 (F

)

fixed

3C0

000FFFC0

External interrupt 0

ICR00

3BC

000FFFBC

External interrupt 1

ICR01

3B8

000FFFB8

External interrupt 2

ICR02

3B4

000FFFB4

External interrupt 3

ICR03

3B0

000FFFB0

UART 0 reception complete

ICR04

3AC

000FFFAC

UART 1 reception complete

ICR05

3A8

000FFFA8

UART 2 reception complete

ICR06

3A4

000FFFA4

UART 0 transmission complete

ICR07

3A0

000FFFA0

UART 1 transmission complete

ICR08

39C

000FFF9C

UART 2 transmission complete

ICR09

398

000FFF98

MB91F127/F128

(Continued)

Interrupt causes

Interrupt number

Interrupt level

TBR default

Address*

Decimal

Hexadecimal

Offset

DMAC 0 (end, error)

ICR10

394

000FFF94

DMAC 1 (end, erro)

ICR11

390

000FFF90

DMAC 2 (end, erro)

ICR12

38C

000FFF8C

DMAC 3 (end, erro)

ICR13

388

000FFF88

DMAC 4 (end, erro)

ICR14

384

000FFF84

DMAC 5 (end, erro)

ICR15

380

000FFF80

DMAC 6 (end, erro)

ICR16

37C

000FFF7C

DMAC 7 (end, erro)

ICR17

378

000FFF78

A/D (sequential type)

ICR18

374

000FFF74

Reload timer 0

ICR19

370

000FFF70

Reload timer 1

ICR20

36C

000FFF6C

Reload timer 2

ICR21

368

000FFF68

External interrupt 4

ICR22

364

000FFF64

External interrupt 5

ICR23

360

000FFF60

Reserved by system

ICR24

35C

000FFF5C

Reserved by system

ICR25

358

000FFF58

U-TIMER 0

ICR26

354

000FFF54

U-TIMER 1

ICR27

350

000FFF50

U-TIMER 2

ICR28

34C

000FFF4C

FLASH memory

ICR29

348

000FFF48

Reserved by system

ICR30

344

000FFF44

Reserved by system

ICR31

340

000FFF40

PPG0

ICR32

33C

000FFF3C

PPG1

ICR33

338

000FFF38

PPG2

ICR34

334

000FFF34

PPG3

ICR35

330

000FFF30

ICU0 (capture)

ICR36

32C

000FFF2C

ICU1 (capture)

ICR37

328

000FFF28

ICU2 (capture)

ICR38

324

000FFF24

ICU3 (capture)

ICR39

320

000FFF20

MB91F127/F128

(Continued)

*1 : ICR specifies interrupt levels for interrupt requests, using the registers in interrupt controller.

ICR is provided for each interrupt request.

*2 : TBR is a register that indicates a head address of the vector table for EIT.

An address that is found by adding offset values defined by TBR and EIT cause, is a vector address.

*3 : If REALOS/FR is used, 0x40 and 0x41 interrupts are used for system code.

Information : An 1 Kbyte area starting with an address indicated by TBR is the vector area for EIT. Size of the area
for one vector is 4 byte. Relation between a vector number and a vector address is as follows:

Interrupt causes

Interrupt number

Interrupt level

TBR default

Address*

Decimal

Hexadecimal

Offset

OCU0 (match)

ICR40

31C

000FFF1C

OCU1 (match)

ICR41

318

000FFF18

OCU2 (match)

ICR42

314

000FFF14

OCU3 (match)

ICR43

310

000FFF10

Reserved by system

ICR44

30C

000FFF0C

16 bit free-run timer

ICR45

308

000FFF08

Reserved by system

ICR46

304

000FFF04

Delay interrupt cause bit

ICR47

300

000FFF00

Reserved by system
(used by REALOS)

2FC

000FFEFC

Reserved by system
(used by REALOS)

2F8

000FFEF8

Used by INT

66
to

255

42
to

2F4

000

000FFEF4

000FFC00

vctadr

TBR

vctofs

TBR

( 3FC

vct)

Vctadr

Vector address, vctofs: Vector offset, vct: Vector number

MB91F127/F128

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

0 V)

*1 : Care must be taken that AV

, AVRH do not exceed V

+ 0.3 V. Also, care must be taken that AVRH do not

exceed AV

*2 : Maximum output current defines a peak value of a specific terminal.

*3 : Average output current defines a mean value of current flow within a period of 100 ms in a specific terminal.

*4 : Average total output current defines a mean value of current flow within a period of 100 ms in all terminals.

*5 :

Aplicable to pins : D16 to D31, A00 to A24, RDY, BGRNT, BRQ, RD, WR0, WR1, CS0 to CS5, CLK, OCPA0

to OCPA3, OC0 to OC3, ALE, INT0 to INT5, SI0, SI2, SO0, SO2, TCI0, SC2

Use within recommended operating conditions.

Use at DC voltage (current) .

The

B signal should always be applied with a limiting resistance placed between the

B signal and the

microcontroller.

(Continued)

Parameter

Symbol

Rating

Unit

Remarks

Min

Max

Power supply voltage

0.3

4.0

Analog supply voltage

0.3

4.0

Analog reference voltage

AVRH

0.3

4.0

Input voltage

0.3

Analog input voltage

0.3

VCC

0.3

Output voltage

0.3

Maximum clamp current

CLAMP

2.0

Total maximum clamp current

CLAMP

"L" level maximum output current

"L" level average output current

OLAV

"L" level maximum total output cur-
rent

100

"L" level average total output cur-
rent

OLAV

"H" level maximum output current

"H" level average output current

OHAV

"H" level maximum total output cur-
rent

"H" level average total output cur-
rent

OHAV

Power consumption

500

Operating temperature

Storage temperature

Tstg

150

MB91F127/F128

(Continued)

The value of the limiting resistance should be set so that when the signal is applied the input current to the

microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods.

Note that when the microcontroller drive current is low, such as in the power saving modes, the

B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.

Note that if a

B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is

provided from the pins, so that incomplete operation may result.

Note that if the

B input is applied during power-on, the power suplly is provided from the pins and the resulting

supply voltage may not be sufficient to operate the power-on reset.

Care must be taken not to leave the input pin open.

Sample recommended circuits

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Input/Output equivalent circuits

P-ch

N-ch

B input (0 V to 16 V)

Limiting

resistance

Protective diode

MB91F127/F128

Recommended Operating Conditions

0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

Parameter

Symbol

Value

Unit

Remarks

Min

Max

Power supply

3.0

3.6

Normal operation

2.0

3.6

Retain RAM data
under "stop" condition

Analog supply voltage

0.3

3.6

Analog reference voltage

AVRH

Operating temperature

MB91F127/F128

DC Characteristics

(AV

3.3 V

0.3 V, AV

0 V, T

C to

* : Refer to "

INPUT/OUTPUT CIRCUIT TYPE".

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Typ

Max

"H" level input
voltage

IHS

Hysteresis
input terminal

0.8

0.3

"L" level input
voltage

ILS

Hysteresis
input terminal

0.3

0.2

"H" level output
voltage

Port2 to PortJ

3.3 V

4.0 mA

0.5

"L" level output
voltage

Port2 to PortJ

3.3 V

4.0 mA

0.4

Input leak
current

Port2 to PortJ

3.6 V

Power supply
current

VCC

25 MHz
V

3.3 V

100

25 MHz
V

3.3 V

120

FLASH
writing

CCS

25 MHz
V

3.3 V

Sleeping

CCH

3.3 V

150

Stopping

Input capacity

Other than
AVCC, AVSS,
AVRH, VCC,
VSS

MB91F127/F128

AC Characteristics

(1) Clock Timing Ratings

3.3 V

0.3 V, AV

0 V, T

C to

*1 : Although PLL allows selection among x1 and x2 multiplication modes, the selection is limited by oscillation

frequency as follows:

Specifying "x2 multiplication" is not allowed if oscillation frequency exceeds 12.5 MHz.

*2 : Frequency regulation indicates a maximum fluctuation from a specified center frequency under locked frequency

multiplication.

Parameter

Symbol

Condition

Value

Unit

Remarks

Min

Max

Clock frequency
(High speed, automatic oscil-
lation)

MHz

Self oscillation allowable
range

Clock frequency
(High speed, PLL used)

MHz

PLL-use allowable area for
self oscillation and external
clock input

Clock frequency
(High speed, 1/2 division in-
put)

MHz

External clock input
allowable range

Clock cycle time

100

Frequency regulation
(when locked)

Input clock pulse width

, P

9.5

Input clock rise and fall time

)

Internal operation
clock frequency

CPU
system

0.625 *

MHz

Peripheral
system

CPP

0.625 *

MHz

Internal operation
clock cycle time

CPU
system

1600 *

Peripheral
system

LCPP

1600 *

100 (%)

MB91F127/F128

(2) Clock Output Timing

3.3 V

0.3 V, AV

0 V, T

C to

*1 : t

CYC

is a frequency of 1 clock cycle indicating gear cycle.

*2 : The values indicate specifications where x1 gear cycle is used.

If gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n.

Min : (1

CYC

Max : (1

CYC

*3 : The values indicate specifications where x1 gear cycle is used.

If gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n.

Min : n

CYC

Max : n

CYC

Clock output timing

(3) Reset Input Ratings

3.3 V

0.3 V, AV

0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Cycle time

CYC

CLK

CHCL

CLK

CYC

10 1

CYC

CLK

CLCH

CLK

CYC

10 1

CYC

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Reset input time

RSTL

RST

CLK

CYC

LCH

CHCL

RST

0.2 V

RSTL

MB91F127/F128

(4) Power-on Reset

3.3 V

0.3 V, V

0 V, T

C to

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min

Max

Power supply rise
time

VCC

3.3 V

0.2 V

before turning on
power

Power supply shut
off time

OFF

VCC

Oscillation stabiliz-
ing wait time

OSC

100

0.2 V

0.9 V

VCC

VSS

2.0 V

3.3 V

VCC

RST

VCC

OFF

OSC

RSTL

A sudden change of supply voltage may activate the power-on reset function. It is recommended that
power voltage should be changed smoothly with less fluctuation of voltages.

Retaining RAM data

The rising slope is recommended
to be less than 50 mV

ms.

Be sure to turn on the power while keeping
RST terminal at L level first. When the power
becomes V

level, rise the voltage to H level

after a period of t

RSTL

MB91F127/F128

(5) Normal Bus Access Read/Write Operation

3.3 V

0.3 V, V

0 V, T

C to

*1 : If the bus is expanded by automatic wait insertion or RDY input, add time (tcyc

the number of expanded

cycles) to the rated value.

*2 : The ratings are based on conditions with "gear cycle

1". If gear cycle of 1/2, 1/4, or 1/8 is specified, calculate

in the formula below by substituting 1/2, 1/4, or 1/8 into n.
Formula : (2

CYC

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

CS0 to CS5 delay
time

CHCSL

CLK

CS0 to CS5

CS0 to CS5 delay
time

CHCSH

Address delay time

CHAV

CLK

A24 to A00

Data delay time

CHDV

CLK

D31 to D16

RD delay time

CLRL

CLK

RD delay time

CLRH

WR0, 1 delay time

CLWL

CLK

WR0, 1

WR0, 1 delay time

CLWH

Valid address

Valid data input time

AVDV

A24 to A00

D31 to D16

tcyc

*1
*2

Valid data input time

RLDV

D31 to D16

tcyc

Data setup

Time

DSRH

Data hold time

RHDX

MB91F127/F128

(6) Timeshared Bus Access Read/Write Operations

3.3 V

0.3 V, V

0 V, T

C to

* : If the bus is expanded by automatic wait insertion or RDY input, add time (tcyc x the number of expanded cycles)

to the rated value.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

ALE delay time

CLLH2

CLK

ALE

ALE delay time

CLLL2

CS1 delay time

CHCSL2

CLK
CS1

CS1 delay time

CHCSH2

Address delay time

CHAV2

CLK

D31 to D16

Data delay time

CHDV2

RD delay time

CLRL2

CLK

RD delay time

CLRH2

WR0, 1 delay time

CLWL2

CLK

WR0
WR1

WR0, 1 pulse width

CLWH2

Valid data input time

RLDV2

D31 to D16

CYC

Data setup

time

DSRH2

Data hold time

RHDX2

MB91F127/F128

CYC

CLLH2

CHCSL2

CHAV2

CHCSH2

RLDV2

MA1

BA1

RHDX2

CLRH2

CLRL2

CHDV2

CLWL2

CLWH2

CHAV2

DSRH2

CLLL2

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

CLK

ALE

CS1

WR0 - WR1

D31-D16
Multiplex bus
for reading

D31-D16
Multiplex bus
for writing

A15-A08
for
non-multi

Address

Read

Address

Write

MB91F127/F128

(7) Ready Input Timing

3.3 V

0.3 V, AV

0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

RDY setup time
RCLK

RDYS

RDY

CLK

RDY hold time

RDYH

CLK

RDY

CLK

RDY

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

RDYH

RDYS

RDYH

RDYS

CYC

With
waiting

Without
waiting

MB91F127/F128

(8) Hold Timing

3.0 V

0.3 V, AV

0 V, T

C to

Note : More than one cycle is required for BGRNT to change after BRQ is input.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

BGRNT delay time

CHBGL

CLK

BGRNT

BGRNT delay time

CHBGH

Terminal floating

BGRNT

time

XHAL

BGRNT

CYC

BGRNT

Terminal valid time

HAHV

CYC

0.8 V

2.4 V

CHBGL

XHAL

HAHV

CHBGH

CYC

BRQ

BGRNT

CLK

2.4 V

Each pin

High-Z

MB91F127/F128

(9) UART Timing

3.3 V

0.3 V, V

0 V, T

C to

* : t

CYCP

is a cycle time of peripheral system clock.

Internal shift clock mode

External shift clock mode

Parameter

Symbol Pin name

Condition

Value

Unit

Remarks

Min

Max

Serial clock cycle time

SCYC

Internal shift

clock mode

8 t

CYCP

SO delay time

SLOV

Valid SI

IVSH

Valid SI hold time

SHIX

Serial clock "H" pulse width

SHSL

External shift

clock mode

4 t

CYCP

Serial clock "L" pulse width

SLSH

4 t

CYCP

SO delay time

SLOV

Valid SI

IVSH

Valid SI hold time

SHIX

Serial busy time

BUSY

6 t

CYCP

SC, SO delay time

CLZO

SC input mask time

CLSL

3 t

CYCP

SC, SO Hi-z time

CHOZ

SHIX

IVSH

SLOV

SCYC

CHOZ

BUSY

CLSL

IVSH

SHIX

SLOV

SLSH

CLZO

SHSL

MB91F127/F128

(11) A/D Converter Block Electrical Characteristics

3.3 V

0.3 V, AV

0 V, T

C to

Notes :

Relatively, the errors increase as |AVRH| value becomes smaller.

Define an output impedance of external circuit analog input under the following conditions :

Output impedance of external circuit

2 (k

)

If an output impedance of external circuit is exceedingly high, sampling time for analog voltage may run
short.

Parameter

Symbol

Pin name

Value

Unit

Remarks

Min

Typ

Max

Resolution

BIT

Total error

4.0

LSB

Linearity error

3.5

LSB

Differential linearity error

2.0

LSB

Zero transition voltage

AN0 to AN7

AVSS

1.5 LSB

AVSS

0.5 LSB

AVSS

2.5 LSB

Full-scale transition voltage

FST

AN0 to AN7

AVRH

5.5 LSB

AVRH

1.5 LSB

AVRH

0.5 LSB

Conversion time

5.3

Analog input current

AIN

AN0 to AN7

0.1

Analog input voltage

AIN

AN0 to AN7

AVRH

Reference voltage

AVRH

Power supply current

AVCC

3.0

5.0

Reference voltage supply
current

AVRH

100

150

Variation among channels

AN0 to AN7

LSB

MB91F127/F128

A/D Converter Block Electrical Characteristics

Resolution

Analog variations recognized by an A/D converter.

Linearity error

Deviation of actual conversion characteristics from an ideal line, which is across zero-transition point ("00 0000
0000"

"00 0000 0001") and full-scale transition point ("11 1111 1110"

"11 1111 1111")

Differential linearity error

Deviation from ideal value of input voltage, which is required for changing output code by 1 LSB.

Total error

Difference between actual value and ideal value. The error includes zero-transition error, full-scale transition
error, and linearity error.

(Continued)

3FF

3FE

3FD

004

003

002

001

AVRH

0.5 LSB'

{1 LSB' ( N

1 )

0.5 LSB'}

1.5 LSB'

Total error

Actual

characteristics

(Actual mea-

sured value)

Actual
characteristics

Ideal characteristics

Analog input

Digital output

Total error of digital output N

{1 LSB'

0.5 LSB'}

1 LSB'

1 LSB' (Ideal value)

AVRH

1024

[V]

' (Ideal value)

: Transition voltage for digital output to change from (N+1) to N.

0.5 LSB'

[V]

FST

' (Ideal value)

AVRH

1.5 LSB'

[V]

MB91F127/F128

(Continued)

3FF

3FE

3FD

004

003

002

001

AVRH

{1 LSB' ( N

1 )

}

AVRH

Linearity error of digital output N

{1 LSB'

}

1 LSB'

[LSB]

Differential linearity error of digital output N

V (

)

}

1 LSB'

1 LSB

FST

1022

[V]

: Transition voltage for digital output to change from (000)

to (001)

FST

: Transition voltage for digital output to change from (3FE)

to (3FF)

[LSB]

Linearity error

Differential linearity error

Digital output

Actual conversion

characteristics

FST

(Actual
measured

value)

(Actual

measured value)

Actual conversion
characteristics

Ideal characteristics

(Actual measured value)

Analog input

Ideal

characteristics

Actual conversion
characteristics

(Actual mea-

sured value)

(Actual

measured value)

FST

MB91F127/F128

FLASH MEMORY WRITE/ERASE CHARACTERISTICS

Parameter

Condition

Value

Unit

Remarks

Min

Typ

Max

Sector erase time

3.3 V

Not including time for internal
writing before deletion.

Chip erase time

Not including time for internal
writing before deletion.

Half byte (16 bit
width) writing time

3600

Not including system-level over-
head time.

Write/erase cycle

10,000

cycle

Data holding time

100,000

MB91F127/F128

EXAMPLE CHARACTERISTICS

ˇ Power Supply Current

2.7

3.3

3.6

3.9

(V)

CCS

(mA)

fc = 25 MHz

100

-10

2.7

3.3

3.6

3.9

(V)

CCH

(

fc = 25 MHz

2.7

3.3

3.6

3.9

(V)

(mA)

fc = 25 MHz

-1

2.7

3.3

3.6

3.9

(V)

(mA)

fc = 25 MHz

180

160

140

100

2.7

3.3

3.6

3.9

(V)

(

120

fc = 25 MHz

A/D Reference Power Supply Current

vs. Power Supply Voltage

Power Supply Current (stopping)

vs. Power Supply Voltage

A/D Power Supply Current vs.

Power Supply Voltage

Power Supply Current (sleeping)

vs. Power Supply Voltage

Power Supply Current vs.

Power Supply Voltage

MB91F127/F128

PACKAGE DIMENSIONS

100-pin plastic LQFP

(FPT-100P-M05)

*Pins width and pins thickness include plating thickness.

Dimensions in mm (inches)

2000 FUJITSU LIMITED F100007S-3c-5

14.00ą0.10(.551ą.004)SQ

16.00ą0.20(.630ą.008)SQ

100

0.50(.020)

0.20ą0.05

(.008ą.002)

0.08(.003)

0.145ą0.055

(.0057ą.0022)

0.08(.003)

"A"

INDEX

.059

.004

+.008

0.10

+0.20

1.50

(Mounting height)

0°~8°

0.50ą0.20

(.020ą.008)

0.60ą0.15

(.024ą.006)

0.25(.010)

0.10ą0.10

(.004ą.004)

Details of "A" part

(Stand off)

MB91F127/F128

FUJITSU LIMITED

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0201

FUJITSU LIMITED Printed in Japan

Part Number MB91F127

Document Outline