DS07-16314-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-Bit Microcontroller

CMOS

FR60 MB91307 Series

MB91306R/MB91307R

DESCRIPTION

The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety
of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability,
high-speed CPU processing. External bus access is assumed in order to support the expanded address space
accessible by the 32-bit CPU, and a 1K bytes cache memory plus large RAM are provided for high-speed execution
of CPU instructions.

This microcontroller is ideal for built-in applications such as DVD players, navigation systems, high-capability FAX
and printer control that demand high-capability CPU processing power.

The MB91307 series is a FR60 family product based on the FR30/40 family CPU with enhanced bus access for
higher speed operation.

FEATURES

FR CPU

ˇ 32-bit RISC, load/store architecture, 5-stage pipeline
ˇ Operating frequency 66MHz [with PLL: base frequency 16.5 MHz]
ˇ 16-bit fixed length instructions (basic instructions), 1 instruction per cycle
ˇ Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc.
ˇ Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/

store instructions

(Continued)

PACKAGE

120-pin, plastic LQFP

(FPT-120P-M21)

MB91307 Series

ˇ Easier assembler notation: register interlock function
ˇ Built-in multiplier/instruction level support

Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles

ˇ Interrupt (PC, PS removal): 6 cycles, 16 priority levels
ˇ Harvard architecture for simultaneous execution of program access and data access
ˇ CPU hold 4-word queue allows advanced instruction fetch function
ˇ 4G bytes expanded memory space enables linear access
ˇ Instruction compatible with FR30/40 family

Bus Interface

ˇ Operating frequency: Max 33 MHz
ˇ 8- or 16-bit data output
ˇ Built-in pre-fetch buffer
ˇ Unused data/address pins can be used as general-0purpose input/output ports
ˇ Fully independent 8-area chip select outputs, can be set in minimum 64K bytes units
ˇ Interface support for many memory types

SRAM, ROM/Flash
Page mode flash ROM, page mode ROM interface
Burst mode flash ROM (select burst length 1, 2, 4, 8)

ˇ Basic bus cycle: 2 cycles
ˇ Programmable by area with automatic wait cycle generation to enable wait insert
ˇ RDY input for external wait cycles
ˇ DMA supports fly-by transfer with independent I/O wait control

Built-in RAM

ˇ 128K bytes (MB91307R), 64K bytes (MB91306R)
ˇ Accepts writing of data and instruction codes, enabling use as instruction RAM

Instruction cache

ˇ 1K bytes capacity
ˇ 2-way set associative
ˇ 4-words (16 bytes) per set
ˇ Lock function enables permanent program storage
ˇ Areas not used for instruction cache can be used for RAM

DMAC (DMA controller)

ˇ 5-channel (3-channel external-to-external)
ˇ 3 transfer sources (external pin, internal peripheral, software)
ˇ Addressing mode with 32-bit full address indication (increment, decrement, fixed)
ˇ Transfer mode (demand transfer / burst transfer / step transfer / block transfer)
ˇ Fly-by transfer support (3 channels between external I/O and external memory)
ˇ Transfer data size selection 8/16/32-bit

Bit search module (using REALOS)

ˇ Searches words from MSB for first bit position of a 1/0 change

Reload timer (includes 1 channel for REALOS)

ˇ 16-bit timer: 3 channels
ˇ Internal clock multiplier choice of x2, x8, x32

(Continued)

MB91307 Series

(Continued)

UART

ˇ Full duplex double buffer
ˇ 3-channel
ˇ Parity/no parity selection
ˇ Asynchronous (start-stop synchronized), CLK-synchronized communications selection
ˇ Built-in exclusive baud rate timer
ˇ External clock can be used as transfer clock
ˇ Variety of error detection functions (parity, frame, overrun)

C* interface

Interrupt controller

ˇ Total of 9 external interrupts: 1 non-maskable interrupt pin (NMI) and 8 normal interrupt pins INT7-INT0
ˇ Interrupt from internal peripheral devices
ˇ Programmable priority settings (16 levels) enabled, except for non-maskable interrupt
ˇ Can be used for wake-up from stop mode

A/D converter

ˇ 10-bit resolution, 4-channel
ˇ Sequential comparator type, conversion time approx. 5.4

ˇ Conversion modes: single conversion mode, continuous conversion mode
ˇ Startup source: software / external trigger / timer output signal

Other interval timers

ˇ 16-bit timer with 3 channels (U-timer)
ˇ Watchdog timer

I/O port

ˇ Maximum 69 ports

Other features

ˇ Built-in oscillator circuit for clock source, PLL multiplier selection enabled
ˇ INIT reset pin
ˇ Also included: watchdog timer reset, software reset
ˇ Power-saving modes: stop mode, sleep mode supported
ˇ Gear functions
ˇ Built-in time base timer
ˇ Packages: LQFP-120 (FPT-120P-M21) : MB91306R, MB91307R

: MB91V307R (Evaluation products)

ˇ CMOS technology

: 0.25

m : MB91V307R, 0.18

m : MB91306R, MB91307R

ˇ Supply voltage

: MB91V307R : 3.3 V

0.3 V (built-in regulator 3.3 V

2.5 V)

: MB91306R, MB91307R : 3.3 V

0.3 V, 1.8V

0.15 V dual power supplies

* : Purchase of Fujitsu I

C components conveys a license under the Philips I

C Patent rights to use, these components

in an I

C system provided that the system conforms to the I

C Standard Specification as defined by Philips.

ˇ Master/slave sending and receiving

ˇ Arbitration function

ˇ Clock synchronization function

ˇ Slave address/general call address detection function

ˇ Transfer direction detection function

ˇ Start condition repeat generator and detection function

ˇ Bus error detection function

ˇ 10-bit/7-bit slave address

ˇ Operates in standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)

MB91307 Series

PIN ASSIGNMENT

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

PA3/CS3
PA4/CS4
PA5/CS5

CCI

PA6/CS6
PA7/CS7

P80/RDY

P81/BGRNT

P82/BRQ

UUB/WR0

P85/ULB/WR1

NMI

CCI

INIT

P90/SYSCLK

P91

P92/MCLK

P93

P94/LBA/AS

P95/BAA

P96

P97/WE

P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21

PI5/SC1
PI4/SO1
PI3/SI1
PI2/SC0
PI1/SO0
PI0/SI0
V

PJ7/INT7/ATG
PJ6/INT6/TIN2
PJ5/INT5/TIN1
PJ4/INT4/TIN0
PJ3/INT3
PJ2/INT2
PJ1/INT1
PJ0/INT0
AN3
AN2
AN1
AN0
AV

/AVRL

AVRH
AV

A24/P70
A23/P67
A22/P66
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

P26/D22

P27/D23

D24

D25

D26

D27

D28

D29

D30

D31

A00

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

P60/A16

A2/CS2

A1/CS1

A0/CS0

PB7/IORD

PB6/IO

PB5/DEOP1/DSTP

PB4/D

CK1

PB3/DREQ1

PB2/DEOP0/DSTP

PB1/D

CK0

PB0/DREQ0

MD2

MD1

MD0

PG2/DEOP2/DSTP

PG1/D

CK2

PG0/DREQ2

PH7/SCL

PH6/SD

PH5/T

PH4/T

PH3/T

PH2/SC2

PH1/SO2

PH0/SI2

* : "L" level output after initialization and reset

FPT-120P-M21

MB91307 Series

PIN DESCRIPTIONS

(Continued)

Pin no.

Pin name

I/O

circuit type

Description

85 to 92

D16 to D23

External data bus bit 16 to bit 23
Valid only in external bus 16-bit mode.

P20 to P27

These pins can be used as ports in external bus 8-bit mode

93 to 100

D24 to D31

External data bus bit 24 to bit 31

102 to 109

A00 to A07

External address output bit0 to bit7

111 to 118

A08 to A15

External address output bit8 to bit15

120, 1 to 7

A16 to A23

External address output bit16 to bit23

P60 to P67

These pins can be used as ports according to setting

A24

External data bus output bit24

P70

This pin can be used as a port according to setting

Power supply pin. Analog power supply for A/D converter

AVRH

A/D converter reference voltage supply

/AVRL

Power supply pin. Analog power supply for A/D converter

12 to 15

AN0 to AN3

A/D converter reference voltage supply. Analog input pin.

16 to 19

INT0 to INT3

External interrupt input. When the corresponding external interrupt is en-
abled, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally

PJ0 to PJ3

General purpose input/output port

20 to 22

TIN0 to TIN2

Reload timer input. When the corresponding timer input is enabled, this
input is in use at all times, so that output from other functions must be
stopped unless used intentionally.

INT4 to INT6

External interrupt input. When the corresponding external interrupt is en-
abled, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.

PJ4 to PJ6

General purpose input/output port

ATG

A/D converter external trigger input. When selected as an A/D start
source, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.

INT7

External interrupt input. When the corresponding external interrupt is en-
abled, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.

PJ7

General purpose input/output port

SI0

UART0 data input. When the UART0 channel is in input operation, this
input is in use at all times, so that output from other functions must be
stopped unless used intentionally.

PI0

General purpose input/output port.

SO0

UART0 data output. This function is valid when the UART0 data output
function setting is disabled.

PI1

General purpose input/output port. This function is valid when the
UART0 data output function setting is disabled.

MB91307 Series

(Continued)

Pin no.

Pin name

I/O

circuit type

Description

SC0

UART0 clock output. The clock output is valid when the UART0 clock
output function setting is enabled.

PI2

General purpose input/output port. This function is valid when the
UART0 clock output function is disabled.

SI1

UART1 data input. When UART1 is set for input operation, this input is
in use at all times, so that output from other functions must be stopped
unless used intentionally.

PI3

General purpose input/output port.

SO1

UART1 data output. This function is enabled when the UART1 data out-
put function setting is enabled.

PI4

General purpose input/output port. This function is valid when the
UART1 data output function setting is disabled.

SC1

UART1 clock input/output. The clock output is enabled when the UART1
clock output function setting is enabled.

PI5

General purpose input/output port. This function is valid when the
UART1 clock output function setting is disabled.

SI2

UART2 data input. When UART2 is set for input operation, this input is
in use at all times, so that output from other functions must be stopped
unless used intentionally.

PH0

General purpose input/output port.

SO2

UART2 data output. This function is enabled when the UART2 data out-
put function setting is enabled.

PH1

General purpose input/output port This function is enabled when the
UART2 data output function setting is disabled.

SC2

UART2 clock input/output. The clock output is enabled when the UART2
clock output function setting is enabled.

PH2

General purpose input/output port This function is enabled when the
UART2 clock output function is disabled.

TOT0

Timer output port. This function is valid when the timer output setting is
enabled.

PH3

General purpose input/output port.This pin outputs an "L" level signal at
reset.

TOT1

Timer output port. This function is valid when the timer output setting is
enabled.

PH4

General purpose input/output port.This pin outputs an "L" level signal at
reset.

TOT2

Timer output port. This function is valid when the timer output is enabled.

PH5

General purpose input/output port.

MB91307 Series

(Continued)

Pin no.

Pin name

I/O

circuit type

Description

SDA

C bus input/output port. This function is valid when I

C operation is en-

abled. When the I

C bus is in use, the port output must be set to Hi-Z

level. When the I

C bus is in use, this is an open drain pin.

PH6

General purpose input/output port.

SCL

C bus input/output port. This function is valid when I

C operation is en-

abled. When the I

C bus is in use, the port output must be set to Hi-Z

level. When the I

C bus is in use, this is an open drain pin.

PH7

General purpose input/output port.

DREQ2

DMA external transfer request input. When selected as a DMA startup
source, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.

PG0

General purpose input/output port.

DACK2

DMA external transfer request acknowledge output. This function is valid
when the DMA transfer request acknowledge output setting is enabled.

PG1

General purpose input/output port. This function is valid when the DMA
transfer request acknowledge output setting is enabled.

DEOP2

DMA external transfer end output. This function is valid when the DMA
external transfer end output setting is enabled.

DSTP2

DMA external transfer stop input. This function is valid when the DMA ex-
ternal transfer stop input setting is enabled.

PG2

General purpose input/output port. This function is valid when the DMA
external transfer end output selection and the DMA external transfer stop
input selection are disabled.

43 to 45

MD2 to MD0

Mode pins 2 to 0. The setting of these two pins determines the basic
operating mode. They should be connected to V

or V

DREQ0

DMA external transfer request input. When selected as a DMA startup
source, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.

PB0

General purpose input/output port.

DACK0

DMA external transfer request acknowledge output. This function is valid
when the DMA transfer request acknowledge output setting is enabled.

PB1

General purpose input/output port. This function is enabled when the
DMA transfer request acknowledge output setting is disabled.

DEOP0

DMA external transfer end output. This function is valid when the DMA
external transfer end output setting is enabled.

DSTP0

DMA external transfer stop input. This function is valid when the DMA ex-
ternal transfer stop input setting is enabled.

PB2

General purpose input/output port. This function is valid when the DMA
external transfer end output selection and the DMA external transfer stop
input selection are disabled.

MB91307 Series

(Continued)

Pin no.

Pin name

I/O

circuit type

Description

DREQ1

DMA external transfer request input. When selected as a DMA startup
source, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.

PB3

General purpose input/output port.

DACK1

DMA external transfer request acknowledge output. This function is valid
when the DMA transfer request acknowledge output setting is enabled.

PB4

General purpose input/output port. This function is enabled when the
DNA transfer request acknowledge output setting is disabled.

DEOP1

DMA external transfer end output. This function is valid when the DMA
external transfer end output setting is enabled.

DSTP1

DMA external transfer stop input. This function is valid when the DMA ex-
ternal transfer stop input setting is enabled.

PB5

General purpose input/output port. This function is valid when the DMA
external transfer end output selection and the DMA external transfer stop
input selection are disabled.

Clock (oscillator) output

Clock (oscillator) input

IOWR

Write strobe output for DMA fly-by transfer. This function is valid when
the DMA fly-by transfer write strobe output setting is enabled.

PB6

General purpose input/output port. This function is valid when the DMA
fly-by transfer write strobe output setting is disabled.

IORD

Read strobe output for DMA fly-by transfer. This function is valid when
the DMA fly-by transfer read strobe output setting is enabled.

PB7

General purpose input/output port. This function is valid when the DMA
fly-by transfer read strobe output setting is disabled.

CS0

Chip select output. This function is valid when the chip select 0 output
setting is enabled.

PA1

General purpose input/output port. This function is valid when the chip
select 0 output setting is disabled.

CS1

Chip select output. This function is valid when the chip select 1 output
setting is enabled.

PA1

General purpose input/output port. This function is valid when the chip
select 1 output setting is disabled.

CS2

Chip select output. This function is valid when the chip select 2 output
setting is enabled.

PA2

General purpose input/output port. This function is valid when the chip
select 2 output setting is disabled.

CS3

Chip select output. This function is valid when the chip select 3 output
setting is enabled.

PA3

General purpose input/output port. This function is valid when the chip
select 3 output setting is disabled.

MB91307 Series

(Continued)

Pin no.

Pin name

I/O

circuit type

Description

CS4

Chip select output. This function is valid when the chip select 4 output set-
ting is enabled.

PA4

General purpose input/output port. This function is valid when the chip se-
lect 4 output setting is disabled.

CS5

Chip select output. This function is valid when the chip select 5 output set-
ting is enabled.

PA5

General purpose input/output port. This function is valid when the chip se-
lect 5 output setting is disabled.

CCI

Internal Power supply pin (1.8 V power supply) .

CS6

Chip select output. This function is valid when the chip select 6 output set-
ting is enabled.

PA6

General purpose input/output port. This function is valid when the chip
select 6 output setting is disabled.

CS7

Chip select output. This function is valid when the chip select 7 output set-
ting is enabled.

PA7

General purpose input/output port. This function is valid when the chip
select 7 output setting is disabled.

RDY

External ready signal input. This function is valid when the external ready
input setting is enabled.

P80

General purpose input/output port. This function is valid when the exter-
nal ready input setting is disabled.

BGRNT

External bus open acknowledge output. This pin outputs an L level signal
when the external bus is open. This function is valid when the output set-
ting is enabled.

P81

General purpose input/output port. This function is valid when the output
setting is disabled.

BRQ

External bus open request input. The input value is "1" when the external
bus is open. This function is valid when the input setting is enabled.

P82

General purpose input/output port. This function is valid when the input
setting is disabled.

External bus read strobe output.

WR0

UUB

External bus write strobe output.
Upper side of the 16-bit SRAM input/output mask enable signal.
It is valid when the external bus is set to SRAM use. (WE/P97 function as
the write strobe.)

WR1

ULB

External bus write strobe output.
Lower side of the 16-bit SRAM input/output mask enable signal.
It is valid when the external bus is set to SRAM use. (WE/P97 function as
the write strobe.)

P85

General purpose input/output port. This function is valid when the enable
output setting is disabled.

MB91307 Series

(Continued)

Pin no.

Pin name

I/O

circuit type

Description

NMI

request

input

CCI

Internal Power supply pin(1.8 V power supply)

INIT

External reset input

SYSCLK

System clock output. This function is valid when the system clock output
setting is enabled. The clock signal output is at the same frequency as the
external bus operating frequency. Clock output halts in the stop mode or
the hardware standby mode.

P90

General purpose input/output port. This function is enabled when the sys-
tem clock output setting is disabled.

P91

General purpose input/output port. This function is enabled when the
SDRAM clock enable output setting is disabled.

MCLK

Memory clock output. Clock output halts in the sleep mode, the stop mode
or the hardware standby mode.

P92

General purpose input/output port. This function is enabled when the
clock output setting is disabled.

P93

General purpose input/output port. This function is enabled when the
SDRAM clock re-input setting is disabled.

Address strobe output. This function is valid when the address strobe out-
put setting is disabled.

LBA

Burst flash ROM address load output. This function is valid when the ad-
dress load output setting is enabled.

P94

General purpose input/output port. This function is valid when the address
load output and address strobe output settings are disabled.

BAA

Burst flash ROM address advance output. This function is valid when the
address advance output setting is enabled.

P95

General purpose input/output port. This function is valid when the address
advance output and column address strobe output settings are disabled.

P96

General purpose input/output port. This function is enabled when the col-
umn address strobe output setting is disabled.

Write strobe output for 16-bit SRAM. This function is enabled when the
write strobe output setting is enabled.

P97

General purpose input/output port. This function is enabled when the write
strobe output setting is prohibited.

A/D converter power supply

AVRH

A/D converter power supply

/AVRL

A/D converter power supply (GND)

24, 55,

110

Power supply pins

34, 52,

75, 101

Power supply pins (GND)

MB91307 Series

HANDLING DEVICES

MB91307 Series

Preventing Latchup

When CMOS integrated circuit devices are subjected to applied voltages higher than V

at input and output

pins (other than medium- and high-withstand voltage pins), or to voltages lower than V

, as well as when voltages

in excess of rated levels are applied between V

and V

, a phenomenon known as latchup can occur. When

a latchup condition occurs, supply current can increase dramatically and may destroy semiconductor elements.
In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.

Treatment of unused pins

Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or
pull-down resistor.

About power supply pins

In products with multiple V

or V

pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V

and V

pins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 mF between V

and V

near

this device.

Notes on Power-ON/shut-down

Cautions to take when turning on/off V

CCI

(1.8-V internal power supply) and V

(3.3-V external-pin power

supply)

Do not apply V

(external) alone continuously (for over an indication of one minute) with V

CCI

(internal) discon-

nected not to cause a reliability problem with the LSI.

When V

(external) returns from the OFF state to the ON state, the circuit may fail to hold its internal state, for

example, due to power supply noise.

Precautions for use of stop mode

The built-in regulator in this device stops operating when the device is in stop mode. In such cases as when
increased leak current (I

CCH

) in stop mode, or abnormal operation or power fluctuation due to noise while in

operating mode cause the regulator to stop, the internal 2.5 V power supply can ball below the voltage at which
operation is assured. Therefore it is necessary when using the internal regulator and stop mode to assure that
the external power supply does not fall below 3.3 V. And even if this should occur, the internal regulator can be
set to restart when a reset is applied. (In this case the oscillator stabilization wait period should also be set to
"L" level.)

When the power is turned on

CCI

(internal)

(external)

Signal

When the power is turned off

Signal

(external)

CCI

(internal)

MB91307 Series

ˇ Sample use of Stop Mode with 3.3 V power supply

About crystal oscillator circuit

Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that
X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to
the device as possible.

It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane
because stable operation can be expected with such a layout.

Treatment of NC pins

Any pins marked "NC" (not connected) must be left open.

About mode pins (MD0 to MD2)

Mode pins (MD0 to MD2) should be connected directly to V

or V

To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and V

or V

is as short as possible and the connection impedance is low.

Operation at startup

Immediately after a power-on startup, always apply a reset initialization (INIT) at the INIT pin. Also, in order to
assure a wait period for the oscillator circuits to stabilize immediately after startup, be sure that the "L" level input
to the INIT pin continues for the required stabilization wait interval. (The INIT cycle for the INIT pin includes only
the minimum setting for the stabilization wait period.)

Base oscillator input at startup

At power-on startup, always input a clock signal until the oscillator stabilization wait period is ended.

Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.

Precaution on using ports 6 and 7

If one of P60/A15 to P70/A24, which are shared for output of external bus interface addresses, is used as a port,
a grid voltage is applied to the port instantaneously when the status of another address output pin is changed.
Therefore, add resistors or capacitors to those ports to prevent application of the grid voltage.

0.1 F

3.3 V

2.4 k

7.6 k

GND

MB91307 Series

Clock control block

For L-level input to the INIT pin, allow for the regulator settling time or oscillation settling time.

Bit search module

The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only word-
accessible.

Prefetch

When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits).

Byte or halfword access results in wrong data read.

Setting of external bus

The MB91307 series is guaranteed at an external bus frequency of 33 MHz. As the external bus is capable of
supporting 66 MHz for future enhancements, the initial value is the same rate as the base clock (determined by
the PLL setting) . The external bus is set to 66 MHz if you set the base clock to 66 MHz with the external-bus
base clock division setting register (DIVR1) containing the initial value. To change the base clock frequency, set
the external bus frequency not exceeding 33 MHz and set the new base clock frequency.

MCLK and SYSCLK

MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either
depending on each application.

C input/output pin

The SDA and SCL pins of the MB91307 series are pseudo open-drain pins with the P-ch transistor turned off
to prevent the "H" level from being output. As the circuit configuration has a diode added to the V

side, therefore,

the communication voltage must be adjusted to the 3.3-V power supply of this model (pulled up to a voltage of
3.3 V) .

Shared port function switching

To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are
switched depending on external bus settings.

Pull-up control

Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the AC standard.

Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standby
mode.

I/O port access

Byte access only for access to port

Remarks for the external clock operation

When selecting the external clock, active X0 pin generally. Also simultaneously the opposite phase clock to X0
must be supplied to X1 pin. When using the clock along with STOP (oscillation stopped) mode, the X1 pin stops
when "H" is input in STOP mode. To prevent one output from competing against another, in this case, the stop
mode must not be used.

MB91307 Series

Low-power consumption modes

To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the
TBCR, or time-base counter control register) and be sure to use the following sequence:

(LDI

#value_of_standby, R0)

(LDI

#_STCR, R12)

STB

R0, @R12

; Write to standby control register (STCR)

LDUB

@R12, R0

; Read STCR for synchronous standby

LDUB

@R12, R0

; Read STCR again for dummy read

NOP

; NOP x 5 for timing adjustment

NOP
NOP
NOP
NOP

Set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt handler
triggers the microcontroller to return from the standby mode.

If you use the monitor debugger, follow the precautions below:

Do not set a breakpoint within the above array of instructions.
Do not single-step the above array of instructions.

Current at power-on (only for MB91V307R)

About 300 mA of power supply current flows when the power is turned on with INIT set to 0.

Set INIT to 1 to stop the overcurrent flowing. After that, the overcurrent will not flow even if INIT is set to 0.

Watchdog timer

The watchdog timer function of this model monitors that a program delays a reset within a certain period of time
and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once
the watchdog timer function is enabled, therefore, the watchdog timer countinues to operate until a reset takes
place.

An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under
a condition in which the CPU stops program execution.

Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of
control. If this is the case, use the external INIT pin to cause a reset (INIT).

MB91307 series

Using external clock (normal)

Note : Stop mode (oscillation stop mode) cannot be used.

MB91307 Series

Terminal and timing control register (TCR) (0x00000683)

The terminal and timing control register (TCR) is a write-only register. Therefore, do not access TCR with a bit
manipulation instruction.

If you intend to disable sharing of the bus by writing "0" to Bit 7 (BREN bit) of TCR when the bit is "1", be sure
to follow the procedure below. If the procedure is not followed, the device may hang up.

1. Write "0" to Bit 2 (BRQE bit) of the port 8 function register (PFR8).

2. Write "0" to Bit 7 (BREN bit) of TCR.

RD/WR

CS hold extension cycle

Assume that use of the RD/WR

CS hold extension cycle is specified (Bit 0 of AWR is 1) for an

area for which the normal memory/IO access type is set (the TYPE3 to TYPE0 bits of ACR are

0xxx). Even in this case, the hold extension cycle might not be inserted when the operation and

settings are specified in a specific combination.

The hold extension cycle will not be inserted when the following conditions are met:
ˇ Use of the RD/WR

CS hold extension cycle is specified.

(Bit 0 [W00 bit] of AWR is 1.)

ˇ A normal memory/IO access type is set for the area.

(Bits 3 to 0 [TYPE3 to TYPE0 bits] of ACR are 0xxx.)
Note: The MB91307 series allows only this type to be set.

ˇ Disuse of the address

CS delay cycle is specified.

(Bit 2 [W02 bit] of AWR is 0.)

ˇ A setting (recovery enabled) other than 0 cycle is made for the write recovery cycle.

(Bits 5 and 4 [W05 and W04 bits] of AWR are other than 00.)
(Example: First word writing to an external bus 16-bit area)

ˇ If an access is made to write data larger than the bus width to the relevant area under the above conditions,

the RD/WR-CS hold extension cycle is not inserted in any cycle other than the last cycle to write divisions of
the data. Therefore, the hold time becomes insufficient.
Note : This problem does not occur in the read cycle.

To use this function, make either of the following settings:
ˇ Specify the use of the address

CS delay cycle.

(Set 1 for Bit 2 [W02 bit] of AWR.)

ˇ Specify 0 cycle for the write recovery cycle.

(Set 00 for Bits 5 and 4 [W05 and W04 bits] of AWR.)

Signed DIVIDE statement (DIVOS)

When the instruction immediately before the instruction of DIVOS is an instruction by which the memory access
is done, a correct calculation result might not be obtained.

This is generated under the following conditions.

ˇ When the instruction performs memory accesses just before a DIVOS instruction.

Note : Instructions that performs relevant memory accesses (a total of 58 instructions)

ST Ri, @- R15

ST Rs, @- R15

ST PS, @- R15

STB Ri, @Rj

STB Ri, @ (R13, Rj)

DMOVB R13, @dir8

STB Ri, @ (R14, disp8)

LDUB @Rj, Ri

LD @ (R13, Rj), Ri

LDUH @ (R13, Rj), Ri

LDUB @ (R13, Rj), Ri

DMOV @dir10, R13

DMOVH @dir9, R13

DMOVB @dir8, R13

LD @ (R14, disp10), Ri

MB91307 Series

LDUH @ (R14, disp9), Ri

LDUB @ (R14, disp8), Ri

AND Rj, @Ri

ANDH Rj, @Ri

ANDB Rj, @Ri

ORB Rj, @Ri

EORB Rj, @Ri

DMOV @R13+, @dir10

DMOVH @R13+, @dir9

DMOVB @R13+, @dir8

DMOV @dir10, @R13+

DMOVH @dir9, @R13+

DMOVB @dir8, @R13+

DMOV @R15+, @dir10

DMOV @dir10, @- R15

ˇ When full trace mode is specified as trace mode and the DIVOS and DIV1 instructions are not 4-byte aligned.
ˇ Even if the DIVOS and DIV1 instructions are 4-byte aligned, perform a D-bus DMA transfer or specify the full

trace mode as trace mode if a breakpoint is set in the DIV1 instruction.

Avoid this notes as follows:

(1) Do not place an instruction that performs memory access before a DIVOS instruction.
(2) Do not perform a DMA transfer to the D-bus or set full trace mode as trace made when a DIVOS instruction

is specified.

To output the code for avoiding above (1) condition, specify "-@div0s 1" as the compiler option.

SOFTUNE compiler:
ˇ In case of using the SOFTUNE V3: after the SOFTUNE compiler V30L07R07
ˇ In case of using the SOFTUNE V5: after the SOFTUNE compiler V50L04
ˇ In case of using the SOFTUNE V6: after the SOFTUNE compiler V60L01

DMA demand transfer

In sleep mode, demand transfer is executed only once and processing does not go further. During normal
operation, the efficiency of demand transfers may seem to be lowered.

This action occurs only in demand transfers (it does not occur in DREQ edge detection mode or the like).

This is occurred in the following cases:
ˇ A demand transfer by DMAC is performed in sleep mode.

- After a demand transfer is performed once, processing does not go further although DREQ is input

successively.

- A subsequent transfer is started if the device is released from sleep mode and an external bus operation

other than a DMA transfer occurs.

ˇ A demand transfer by DMAC is performed during normal operation.

- After a demand transfer is performed once, a subsequent transfer is not performed until an external bus

access other than a DMA transfer occurs.

- A demand transfer does not progress while there is no external bus access because cache hitting is

performed continuously or internal ROM operation continues.

ˇ A subsequent demand transfer is not started even if an external bus access for prefetching occurs.

Avoid this notes as follows:
ˇ Do not perform a demand transfer by DMAC in sleep mode.
ˇ Do not use sleep mode during a demand transfer by DMAC.

MB91307 Series

RMW instructions using R15

If one of the instructions listed below is executed, the value of SSP or USP* is not used as the value of R15 and,
as a result, an incorrect value is written to memory. Therefore, the compiler does not generate the following
instructions:

AND

R15,@Rj ANDH

R15,@Rj ANDB

R15,@Rj

R15,@Rj ORH

R15,@Rj ORB

R15,@Rj

EOR

R15,@Rj EORH

R15,@Rj EORB

R15,@Rj

XCHB

@Rj,R15

* : R15 is an insubstantial register. If R15 is accessed by a program, SSP or USP is accessed according to the

state of the S flag of the PS register.

Avoid this notes as follows:
ˇ When programming any of the above 10 instructions by an assembler, specify a general-purpose register in

place of R15.

Executing instructions on RAM

ˇ If instruction codes are placed in RAM, they should not be placed in the last 8 address bytes 0005 FFF8

0005 FFFF

. (Instruction code prohibited area)

Notes on the PS register

Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the microcon-
troller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs oper-
ations before and after the EIT as specified in either case.

The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as those in (1) above.

The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the

same value as that in (1) above.

Notes on I-bus Memory

Do not access data in the instruction cache control register or the instruction cache RAM immediately before
the RETI instruction.

MB91307 Series

Unique to the evaluation chip MB91V307R

Simultaneous occurrences of a software break and a user interrupt/NMI

When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause
the following phenomena:

The debugger stops pointing to a location other than the programmed breakpoints.

The halted program is not re-executed correctly.

If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has
been used, avoid setting any break at the relevant location.

Single-stepping the RETI instruction

If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly
after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being
executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant
interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.

Break function

ˇ If the address of a current system stack pointer or an area that includes a stack pointer is specified as an

object address of a hardware break (including an event break), a break occurs after one instruction is executed.
The break occurs although the relevant user program does not include an actual data access instruction. To
avoid this problem, do not set the (word) access to an area that includes the address of a system stack pointer
as a target of a hardware break (including an event break).

ˇ If an instruction that causes a wait is executed between an instruction to read a branch destination address

from memory and a branch instruction, an instruction alignment error occurs at a point where an instruction
alignment error cannot occur originally. Then, an ICE break (CPU error break) occurs, and execution of
instructions stops. Furthermore, even if an instruction break is set for the branch destination address at the
point where the above error occurs, a break might not occur.

Example: LD

@R1,R0 ; read F-bus RAM

@R2,R3 ; read F-bus RAM

CALL

@R0

; An incorrect alignment error may occur or a break might not occur.

To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger
function setup.

To perform the instruction break correctly, do not specify use of a hardware break, but specify use of a software
break in debugger function setup.

Trace mode

If the trace mode for debugging is set to full trace mode, which uses internal FIFO memory as the output buffer,
the current may increase or DMA access to the D-bus may be lost.

This is occurred if:
ˇ A DMA transfer to the D-bus or standby mode occurs in full trace mode.

Use internal trace mode to avoid this notes.

MB91307 Series

Alignment error (emulator debugger)

Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed
between an instruction to read a branch destination address from memory and a branch instruction. Under these
conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur
originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown
break factor or a CPU error break is output.

Furthermore, even if an instruction break is set for the branch destination address at the point where the above
error occurs, a break might not occur.

This problem occurs if the following three types of instructions are executed successively:

(1) LD or DMOV instructions causing a wait (reading a branch destination address)

@Rj,Ri

LDUH @Rj,RI

@(R13,Rj)Ri

LDUH @(R13,Rj),Ri

LDUB @(R13,Rj),Ri

@(R14,disp10),Ri LDUH @(R14,disp9),Ri LDUB @(R14,disp8),Ri

@R15+,Ri LD

@R15+,Rs

@R15+,PS

DMOV @dir10,R13

DMOVH @dir9,R13

DMOVB @dir8,R13

(2) Instructions causing a wait (reading F-bus RAM or external memory)

(3) Branch instructions such as JMP @Ri, JMP: D @Ri, CALL @Ri, CALL: D @Ri, RET, and RET: D

Example:

LD@R1,R0

;read F-bus RAM

LD@R2,R3

;read F-bus RAM

CALL @R0

Avoid this notes as follows:

Furthermore, even if an instruction break is set for the branch destination address at the point where the above
error occurs, a break might not occur.

Avoid this problem as follows:
ˇ To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger

function setup.

ˇ To perform the instruction break correctly, set the break point in an address other than the branch destination

address.

Operand break

A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data
event break to access to the area containing the address of a system stack pointer.

MB91307 Series

CPU AND CONTROL BLOCK

Internal Architecture

The FR series CPU is a high-performance core using RISC architecture with a high-capability instruction set
intended for built-in applications.

Features

ˇ Uses of RISC Architecture

Basic instruction set: 1 instruction to 1 cycle.

ˇ 32-bit architecture

General-purpose registers: 32-bits

16 registers

ˇ 4G bytes linear memory space
ˇ Built-in multipliers

32-bit

32-bit multiplication: 5 cycles

16-bit

16-bit multiplication: 3 cycles

ˇ Enhanced interrupt processing

High-speed response (6 cycles)
Multiple interrupt support
Level masking functions (16 levels)

ˇ Enhanced I/O operating instructions

Memory-to-memory transfer instructions
Bit processing instructions

ˇ High code efficiency

Basic instruction length: 16 bits

ˇ Low power consumption

Sleep mode, stop mode

ˇ Gear function

MB91307 Series

Internal Architecture

The FR series CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction
bus (I-bus) is connected to an on-chip instruction cache. a 32-bit

16-bit bus converter is connected to the

bus (F-bus) to provide an interface between the CPU and peripheral resources. The Harvard

Princeton bus

converter is connected to the both the I-bus and D-bus as an interface between the CPU and bus controller.

FRex CPU

D-bus

Instruction

cache

I address

I data

D address

R-bus

X-bus

D data

F address

F data

RAM

32 bit

16 bit

Bus converter

Princeton

bus

converter

Harvard

Bus controller

Peripherals resource

I-bus

MB91307 Series

Registers

General Purpose Register

Registers R 0 to R 15 are general-purpose registers. These registers can be used as accumulators for compu-
tation operations, or as pointers for memory access.

Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular
applications.

R13: Virtual accumulator

R14: Frame pointer

R15: Stack pointer

Default values at reset are undefined for R0 to R14. The value for R15 is 00000000

(SSP value).

PS (Program Status Register)

This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.

All bits not defined in the diagram are reserved bits with read value "0" at all times. Write access to these bits
is not enabled.

CCR (Condition Code Register)

S : Stack flag, cleared to "0" at reset.

I : Interrupt flag, cleared to "0" at reset.

N : Negative flag, default value at reset undefined.

Z : Zero flag, default value at reset undefined.

V : Overflow flag, default value at reset undefined.

C : Carry flag, default value at reset undefined.

R12

R13

R14

R15

XXXX XXXX

0000 0000

32 bits

[Default values]

Bit position

PS Register

ILM

SCR

CCR

[Default value]

- - 00XXXX

CCR Register

MB91307 Series

SCR (System Condition code Register)

Stepwise division flags

These flags store interim data during execution of stepwise division.

Step trace trap flag

Indicates whether the step trace trap is enabled or disabled.

The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution

of user programs.

ILM(Interrupt Level Mask Register)

This register stores interrupt level mask values, for use in level masking.

The register is initialized to value 15 (01111

) at reset.

PC (Program Counte Registerr)

The program counter indicates the address of the instruction that is executing.

The default value at reset is undefined.

TBR (Table Base Register)

The table base register stores the starting address of the vector table used in EIT processing.

The default value at reset is 000FFC00

[Default value]

XX0

SCR Register

[Default value]

01111

ILM Register

ILM4 ILM3 ILM2 ILM1 ILM0

[Default value]

XXXXXXXX

PC Register

[Default value]

000FFC00

TBR Register

TBR

MB91307 Series

RP (Return Pointer)

The return register stores the address for return from subroutines.

During execution of a CALL instruction, the PC value is transferred to this RP register.

During execution of a RET instruction, the contents of the RP register are transferred to this PC register.

The default value at reset is undefined.

SSP (System Stack Pointer)

The SSP register is the system stack pointer.

When the S flag is "0," this register functions as the R15 register.

The SSP register can also be explicitly specified.

This register is also used as a stack pointer to indicate the stack to which the PS and PC are removed when an
EIT occurs.

The default value at reset is 00000000

USP (User Stack Pointer)

The USP register is the user stack pointer.

When the S flag is "1," this register functions as the R15 register.

The USP register can also be explicitly specified.

The default value at reset is undefined.

This register cannot be used with RETI instructions.

Multiply & Divide registers

The multiply and divide registers are each 32 bits in length.

The default value at reset is undefined.

[Default value]

XXXXXXXX

RP Register

[Default value]

00000000

SSP Register

SSP

[Default value]

XXXXXXXX

USP Register

USP

Multiply & Divide Registers

MDH

MDL

MB91307 Series

SETTING MODE

In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating
mode.

Mode Pins

The three pins MD2, MD1, MD0 are used in mode vector fetch instructions, and also to make settings in test mode.

Mode Register (MODR)

The mode data fetch instruction writes data to the address "0000 07FD

" called the mode data.

The area "0000 07FD

" is the mode register (MODR). When a setting is made to this register, the device will

operate the mode corresponding to that setting.

The mode register can only be set by a reset source at the INIT level. It is not possible to write to this register
from a user program.

Note : No data exists at the FR family mode register address (0000 07FF

[bit7 to bit3] Reserved bits

These bits should always be set to "00000." If set to any other value, stable operation is not assured.

[bit2] ROMA (Internal RAM enable bit)

This bit indicates whether internal RAM is enabled.

[bit1, 0] WTH1, WTH0 (Bus width indicator bits)

In external bus mode, these bits determine the bus width setting.

In external bus mode, the value of these bits sets the BW1, 0 bits in the AMD0 register (CS0 area).

Mode pin

Mode name

Reset vector access area

Remarks

MD2

MD1

MD0

External ROM mode vector

Outside

Bus width is set by mode register.

ROMA

Function

Remarks

External ROM mode

The built-in RAM area functions as external area.

Internal RAM mode

The built-in RAM area is enabled.
The 128K bytes built-in RAM can be used.

WTH1

WTH0

Bus width

8-bit

16-bit

Setting prohibited

Detailed register description >

MODR

Default

Address
0000 07FD

XXXXXXXX

ROMA

WTH1

WTH0

Operating mode setting bits

MB91307 Series

MEMORY SPACE

Memory Space

The FR family has 4G bytes (2

addresses) of logical address space with linear access from the CPU.

Direct Addressing Areas

The following areas of address space are used for I/O operations.

These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.

The direct areas differ according to the size of the data accessed, as follows.

Memory Map

The following diagram illustrates memory space in the FR family.

byte data access

: 000

to 0FF

half word data access : 000

to 1FF

word data access

: 000

to 3FF

0000 0000

0000 0400

0001 0000

0004 0000

0006 0000

0010 0000

FFFF FFFF

0000 0000

0000 0400

0001 0000

0004 0000

0006 0000

0010 0000

I/O

0005 0000

Direct addressing

area

Refer to I/O map

Access

prohibited

Internal RAM

128K bytes

Access

prohibited

External area

Access

prohibited

External area

Access

prohibited

Internal RAM

128K bytes

Access

prohibited

External area

Internal ROM

external bus mode

External bus mode

MB91307R

External area

MB91306R

MB91306R/MB91307R

Internal ROM

external bus mode

MB91307 Series

Use of Built-in RAM

The MB91307R contains 128K bytes of internal RAM, and MB91306R contains 64K bytes of internal RAM. To
enable use of this RAM, the mode register must be set to internal ROM external bus mode (ROMA=1).

Precautions for use of this model

ˇ The reset vector is fixed at 000F FFFC

ˇ For the MB91307R, the 128K bytes RAM area is from 0004 0000

to 0005 FFFF

and for the MB91306R, the

64K bytes RAM area is from 0004 0000

to 0004 FFFF

. The area from 0006 0000

to 000F FFFF

is access

prohibited.

ˇ In order to use RAM the mode register must be set to internal ROM external bus mode.
ˇ In internal ROM external bus mode the built-in RAM area can be used, but the vector area 000F FFXX

is an

internal area and cannot be accessed externally. Please refer to the following explanation.

ˇ When placing instruction code in RAM, nothing should be placed in the last 8 bytes of the area 0005 FFF8

to 0005 FFFF

. (This is an instruction code prohibited area.)

0000 0000

0000 0400

0001 0000

0004 0000

0006 0000

0010 0000

FFFF FFFF

I/O

0005 0000

Direct addressing

area

Refer to I/O map

Access

prohibited

External area

Access

prohibited

External area

After reset release

After mode setting

Internal ROM external bus mode

Internal RAM

128K bytes

Access

prohibited

External area

After mode register setting the vector area is an internal area. Therefore before writing to the mode register
it is necessary to rewrite the TBR register so that the vector area is changed to an external area.

External area

Access

prohibited

Access

prohibited

Internal RAM

64K bytes

: The shaded portion is an internal area.

MB91307 Series

USER PROGRAM INITIALIZATION

The following sequence describes an example using built-in RAM.
For the MB91306R, only the internal RAM area is different but the setting is same.

Hardware Setting Conditions

Immediately After Reset Release

1) Assume that 1M bytes of external ROM is placed beginning at 0010 0000

. Place the program at this location

in the linker. (The following description can apply to other addresses than this one as well.)

2) Connect addresses A19 to A1 (1M bytes) to ROM, other addresses will use CS0.

3) Set the mode pins (MD2, MD1, MD0) to external vectors.

4) Write the reset vector to 001F FFFC

. Likewise write the mode vector to 001F FFF8

After reset release, the CPU will attempt to load a mode vector from 000F FFF8

, a reset vector from 000F

FFFC

, however because this will be an external vector, the CPU will have to go externally. However the

CS0 default value causes 1M bytes of external ROM to be repeated in external space, so that the mode
vector and the reset vector itself will load the contents written at 001F FFF8

and 001F FFFC

in external

ROM.

2) The branch destination is set in the linker to an address in the area 001X XXXX

, so that subsequent pro-

gram execution will be in this area.

CS0

External

ROM

A19 to A1

MB91307 series

CS0

External

ROM

External

ROM

0000 0000

0004 0000

FFFF FFFF

MB91307 series

1M bytes of ROM can
be viewed again on the
address map.

MB91307 Series

User Program Initialization Steps

1) Set the TBR register so that the interrupt table is 001F FFXX

, then perform initialization. This process also

includes a chip select setting, and at the same time the CS0 address is set to be valid at 001X XXXX

. The

CS0 decoding result is the same before and after the setting, so that the CPU can continue to run programs
on external ROM.

2) If necessary, initialize the contents of RAM.

3) Now initialization is complete, and the application program can be executed.

CS0

External

ROM

External

ROM

0000 0000

0004 0000

0010 0000

001F FFFF

FFFF FFFF

MB91307 series

1M bytes of ROM space
matches 1M bytes of the
address map.

MB91307 Series

I/O MAP

This map shows the correlation between areas of memory space and individual registers in peripheral resources.

[How to read the map]

Note: Default register bit values are indicated as follows:

"1" : Default value "1"

"0" : Default value "0"

"X" : Default value "X"

"-"

: No physical register at this location

Address

Register

Block

000000

PDR0 [R/W]

PDR1 [R/W]

PDR2 [R/W]

PDR3 [R/W]

T-unit

Port Data Register

XXXXXXXX

Read/write attributes

...

)

Left most register address
(for word access, the first column of the register contains the MSB end of the data)

MB91307 Series

(Continued)

Address

Register

Block

000000

PDR2 [R/W]

T-unit

Port Data Register

XXXXXXXX

000004

PDR6 [R/W]

PDR7 [R/W]

XXXXXXXX

-------X

000008

PDR8 [R/W]

PDR9 [R/W]

PDRA [R/W]

PDRB [R/W]

--X--XXX

XXXXXXX-

XXXXXXXX

00000C

000010

PDRG [R/W]

PDRH [R/W]

PDRI [R/W]

PDRJ [R/W]

R-bus

Port Data Register

-----XXX

XXX00XXX

---XXXXX

XXXXXXXX

000018

00001C

000020

00003C

Reserved

000040

EIRR [R/W]

ENIR [R/W]

ELVR [R/W]

Ext int

00000000

000044

DICR [R/W]

HRCL [R/W]

DLYI/I-unit

-------0

0--11111

000048

TMRLR [W]

TMR [R]

Reload Timer 0

XXXXXXXX XXXXXXXX

00004C

TMCSR [R/W]

----0000 00000000

000050

TMRLR [W]

TMR [R]

Reload Timer 1

XXXXXXXX XXXXXXXX

000054

TMCSR [R/W]

----0000 00000000

000058

TMRLR [W]

TMR [R]

Reload Timer 2

XXXXXXXX XXXXXXXX

00005C

TMCSR [R/W]

----0000 00000000

000060

SSR [R/W]

SIDR [R/W]

SCR [R/W]

SMR [R/W]

UART0

00001-00

XXXXXXXX

00000100

00--0-0-

000064

UTIM [R] (UTIMR [W] )

DRCL [W]

UTIMC [R/W]

U-TIMER 0

00000000 00000000

--------

0--00001

000068

SSR [R/W]

SIDR [R/W]

SCR [R/W]

SMR [R/W]

UART1

00001-00

XXXXXXXX

00000100

00--0-0-

MB91307 Series

(Continued)

Address

Register

Block

00006C

UTIM [R] (UTIMR [W] )

DRCL [W]

UTIMC [R/W]

U-TIMER 1

00000000 00000000

--------

0--00001

000070

SSR [R/W]

SIDR [R/W]

SCR [R/W]

SMR [R/W]

UART2

00001-00

XXXXXXXX

00000100

00--0-0-

000074

UTIM [R] (UTIMR [W] )

DRCL [W]

UTIMC [R/W]

U-TIMER 2

00000000 00000000

--------

0--00001

000078

ADCR

[R]

ADCS

[R/W]

A/D Converter

sequential comparator

------XX XXXXXXXX

00000000 00000000

00007C

Reserved

000080

Reserved

000084

Reserved

000088

Reserved

00008C

Reserved

000090

Reserved

000094

IBCR [R/W]

IBSR [R/W]

ITBA [R/W]

C interface

00000000

------00 00000000

000098

ITMK [R/W]

ISMK [R/W]

ISBA [R/W]

00----11 11111111

01111111

00000000

00009C

IDAR [R/W]

ICCR [R/W]

IDBL [R/W]

00000000

0-011111

-------0

0000A0

Reserved

0000A4

Reserved

0000A8

Reserved

0000AC

Reserved

0000B0

Reserved

MB91307 Series

(Continued)

Address

Register

Block

000200

DMACA0 [R/W]

DMAC

00000000 0000XXXX XXXXXXXX XXXXXXXX

000204

DMACB4 [R/W]

00000000 00000000 00000000 00000000

000208

DMACA1 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

00020C

DMACB4 [R/W]

00000000 00000000 00000000 00000000

000210

DMACA2 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

000214

DMACB4 [R/W]

00000000 00000000 00000000 00000000

000218

DMACA3 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

00021C

DMACB4 [R/W]

00000000 00000000 00000000 00000000

000220

DMACA4 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

000224

DMACB4 [R/W]

00000000 00000000 00000000 00000000

000228

00022C

00023C

Reserved

000240

DMACR [R/W]

DMAC

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

000244

000274

Reserved

000278

Reserved

00027C

Reserved

000280

0002FC

Reserved

MB91307 Series

(Continued)

Address

Register

Block

000300

Reserved

000304

ISIZE [R/W]

Instruction Cache

------00

000308

0003E0

Reserved

0003E4

ICHRC [R/W]

Instruction Cache

0 - 000000

0003E8

0003EC

Reserved

0003F0

BSD0 [W]

Bit Search Module

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F4

BSD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8

BSDC [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FC

BSRR [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000400

DDRG [R/W]

DDRH [R/W]

DDRI [R/W]

DDRJ [R/W]

R-bus

Port Direction Register

----000

00011000

--000000

00000000

000404

000408

00040C

000410

PFRG [R/W]

PFRH [R/W]

PFRI [R/W]

R-bus

Port Function Register

----0000

0000000-

--00-00-

000414

000418

00041C

000420

00043C

Reserved

MB91307 Series

*1: These registers have different default values at reset level. The value shown is the INIT level value.

*2: These registers have different default values at reset level. The value shown is the INIT level value from the INIT

pin.

(Continued)

Address

Register

Block

000440

ICR00 [R/W]

ICR01 [R/W]

ICR02 [R/W]

ICR03 [R/W]

Interrupt Control unit

---11111

000444

ICR04 [R/W]

ICR05 [R/W]

ICR06 [R/W]

ICR07 [R/W]

---11111

000448

ICR08 [R/W]

ICR09 [R/W]

ICR10 [R/W]

ICR11 [R/W]

---11111

00044C

ICR12 [R/W]

ICR13 [R/W]

ICR14 [R/W]

ICR15 [R/W]

---11111

000450

ICR16 [R/W]

ICR17 [R/W]

ICR18 [R/W]

ICR19 [R/W]

Interrupt Control unit

---11111

000454

ICR20 [R/W]

ICR21 [R/W]

ICR22 [R/W]

ICR23 [R/W]

---11111

000458

ICR24 [R/W]

ICR25 [R/W]

ICR26 [R/W]

ICR27 [R/W]

---11111

00045C

ICR28 [R/W]

ICR29 [R/W]

ICR30 [R/W]

ICR31 [R/W]

---11111

000460

ICR32 [R/W]

ICR33 [R/W]

ICR34 [R/W]

ICR35 [R/W]

---11111

000464

ICR36 [R/W]

ICR37 [R/W]

ICR38 [R/W]

ICR39 [R/W]

---11111

000468

ICR40 [R/W]

ICR41 [R/W]

ICR42 [R/W]

ICR43 [R/W]

---11111

00046C

ICR44 [R/W]

ICR45 [R/W]

ICR46 [R/W]

ICR47 [R/W]

---11111

000470

00047C

000480

RSRR [R/W]

STCR [R/W]

TBCR [R/W]

CTBR [W]

Clock Control unit

10000000 *

00110011 *

00XXXX00 *

XXXXXXXX

000484

CLKR [R/W]

WPR [W]

DIVR0 [R/W]

DIVR1 [R/W]

00000000 *

XXXXXXXX

00000011 *

00000000 *

000488

0005FC

Reserved

MB91307 Series

(Continued)

Address

Register

Block

000600

DDR2 [R/W]

T-unit

Port Direction Register

00000000

000604

DDR6 [R/W]

DDR7 [R/W]

00000000

000608

DDR8 [R/W]

DDR9 [R/W]

DDRA [R/W]

DDRB [R/W]

--0--000

00000000

00060C

000610

T-unit

Port Function Register

000614

PFR6 [R/W]

PFR7 [R/W]

11111111

-------1

000618

PFR8 [R/W]

PFR9 [R/W]

PFRA [R/W]

PFRB1 [R/W]

--1--0--

1111111-

0-001101

00000000

00061C

PFRB2 [R/W]

00------

000620

000624

000628

00063F

Reserved

000640

ASR0 [R/W]

ACR0 [R/W]

T-unit

00000000 00000000

1111XX00 00000000

000644

ASR1 [R/W]

ACR1 [R/W]

XXXXXXXX XXXXXXXX

000648

ASR2 [R/W]

ACR2 [R/W]

XXXXXXXX XXXXXXXX

00064C

ASR3 [R/W]

ACR3 [R/W]

XXXXXXXX XXXXXXXX

000650

ASR4 [R/W]

ACR4 [R/W]

XXXXXXXX XXXXXXXX

000654

ASR5 [R/W]

ACR5 [R/W]

XXXXXXXX XXXXXXXX

MB91307 Series

(Continued)

Address

Register

Block

000658

ASR6 [R/W]

ACR6 [R/W]

T-unit

XXXXXXXX XXXXXXXX

00065C

ASR7 [R/W]

ACR7 [R/W]

XXXXXXXX XXXXXXXX

000660

AWR0 [R/W]

AWR1 [R/W]

011111111 11111111

XXXXXXXX XXXXXXXX

000664

AWR2 [R/W]

AWR3 [R/W]

XXXXXXXX XXXXXXXX

000668

AWR4 [R/W]

AWR5 [R/W]

XXXXXXXX XXXXXXXX

00066C

AWR6 [R/W]

AWR7 [R/W]

XXXXXXXX XXXXXXXX

000670

000674

000678

IOWR0 [R/W] IOWR1 [R/W] IOWR2 [R/W]

XXXXXXXX

00067C

000680

CSER [R/W]

CHER [R/W]

TCR [R/W]

000000001

11111111

00000000

000684

0007F8

Reserved

0007FC

000800

000AFC

Reserved

000B00

ESTS0 [R/W] ESTS1 [R/W]

ESTS2 [R]

DSU

X0000000

XXXXXXXX

1XXXXXXX

000B04

ECTL0 [R/W] ECTL1 [R/W]

ECTL2 [W]

ECTL3 [R/W]

0X000000

00000000

000X0000

00X00X11

MB91307 Series

(Continued)

Address

Register

Block

000B08

ECNT0 [W]

ECNT1 [W]

EUSA [W]

EDTC [W]

DSU

XXXXXXXX

XXX00000

0000XXXX

000B0C

EWPT [R]

00000000 00000000

000B10

EDTR0 [W]

EDTR1 [W]

XXXXXXXX XXXXXXXX

000B14

000B1C

000B20

EIA0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B24

EIA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B28

EIA2 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B2C

EIA3 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B30

EIA4 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B34

EIA5 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B38

EIA6 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B3C

EIA7 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B40

EDTA [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B44

EDTM [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B48

EOA0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B4C

EOA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B50

EPCR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

MB91307 Series

(Continued)

Address

Register

Block

000B54

EPSR [R/W]

DSU

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B58

EIAM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B5C

EIAM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B60

EOAM0/EODM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B64

EOAM1/EODM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B68

EOD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B6C

EOD1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B70

000FFC

Reserved

001000

DMASA0 [R/W]

DMAC

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001004

DMADA0 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001008

DMASA1 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

00100C

DMADA1 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001010

DMASA2 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001014

DMADA2 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001018

DMASA3 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

00101C

DMADA3 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001020

DMASA4 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001024

DMADA4 [R/W]

DMAC

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

MB91307 Series

INTERRUPT SOURCES AND INTERRUPT VECTORS

(Continued)

Interrupt source

Interrupt number

Interrupt level

Offset TBR default address

Decimal

Hex

Reset

3FC

000FFFFC

Mode vector

3F8

000FFFF8

System reserved

3F4

000FFFF4

System reserved

3F0

000FFFF0

System reserved

3EC

000FFFEC

System reserved

3E8

000FFFE8

System reserved

3E4

000FFFE4

Coprocessor absent trap

3E0

000FFFE0

Coprocessor error trap

3DC

000FFFDC

INTE instruction

3D8

000FFFD8

Instruction break exception

3D4

000FFFD4

Operand break trap

3D0

000FFFD0

Step trace trap

3CC

000FFFCC

NMI request (tool)

3C8

000FFFC8

Undefined instruction exception

3C4

000FFFC4

NMI requ

15 (F

)

3C0

000FFFC0

External interrupt 0

ICR00

3BC

000FFFBC

External interrupt 1

ICR01

3B8

000FFFB8

External interrupt 2

ICR02

3B4

000FFFB4

External interrupt 3

ICR03

3B0

000FFFB0

External interrupt 4

ICR04

3AC

000FFFAC

External interrupt 5

ICR05

3A8

000FFFA8

External interrupt 6

ICR06

3A4

000FFFA4

External interrupt 7

ICR07

3A0

000FFFA0

Reload timer 0

ICR08

39C

000FFF9C

Reload timer 1

ICR09

398

000FFF98

Reload timer 2

ICR10

394

000FFF94

UART0(RX completed)

ICR11

390

000FFF90

UART1(RX completed)

ICR12

38C

000FFF8C

UART2(RX completed)

ICR13

388

000FFF88

UART0(TX completed)

ICR14

384

000FFF84

UART1(TX completed)

ICR15

380

000FFF80

UART2(TX completed)

ICR16

37C

000FFF7C

DMAC0(end, error)

ICR17

378

000FFF78

MB91307 Series

(Continued)

Interrupt source

Interrupt number

Interrupt level

Offset TBR default address

Decimal

Hex

DMAC1(end, error)

ICR18

374

000FFF74

DMAC2(end, error)

ICR19

370

000FFF70

DMAC3(end, error)

ICR20

36C

000FFF6C

DMAC4(end, error)

ICR21

368

000FFF68

A/D

ICR22

364

000FFF64

ICR23

360

000FFF60

System reserved

ICR24

35C

000FFF5C

System reserved

ICR25

358

000FFF58

System reserved

ICR26

354

000FFF54

System reserved

ICR27

350

000FFF50

U-TIMER0

ICR28

34C

000FFF4C

U-TIMER1

ICR29

348

000FFF48

U-TIMER2

ICR30

344

000FFF44

Time base timer overflow

ICR31

340

000FFF40

System reserved

ICR32

33C

000FFF3C

System reserved

ICR33

338

000FFF38

System reserved

ICR34

334

000FFF34

System reserved

ICR35

330

000FFF30

System reserved

ICR36

32C

000FFF2C

System reserved

ICR37

328

000FFF28

System reserved

ICR38

324

000FFF24

System reserved

ICR39

320

000FFF20

System reserved

ICR40

31C

000FFF1C

System reserved

ICR41

318

000FFF18

System reserved

ICR42

314

000FFF14

System reserved

ICR43

310

000FFF10

System reserved

ICR44

30C

000FFF0C

System reserved

ICR45

308

000FFF08

System reserved

ICR46

304

000FFF04

Delay interrupt source bit

ICR47

300

000FFF00

System reserved (REALOS use)

2FC

000FFEFC

System reserved (REALOS use)

2F8

000FFEF8

System reserved

2F4

000FFEF4

System reserved

2F0

000FFEF0

System reserved

2EC

000FFEEC

MB91307 Series

(Continued)

Interrupt source

Interrupt number

Interrupt level

Offset TBR default address

Decimal

Hex

System reserved

2E8

000FFEE8

System reserved

2E4

000FFEE4

System reserved

2E0

000FFEE0

System reserved

2DC

000FFEDC

System reserved

2D8

000FFED8

System reserved

2D4

000FFED4

System reserved

2D0

000FFED0

System reserved

2CC

000FFECC

System reserved

2C8

000FFEC8

System reserved

2C4

000FFEC4

System reserved

2C0

000FFEC0

Used by INT instructions

255

2BC

000

000FFEBC

000FFC00

MB91307 Series

PERIPHERAL RESOURCES

Interrupt Controller

(1) Overview

The interrupt controller receives and processes arbitration of interrupts.

Hardware Configuration

This module is configured from the following elements.
ˇ ICR register
ˇ Interrupt priority determination circuit
ˇ Interrupt level and interrupt number (vector) generator
ˇ Hold request removal request generator

Principal Functions

This module primarily provides the following functions.
ˇ NMI request / interrupt request detection
ˇ Order of priority determination (according to level and number)
ˇ Notification (to CPU) of interrupt level of source according to determination
ˇ Notification (to CPU) of interrupt number of source according to determination
ˇ Instruction (to CPU) to recover from stop mode when an interrupt other than NMI/interrupt level "11111" is

generated

ˇ Generation of hold request removal requests to the bus master

MB91307 Series

(2) Register List

(Continued)

Address :

bit 7

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

00000440

00000441

00000442

00000443

00000444

00000445

00000446

00000447

00000448

00000449

0000044A

0000044B

0000044C

0000044D

0000044E

0000044F

00000450

00000451

00000452

00000453

00000454

00000455

00000456

00000457

00000458

00000459

0000045A

0000045B

0000045C

0000045D

0000045E

0000045F

R/W

MB91307 Series

(Continued)

Address :

bit 7

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

R/W

MHALTI

LVL4

LVL3

LVL2

LVL1

LVL0

R/W

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

HRCL

00000460

00000461

00000462

00000463

00000464

00000465

00000466

00000467

00000468

00000469

0000046A

0000046B

0000046C

0000046D

0000046E

0000046F

00000045

MB91307 Series

External Interrupt - NMI Control Block

(1) Overview

The External Interrupt-control block controls external interrupt requests input at the NMI and INT0 to INT7 pins.

The request level can be selected from "H," "L," "rising edge," or "falling edge" detection (except for NMI).

(2) Register List

(3) Block Diagram

ˇ External interrupt enable register (ENIR)

ˇ External interrupt source register (EIRR)

ˇ Request level setting register (ELVR)

bit

EN6

EN7

EN5

EN4

EN3

EN2

EN1

EN0

ER6

ER7

ER5

ER4

ER3

ER2

ER1

ER0

LA7

LB7

LB6

LA6

LB5

LA5

LB4

LA4

LA3

LB3

LB2

LA2

LB1

LA1

LB0

LA0

INT0 to INT7
NMI

R-bus

Interrupt

request

Interrupt enable register

Gate

Source F/F

Edge detection circuit

Interrupt source register

Interrupt level setting register

MB91307 Series

16-bit Reload Timer

(1) Overview

The 16-bit timer is configured from a 16-bit down-counter, 16-bit reload register, prescaler for internal count clock
generation, and a control register.

For the input clock signal, a selection of three internal clock signals (machine clock multiplied by 2, 8, or 32) or
external clock is provided.

The output pin (TOUT) produces a toggle output waveform at every underflow in reload mode, and a square
wave indicating counting in progress in one-shot mode.

The input pin (TIN) can be used for event input in external event count mode, and trigger input or gate input in
internal clock mode.

The external event count function can be used in reload mode or as a frequency multiplier in external clock mode.

The MB91306R/MB91307R contain 3 channels (0 to 2) of this timer.

(2) Register List

ˇ Control status register (TMCSR)

ˇ 16-bit timer register (TMR)

ˇ 16-bit reload register (TMRLR)

CSL1

CSL0

MOD2

MOD1

MOD0

OUTL

RELD

INTE

CNTE

TRG

MB91307 Series

U-TIMER (16 bit timer for UART baud rate generation)

(1) Overview

The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set
using the combination of chip operating frequency and U-TIMER reload value.

The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event.

This device features a 3-channel built-in U-TIMER. By connecting two U-TIMER channels used as interval timers
in a cascade connection, it is possible to count intervals up to a maximum of 2

The available case connections are channel 0 to channel 1, and channel 1 to channel 2.

(2) Register List

(3) Block Diagram

UTIMR

UTIM

UTIMC

(W)

(R)

(R/W)

8 7

UTIMR (reload register)

UTIM (timer)

Clock

Load

Underflow

Under flow U-TIMER 1

To UART

control

f.f.

MUX

Channel 0 only

(Peripheral clock)

MB91307 Series

UART

(1) Overview

The UART is an I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission, providing
the following features. This device features a 3-channel built-in UART.

ˇ Full duplex double buffer
ˇ Asynchronous (start-stop synchronized) or CLK synchronized transmission enabled
ˇ Supports multi-processor mode
ˇ Fully programmable baud rate

Built-in timer can be set to any desired baud rate (see U-TIMER description)

ˇ Independent baud rate setting from external clock enabled.
ˇ Error detection functions (parity, framing, overrun)
ˇ Transfer signal NRZ encoded
ˇ DMA transfer start from interrupt enabled
ˇ DMAC interrupt source cleared by write operation to DRCL register.

(2) Register List

ˇ Serial input register/Serial output registe (SIDR/SODR)

ˇ Serial status register (SSR)

ˇ Serial mode register (SMR)

ˇ Serial control register (SCR)

ˇ DRCL register (DRCL)

SIDR (R)/SODR (W)

SMR

SCR

(R/W)

(W)

SSR

DRCL

8 bit

8 7

ORE

FRE

RDRF

TDRE

RIE

TIE

MD0

MD1

CS0

SCKE

PEN

SBL

A/D

REC

RXE

TXE

MB91307 Series

(3) Block Diagram

MD1
MD0

CS0

SCKE
SOE

PEN
P
SBL
CL
A

REC
RXE
TXE

PE
ORE
FRE
RDRF
TDRE

RIE
TIE

R-bus

SIDR

SODR

Control signal

From U-TIMER

External clock
SC

Clock select

circuit

Receiving status

decision circuit

DMA receiving
error signal
(to DMAC)

RX clock

RX control circuit

Start bit detect

circuit

Receiving bit

counter

Receiving parity

counter

Receiving shifter

Receiving

end

TX clock

RX interrupt
(to CPU)

TX interrupt

(to CPU)

TX control circuit

Sent start

circuit

Sending bit

counter

Sending parity

counter

Sending shifter

Sending

start

SMR

Control signal

SCR

SSR

SC (clock)

SI (receiving data)

SO (Sending data)

MB91307 Series

A/D Converter (Sequential comparison type)

(1) Overview

This A/D converter is a module that coverts analog input voltages to digital values, and provides the following
features.

ˇ Minimum conversion time 5.4

s/ch (at machine clock 33 MHz-CKLP)

ˇ Built-in sample & hold circuit
ˇ Resolution 10 bits (8-bit accuracy)
ˇ Analog input: 4 channels by program selection

Single conversion mode: Conversion on 1 select channel
Scan conversion mode: Select continuous multiple channels. Up to 4 channels can be selected by program.
Continuous conversion mode: Continuous conversion on selected channel
Stop conversion mode: 1-channel conversion then pause and wait until the next start is applied

(enables synchronized conversion start)

ˇ DMA transfer start from interrupt enabled
ˇ Start sources can be selected from software, external trigger (falling edge), reload timer (rising edge).

(2) Register List

ˇ Control status register (ADCS)

ˇ Data register (ADCR)

bit

INT

BUSY

INTE

PAUS

STS1

STS0

STRT

MD0

MD1

ANS2

ANS1

ANS0

ANE2

ANE1

ANE0

MB91307 Series

(3) Block Diagram

(4) Precautions for Use:

When the A/D converter is started from an external trigger or internal timer, the ADCS register A/D start source
bits STS1, STS0 are set, and at this time the input values for the external trigger and internal timer should be
set to the inactive side. If these values are set to the active side, abnormal operation may result.

When setting the STS1, STS0 bits, set ATG = "1" input, reload timer (channel 2) = "0" output.

Note : If internal impedance is higher than the specified value, it may not be possible to obtain analog input

value sampling within the specified sampling time, so that proper results will not be obtained.

AVRH

R-bus

Input switch

Sample & hold circuit

Channel decoder

Internal voltage

Sequential

Data register (ADCR)

AD control register

ATG (External pin trigger)

Reload timer ch1 (Internal connection)

Timing generator

Prescaler

Clock (CLKP)

MB91307 Series

C Interface

(1) Overview

The I

C interface operates as a master/slave device on the I

C bus at serial I/O ports with IC bus support. The

following features are provided.
ˇ Master/slave sending and receiving
ˇ Arbitration function
ˇ Clock synchronization function
ˇ Slave address/general call address detection function
ˇ Transfer direction detection function
ˇ Start condition repeat generation and detection function
ˇ Bus error detection function
ˇ 10-bit/7-bit master/slave addressing
ˇ Compatible with standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)
ˇ Transfer end interrupt/bus error interrupt generation

(2) Register List

(Continued)

Bus Control Register (IBCR)

Bus Status Register (IBSR)

10-Bit Slave Address Register

Address : 000094

Default value

Address : 000095

Default value

Address : 000096

Default value

Address : 000097

Default value

R/W

BEIE

R/W

BER

SCC

MSS

ACK

GCAA

INTE

INT

RSC

LRB

TRX

AAS

GCA

ADT

R/W

TA9

TA8

R/W

TA6

R/W

TA7

TA5

TA4

TA3

TA2

TA1

TA0

MB91307 Series

(Continued)

ˇ 10-Bit Slave Address Mask Register (ITMK)

ˇ 7-Bit Slave Address Register (ISBA)

ˇ 7-Bit Slave Address Mask Register (ISMK)

ˇ Data Register (IDAR)

ˇ Clock Control Register (ICCR)

ˇ Clock Disable Register (IDBL)

Address : 000098

Default value

Address : 000099

Default value

Address : 00009B

Default value

Address : 00009A

Default value

Address : 00009D

Default value

Address : 00009E

Default value

Address : 00009F

Default value

R/W

RAL

R/W

ENTB

TM9

TM8

R/W

TM6

R/W

TM7

TM5

TM4

TM3

TM2

TM1

TM0

R/W

SA6

SA5

SA4

SA3

SA2

SA1

SA0

R/W

SM6

R/W

ENSB

SM5

SM4

SM3

SM2

SM1

SM0

R/W

TEST

CS4

CS3

CS2

CS1

CS0

R/W

DBL

MB91307 Series

(3) Block Diagram

ICCR

IDBL

DBL

ICCR

IBSR

RSC

LRB

Last Bit

TRX

ADT

IBCR

BER

BEIE

INTE

INT

IBCR

SCC

MSS

ACK

GCAA

IBSR

IDAR

AAS

GCA

ENTB

ISMK

RAL

ITBA

ITMK

ISBA

ISMK

CS4
CS3
CS2
CS1
CS0

2 3 4 5

Sync

First Byte

IRQ

SCL

SDA

R-b

C operation enabled

Clock enabled

Clock multiplier 2

Clock select 2 (1/12)

Bus busy

Repeat start

TX/RX

Start - stop

condition generator

Arbitration lost detector

Interrupt request

Start

Master

ACK OK

GC-ACK OK

Slave

Global call

Slave address

compare

End

Error

Shift clock

edge change

Start - stop

condition detector

Shift clock generator

MB91307 Series

DMAC (DMA Controller)

(1) Overview

This module is used to accomplish DMA (Direct Memory Access) transfer on FR family devices.

DMA transfer controlled by this module increases system performance by enabling high speed transfer of many
types of data without going through the CPU.

Hardware Configuration

This module is principally configured from the following units:
ˇ Five independent DMA channels
ˇ 5 channels independent access control circuit
ˇ 32-bit address registers (reload enabled: 2 per channel)
ˇ 16-bit transfer count registers (reload enabled: 2 per channel)
ˇ 4-bit block count registers (1 per channel)
ˇ External transfer request input pins: DREQ0,DREQ1,DREQ2 (ch0, ch1, ch2 only)
ˇ External transfer request acknowledge output pins: DACK0,DACK1,DACK2 (ch0, ch1, ch2 only)
ˇ DMA output completed pins: DEOP0,DEOP1,DEOP2 (ch0, ch1, ch2 only)
ˇ Fly-by transfer (memory to I/O, memory to memory) (ch0, ch1, ch2 only)
ˇ Two-cycle transfer

Principal Functions

Data transfer using the DMAC module primarily involves the following functions:
ˇ Supports independent data transfer on multiple channels (5 channels)

(1) Order of priority (ch0

ch1

ch2

ch3

ch4)

(2) The order can be reversed between ch0 and ch1.

(3) DMAC startup sources

Input from an external-only pin (edge detection/level detection, ch0, ch1, ch2 only)

Request from a built-in peripheral (shared interrupt request, including external interrupts)

Software request (register write)

(4) Transfer modes

Demand transfer / burst transfer / step transfer / block transfer

Addressing mode 32-bit full address designation (increment/decrement/fixed)

(address increment can be specified up to -255 to +255)

Data type, byte / half-word / word length

Single-shot / reload selection available

MB91307 Series

(2) Register Descriptions

ch0 Control/status register A

ch0 Control/status register B

ch1 Control/status register A

ch1 Control/status register B

ch2 Control/status register A

ch2 Control/status register B

ch3 Control/status register A

ch3 Control/status register B

ch4 Control/status register A

ch4 Control/status register B

Overall control register

ch0 Transfer source address register

ch1 Transfer source address register

ch2 Transfer source address register

ch3 Transfer source address register

ch4 Transfer source address register

(bit)

0000200

0000204

0000208

000020C

0000210

0000214

0000218

000021C

0000220

0000224

0000240

0001000

0001004

0001008

000100C

0001010

0001014

0001018

000101C

0001020

0001024

DMACA0

DMACB0

DMACA1

DMACB1

DMACA2

DMACB2

DMACA3

DMACB3

DMACA4

DMACB4

D M A C R

DMASA0

DMADA0

DMASA1

DMADA1

DMASA2

DMADA2

DMASA3

DMADA3

DMASA4

DMADA4

MB91307 Series

(3) Block Diagram

Read
Write

DDNO

BLK register

DDNO register

DTCR

DSS3 to DSS0

ERIR, EDIR

TYPE, MOD, WS

IRQ4 to
IRQ0

MCLREQ

X-bus

DADM, DASZ7 to DASZ0 DADR

SDAM, SASZ7 to SASZ0 SADR

DMA transfer request to

bus controller

Read/write

control

To bus

controller

Bus control block

Access

address

Address counter

Counter/buffer

ounter/buffer

Selector

Write back

Selector

Buffer

Counter

Selector

Write back

DTC two-stage register

Buffer

Counter

Selector

DMA start

source selection
circuit & request

acceptance

control

Priority

circuit

Status

transition

circuit

DMA controller

DDAD two-stage register

Bus control block

Peripheral start request/stop

input

External pin start request/stop

input

To interrupt controller

Peripheral interrupt clear

DMAC 5-channel Block Diagram

Write back

MB91307 Series

10. External Interface

(1) Overview

The external interface controller controls the interface between the LSI's internal bus and external memory or I/
O devices.

This section describes the functions of the external interface.

(2) Features

ˇ Up to 32 bit-length (4G bytes space) address output.
ˇ Connects directly to many external memory (8 bit/16 bit) devices, allows control of multiple access timings.

Asynchronous SRAM, asynchronous ROM/Flash memory (multiple write strobe type or byte enable type)
Page mode ROM/flash memory (2/4/8 page size enabled)
Burst ROM/Flash memory (MBM29BL160D/161D/162D etc.)
Address/data multiplexed bus (8 bit/16 bit width only)
Synchronous memory* (ASIC built-in memory etc.)

*: Does not connect to synchronous SRAM.

ˇ 8 independent bank (chip select area) settings, each with corresponding chip select output available

Each area size can be set in multiples of 64K bytes (from 64K bytes to 2G bytes per chip select area).
Each area can be set in any desired area of logic address space (boundaries limited by area size).

ˇ The following functions can be independently set for each chip select area.

Chip select area enable/disable (no access to prohibited areas)
Access timing type for each area, etc.
Detailed access timing settings (individual access type settings for wait cycle, etc.)
Data bus width setting (8 bit/16 bit)
Byte ordering endian setting* (big or little).

*: CS0 area available with big endian only.

Write prohibited setting (read-only areas)
Internal cache loading enable/disable settings
Pre-fetch function enable/disable settings
Maximum burst length setting (1,2,4,8)

ˇ Different detailed timing settings for each access timing type

Different settings can be used for each chip select area even for the same access timing type.
Auto wait setting up to 15 cycles (asynchronous SRAM, ROM, Flash, I/O areas)
Bus cycle extension with external RDY input enabled (asynchronous SRAM, ROM, Flash, I/O areas)
First access wait and page wait settings enabled (burst, page mode ROM/FLASH areas)
Different idle, recovery cycles setup delay insertion etc. enabled

ˇ Fly-by transfer with DMA enabled

Transfer between memory and I/O with 1 access
Memory wait cycle can be synchronized with I/O wait cycle during fly-by
Hold time can be obtained by delaying transfer access only
Specific idle/recovery cycles can be set for fly-by transfer

ˇ External bus arbitration using BRQ and BGRNT enabled
ˇ Pins not used in external interface can be set for use as general purpose I/O ports

MB91307 Series

(3) Block Diagram

(4) I/O Pins

These are the external interface pins. (Some pins have dual functions.)

< Normal bus interface >

A24 to A0, D31 to D16

CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7

AS, SYSCLK, MCLK

WE, WR0 (UUB) , WR1 (ULB)

RDY, BRQ, BGRNT

< Memory interface >

MCLK

LBA (

AS) , BAA*

*: For burst ROM, Flash use

MUX

CS0 to CS7

RD
WR0, WR1
AS, BAA

BRQ
BGRNT
RDY

Write buffer

Read buffer

Switch

1 or

Address buffer

ASR

ASZ

Comparator

Data block

Address block

Resisters &

controls

External pin control block

All block control

Internal

address bus

Internal data

bus

External data bus

External address bus

MB91307 Series

< DMA interface >

IOWR, IORD

DACK0, DACK1, DACK2

DREQ0, DREQ1, DREQ2

DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2

(5) Register List

Reserved: This address is reserved, and should always be set to "0."

MODR: Cannot be accessed from user programs.

Address 31

24 23

16 15

08 07

00000640

ASR0

ACR0

00000644

ASR1

ACR1

00000648

ASR2

0000064C

ASR3

ACR3

00000650

ASR4

ACR4

00000654

ASR5

ACR5

00000658

ASR6

ACR6

0000065C

ASR7

ACR7

00000660

AWR0

AWR1

00000664

AWR2

AWR3

00000668

AWR4

AWR5

0000066C

AWR6

AWR7

00000670

Reserved

00000674

Reserved

00000678

IOWR0

IOWR1

IOWR2

Reserved

0000067C

Reserved

00000680

CSER

CHER

Reserved

TCR

00000684

Reserved

00000688

Reserved

0000068C

Reserved

000007F8

Reserved

000007FC

Reserved

(MODR)

Reserved

MB91307 Series

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

*1 : The parameter is based on V

0 V.

*2 : V

must not be lower than V

0.3 V.

*3 : AV

and AVRH shall never exceed V

0.3 V. Also AVRH shall never exceed AV

*4 : Maximum output current determines the peak value of any one of the corresponding pins.

*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the

corresponding pins.

*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the

corresponding pins.

*7 :

Applicable to pins : P20 to P27, P60 to P67, P70, PJ0 to PJ7, PI0 to PI5, PH0 to PH7, PB0 to PB5, PA0 to
PA7, P80 to P82, P85, P90 to P97, AN0 to AN3

Use within recommended operating conditions.

Use at DC voltage (current) .

The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.

The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

Parameter

Symbol

Rating

Unit

Remarks

Min

Max

Supply voltage*

0.5

4.0

Internal supply voltage

CCI

0.5

2.2

Analog supply voltage

0.5

4.0

Analog reference voltage

AVRH

0.5

4.0

Input voltage*

0.3

Analog pin input voltage

0.3

Output voltage*

0.3

Maximum clamp current

CLAMP

2.0

Total maximum clamp current

CLAMP

L level maximum output current

L level average output current

OLAV

L level maximum total output current

100

L level average total output current

OLAV

H level maximum output current

H level average output current

OHAV

H level maximum total output current

H level average total output current

OHAV

Power consumption

750

Operating temperature

Storage temperature

STG

150

MB91307 Series

Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.

Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V), the power supply is
provided from the pins, so that incomplete operation may result.

Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

Care must be taken not to leave the +B input pin open.

Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.

Sample recommended circuits :

*8 : V

and V

must never exceed V

0.3 V. However if the maximum current to/from an input is limited by some

means with external components, the I

CLAMP

rating supersedes the V

rating.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

Input/Output Equivalent circuits

B input (0 V to 16 V)

Protective diode

Limiting

resistance

MB91307 Series

Recommended Operating Conditions

0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

Parameter

Symbol

Value

Unit

Remarks

Min

Max

Supply voltage

3.0

3.6

CCI

1.65

1.95

Analog supply voltage

0.3

3.6

Analog reference voltage

AVRH

Operating temperature

MB91307 Series

DC Characteristics

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

* : Pins without hysteresis input pins: D16 to D31, RDY, BRQ, INIT

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Typ

Max

"H" level input
voltage

See note *

0.7

0.3

HIS

Input pins
other than *

0.8

0.3

Hysteresis
input

"L" level input
voltage

See note *

0.25

ILS

Input pins
other than *

0.2

Hysteresis
input

"H" level output
voltage

D16 to D31

A00 to A25

P6 to PH

3.0 V

4.0 mA

0.5

"L" level output
voltage

D16 to D31

A00 to A25

P6 to PH

3.0 V

8.0 mA

0.4

Input leak
current
(Hi-Z output leak
current)

D16 to D31

A00 to A25

P8 to PH

3.6 V

0.45 V<V

Pull-up resistance

INIT

3.6 V

0.45 V

100

Pull-down
resistance

DOWN

P82/BRQ

3.6 V

3.3 V

100

Supply current

CCI(

16.5 MHz

3.3 V

CCI

1.8 V

150

(4x
multiplied)
66 MHz
operation

CCS

16.5 MHz

3.3 V

CCI

1.8 V

Sleep mode

CCH

3.3 V

CCI

1.8 V

150

Stop mode

Input capacitance

Other than:

MB91307 Series

AC Characteristics

(1) Clock Timing Standards

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

*1 : When using the PLL, the clock frequency should be around 12.5 to 16.5 MHz.

*2 : The values shown represent a minimum clock frequency of 12.5 MHz input at the X0 pin, using the oscillator

circuit PLL and a gear ratio of 1/16.

Parameter

Symbol

Pin

name

Condi-

tion

Value

Unit

Remarks

Min

Max

Clock frequency (1)

X0
X1

12.5

16.5

MHz

PLL system*

(self oscillation
16.5MHz,multiplied
x4,maximum internal
operation 66MHz)

Clock cycle time

X0
X1

60.6

Clock frequency (2)

X0
X1

MHz

Self oscillation (x1/2
frequency input)

Clock frequency (3)

X0
X1

MHz

External clock

Clock cycle time

X0
X1

100

Input clock pulse width

X0
X1

Input clock rise, fall time

X0
X1

)

Internal operating clock frequency

0.78

MHz CPU system

CPP

0.78

MHz Peripheral system

CPT

0.78

MHz External bus system

Internal operating clock cycle time

15.2

1280

CPU system

CPP

30.3

1280

Peripheral system

CPT

15.2

1280

External bus system

MB91307 Series

Clock timing measurement conditions:

Warranted operating range

External/internal clock setting range

Notes : ˇ When using the PLL, the external clock input should be around 16.5 MHz.

ˇ Set PLL oscillator stabilization time > 300

ˇ The internal clock gear setting should be within the values shown in (1) clock timing standards.

0.8 V

0.2 V

50 pF

Output pin

(MHz)

1.95

1.65

/ f

CPP

0.78

(V)

Internal clock

Power supply

Warranted operating temperature:
(T

C to +70

CPP

is represented by the shaded area

(MHz)

16.5

4 : 4

2 : 2

1 : 2

CPT

CPP

Internal clock

CPU: Divided ratio for peripherals

Peripheral system

CPU, external bus systems

MB91307 Series

(2) Clock Output Timing

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

*1 : t

CYC

represents the frequency of one clock cycle including the gear period.

*2 : The values shown represent standards for

1 gear period.

For gear period settings of 1/2, 1/4, 1/8, use the following formula replacing n with the value 1/2, 1/4, 1/8
respectively.

(1/2

1/n)

CYC

*3 : The values shown represent standards for

1 gear period.

Note : t

CPT

indicates the internal operating clock time. See " (1) Clock Timing Standards".

Parameter

Symbol

Pin

name

Conditions

Value

Unit

Remarks

Min

Max

Cycle time

CYC

MCLK,

SYSCLK

CPT

MCLK

SYSCLK

CHCL

MCLK,

SYSCLK

1/2

CYC

1/2

CYC

MCLK

SYSCLK

CLCL

MCLK,

SYSCLK

1/2

CYC

1/2

CYC

MCLK,
SYSCLK

CYC

CLCH

CHCL

MB91307 Series

(3) Reset and Hardware Standby Input Standards

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

* : INIT input time (at power-on)

FAR, Ceralock :

or greater recommended

Crystal

or greater recommended

: Power on

X0/X1 period

Note : t

indicates the clock cycle time. See " (1) Clock Timing Standards".

Parameter

Symbol

Pin

name

Conditions

Value

Unit

Remarks

Min

Max

Hardware standby input time

HSTL

CCI

INIT input time
(power-on)

INTL

INIT

INIT input time
(other than power-on)

INIT

0.2 V

RSTL

, t

HSTL

, t

INTL

HST

MB91307 Series

(4) Normal Bus Access Read/Write Operation

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

* : To extend bus time by automatic wait insertion or RDY input, add to this value (t

CYC

number of extended cycles).

Note : t

CYC

indicates the cycle time. See " (2) Clock Output Timing".

Parameter

Symbol

Pin name

Condition

Value

Unit Remarks

Min

Max

CS0 to CS7 setup

CSLCH

MCLK, SYSCLK,

CS0 to CS7

CS0 to CS7 hold

CSHCH

CYC

Address setup

ASCH

MCLK, SYSCLK,

A23 to A00

Address hold

CHAX

MCLK, SYSCLK,

A23 to A00

CYC

Valid address

valid data input time

AVDV

A23 to A00,

D31 to D16

3/2

CYC

WR0 to WR1 delay time

CHWL

MCLK, SYSCLK,

WR0 to WR1

CHWH

WR0 to WR1 minimum pulse
width

WLWH

WR0 to WR1

CYC

Data setup

WRx

DSWH

WR0 to WR1,

D31 to D16

CYC

WRx

data hold time

WHDX

RD delay time

CHRL

MCLK, SYSCLK,

CHRH

valid data input time

RLDV

RD,

D31 to D16

CYC

Data setup

time

DSRH

data hold time

RHDX

RD minimum pulse width

RLRH

CYC

AS setup

ASLCH

MCLK, SYSCLK,

AS hold

ASHCH

MB91307 Series

(5) Ready Input Timing

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

RDY setup time

MCLK

, SYSCLK

RDYS

MCLK, SYSCLK,

RDY

MCLK

, SYSCLK

RDY hold time

RDYH

MCLK, SYSCLK,

RDY

MCLK,
SYSCLK

RDYH

RDY

CYC

RDYS

CHASL

Wait applied

Wait not applied

MB91307 Series

(6) Hold Timing

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

Note: After a BRQ is accepted, a minimum of 1 cycle is required before BGRNT changes.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

BGRNT delay time

CHBGL

MCLK, SYSCLK,

BGRNT

13.5

CHBGH

13.5

Pin floating

BGRNT

time

XHAL

BGRNT

CYC

BGRNT

valid time

HAHV

CYC

MCLK,
SYSCLK

CHBGL

CHBGH

BRQ

BGRNT

CYC

HAHV

HXAL

Pins

High-Z

MB91307 Series

(7) UART Timing

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

Notes: ˇ Above ratings are for operation in CLK synchronized mode.

ˇ t

CPP

is the cycle time of the peripheral system clock.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Serial clock cycle time

SCYC

SC0 to SC2

Internal

shift lock

mode

8 t

CPP

SCLK

SOUT delay time

SLOV

SC0 to SC2,

SO0 to SO2

Valid SIN

SCLK

IVSH

SC0 to SC2,

SI0 to SI2

100

SCLK

valid SIN hold time

SHIX

SC0 to SC2,

SI0 to SI2

Serial clock "H" pulse width

SHSL

SC0 to SC2

External

shift lock

mode

4 t

CPP

Serial clock "L" pulse width

SLSH

SC0 to SC2

4 t

CPP

SCLK

SOUT delay time

SLOV

SC0 to SC2,

SO0 to SO2

150

Valid SIN

SCLK

IVSH

SC0 to SC2,

SI0 to SI2

SCLK

valid SIN hold time

SHIX

SC0 to SC2,

SI0 to SI2

Internal Shift Clock Mode

External Shift Clock Mode

SC0, SC1

SO0, SO1

SI0, SI1

SCYC

SLOV

IVSH

SHIX

SC0, SC1

SO0, SO1

SI0, SI1

SLOV

SLSH

SHSL

IVSH

SHIX

MB91307 Series

(8) Timer Clock Input Timing

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

Note: t

CYCP

is the cycle time of the peripheral system clock.

(9) Trigger Input Timing

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

Note: t

CYCP

is the cycle time of the peripheral system clock.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Input pulse width

TIWH

TIWL

TIN0 to TIN2

2 t

CYCP

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

A/D startup trigger input time

ATGX

ATG

5 t

CYCP

TIWH

TIWL

TIN0 to TIN2

ATG

ATGX,

INP

, t

PTG

MB91307 Series

(10) DMA Controller Timing

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

DREQ input pulse width

DRWH

DREQ 0 to DREQ2

5 t

CYC

DSTP input pulse width

DSWH

DSTP 0 to DSTP2

5 t

CYC

DACK delay time

CLDL

MCLK, SYSCLK,

DACK0 to DACK2

CLDH

DEOP delay time

CLEL

MCLK, SYSCLK,

DEOP 0 to DEOP2

CLEH

IORD delay time

CLIRL

MCLK, SYSCLK

CLIRH

IOWR delay time

CLIWL

MCLK, SYSCLK

CLIWH

MB91307 Series

(11) I

C Timing

CCI

1.65 V to 1.95 V, V

3.0 V to 3.6 V, V

0 V, T

C to

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t

HDDAT

only has to be met if the device does not stretch the "L" width (t

LOW

) of the SCL signal.

*3 : A Fast-mode I

C-bus device can be used in a Standard-mode I

C-bus system, but the requirement

SUDAT

250 ns must then be met.

*4 : For use at over 100 kHz, set the resource clock to at least 6 MHz.

Parameter

Symbol

Condition

Standard mode

High-speed mode*

Unit

Min

Max

Min

Max

SCL clock frequency

SCL

1.0 k

50 pF*

100

400

kHz

(Repeat) "start" condition hold time
SDA

SCL

HDSTA

4.0

0.6

SCL clock "L" width

LOW

4.7

1.3

SCL clock "H" width

HIGH

4.0

0.6

Repeat "start" condition setup time
SCL

SDA

SUSTA

4.7

0.6

Data hold time
SCL

SDA

HDDAT

3.45*

0.9*

Data setup time
SDA

SCL

SUDAT

250

100

"Stop" condition setup time
SCL

SDA

SUSTO

4.0

0.6

Bus free time between "stop" and
"start" conditions

BUS

4.7

1.3

SDA

SCL

BUS

SUSTA

HDSTA

SUSTO

HIGH

HDDAT

HDSTA

LOW

SUDAT

MB91307 Series

A/D Converter Electrical Characteristics

CCI

1.65 V to 1.95 V, V

3.0 V to

3.6 V, V

0 V, T

C to

*1 : At V

= AV

= 3.0 V to 3.6 V, V

CCI

1.65 V to 1.95 V machine clock 33 MHz.

*2 : Current in CPU stop mode with A/D converter not operating (at V

= AV

= AVRH = 3.6 V, V

CCI

1.95 V)

ˇ About the external impedance of the analog input and its sampling time

ˇ A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.

Parameter Symbol

Pin

name

Value

Unit

Min

Typ

Max

Resolution

BIT

Total error

4.5

LSB

Linear error

3.0

LSB

Differential linear error

2.5

LSB

Zero transition error

AN0 to AN3

1.5

0.5

4.5

LSB

Full scale transition error

FST

AN0 to AN3

AVRH

4.5

AVRH

1.5

AVRH

4.5

LSB

Conversion time

5.4 *

Analog port input current

AIN

AN0 to AN3

0.1

Analog input voltage

AIN

AN0 to AN3

AVss

AVRH

Reference voltage

AVRH

AVss

Supply current

600

10 *

Reference voltage supply current

AVRH

600

10 *

Inter-channel variation

AN0 to AN3

LSB

During sampling : ON

Analog input

Comparator

ˇ Analog input circuit model

Note : The values are reference values.

MB91307R/306R

5.0 k

(Max) 15 pF (Max)

MB91V307R

8.1 k

(Max) 10 pF (Max)

MB91307 Series

ˇ To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the operating frequency or decrease the external impedance
so that the sampling time is longer than the minimum value.

ˇ If the sampling time cannot be sufficient, connect a capacitor of about 0.1 mF to the analog input pin.

ˇ About errors

As | AVRH | becomes smaller, values of relative errorsgrow larger.

MB91V307R

MB91307R
MB91306R

100

MB91V307R

MB91307R
MB91306R

External impedance

0 k

to 100 k

External impedance

0 k

to 20 k

External impedance [k

]

External impedance [k

]

Minimum sampling time [

The relationship between external impedance and minimum sampling time

MB91307 Series

Definition of A/D Converter Terms

ˇ Resolution

Indicates the ability of the A/D converter to discriminate analog variation

ˇ Linear error

Expresses the deviation between actual conversion characteristics and a straight line connecting the device's
zero transition point (00 0000 0000

00 0000 0001) and full scale transition point (11 1111 1110

1111 1111)

ˇ Differential linear error

Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output
code.

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

{1 LSB

}

FST

AVRL

AVRH

1)T

[Linear Error]

[Differential linear error]

Digital output

Actual variation

(measured

value)

(measured

value)

Actual variation

Theoretical values

(measured value)

Analog input

Theoretical

Actual variation

(measured

value)

(measured value)

Actual variation

Linear error in digital output N

{1 LSB

}

1 LSB

[LSB]

Differential linear error in digital output N

V (

)

1 LSB

FST

1022

[V]

1 LSB"

AVRH

AVRL

1024

[V]

: Voltage at which the digital output transitions from "000"

to "001"

FST

: Voltage at which the digital output transitions from "3FE"

to "3FF"

: Voltage at which the digital output transitions from (N-1) to N.

[LSB]

(theoretical value)

MB91307 Series

ˇ Total error

Expresses the difference between actual and theoretical values as error, including zero transition error, full-
scale error, and linearity error.

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

1.5 LSB

0.5 LSB

{1 LSB

0.5 LSB

[Total error]

Digital output

Actual variation

(measured

value)

Actual variation

theoretical value

Analog input

Total error in digital output N

{1 LSB"

0.5 LSB"}

1 LSB"

[LSB]

" (theoretical value)

AVRL

0.5 LSB" [V]

FST

" (theoretical value)

AVRH

1.5 LSB" [V]

: Voltage at which digital output transitions from (N-1) to N.

MB91307 Series

EXAMPLE CHARACTERISTICS

(Continued)

(1) Sample output voltage characteristics (T

(2) Sample input voltage characteristics (T

(3) Sample supply current characteristics

Output voltage (V)

Supply voltage (V)

0.4

0.3

0.2

0.1

0.0

3.0

3.2

3.4

3.6

Supply voltage (V)

Output voltage (V)

3.6

3.4

3.2

3.0

2.8

3.0

3.2

3.4

3.6

Sample output H voltage (V

) characteristics

Sample output L voltage (V

) characteristics

3.0

2.0

1.0

0.0

3.0

3.2

3.4

3.6

Input voltage (V)

Supply voltage (V)

3.0

2.0

1.0

0.0

3.0

3.2

3.4

3.6

Supply voltage (V)

Input voltage (V)

Sample input H/L level characteristics (CMOS)

Sample input H/L level characteristics (hysteresis)

200

150

100

3.0

3.2

3.4

3.6

Supply current (mA)

Supply voltage (V)

200

150

100

0.0

Temperature (

Supply current (mA)

Sample supply current (I

) characteristics

C, 66 MHz)

Sample supply current (I

) characteristics

3.3 V, 66 MHz)

MB91307 Series

(Continued)

(4) Port resistance characteristics

Sample sleep current (I

CCS

) characteristics

C, 33 MHz)

3.0

3.2

3.4

3.6

Supply current (mA)

Supply voltage (V)

Sample sleep current (I

CCS

) characteristics

3.3 V, 33 MHz)

Supply current (mA)

Temperature (

Sample A/D supply current (I

) characteristics

C, 33 MHz)

500

400

300

200

3.0

3.2

3.4

3.6

Supply current (

Supply voltage (V)

Sample A/D reference current (I

) characteristics

C, 33 MHz)

500

400

300

200

3.0

3.2

3.4

3.6

Supply current (

Supply voltage (V)

3.0

3.2

3.4

3.6

Supply voltage (V)

Resistance (k

)

3.0

3.2

3.4

3.6

Supply voltage (V)

Resistance (k

)

Sample pull-up resistance characteristics

Sample pull-down resistance characteristics

MB91307 Series

PACKAGE DIMENSION

120-pin, Plastic LQFP

(FPT-120P-M21)

Dimensions in mm (inches)
Note : The values in parentheses are reference values.

2002 FUJITSU LIMITED F120033S-c-4-4

120

18.00ą0.20(.709ą.008)SQ

0.50(.020)

0.22ą0.05

(.009ą.002)

0.08(.003)

INDEX

.006

.001

+.002

0.03

+0.05

0.145

"A"

0.08(.003)

LEAD No.

.059

.004

+.008

0.10

+0.20

1.50

Details of "A" part

(Mounting height)

0.60ą0.15

(.024ą.006)

0.25(.010)

(.004ą.002)

0.10ą0.05

(Stand off)

0~8°

.630

.004

+.016

0.10

+0.40

16.00

Note 1) * : These dimensions do not include resin protrusion.

Resin protrusion is +0.25(.010) MAX(each side).

Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.

MB91307 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party's
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0502

2005 FUJITSU LIMITED Printed in Japan

Part Number MB91307

Document Outline