DS07-16307-3E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-Bit RISC Microcontroller

CMOS

FR Family MB91110 Series

MB91110/MB91V110

DESCRIPTION

The MB91110 series is a standard single-chip micro controller featuring various I/O resources and bus control
mechanisms to incorporate the control with required for high performance high-speed CPU processes, having a
32-bit RISC CPU (FR30 series) in its core. Although external bus access is the basis for supporting a large address
space accessible by a 32-bit CPU, a 1-KB instruction cache memory has been built-in to increase the instruction/
execution speed of the CPU.

This unit features the optimal specifications for incorporating applications that require high performance CPU
processing power such as navigation systems, high performance facsimile systems, printer control, etc.

FEATURES

FR30CPU
ˇ 32-bit RISC, load / store architecture, 5-level pipeline
ˇ Operating frequency : external 25 MHz, internal 50 MHz
ˇ Multi-purpose register : 32 bits

ˇ 16-bit fixed length instructions (basic instruction) , 1 instruction per cycle
ˇ Instructions for barrel shift, bit processing and inter memory transfers : Instructions suited to loading purposes

(Continued)

PACKAGE

144-pin plastic LQFP

(FPT-144P-M08)

MB91110 Series

(Continued)

ˇ Function entry / exit instruction, multi load / store instruction of register details : Instruction capable of handling

High level language instruction.

ˇ Register Interlock function : Simplification of assembler description
ˇ Branch instruction with delay slot : Reduction in overheads in case of branching
ˇ Multiplier is built-in / Supported at instruction level

Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles

ˇ Interruption (saving PC and PS) : 6 cycles, 16 priority levels

Bus Interface
ˇ 24-bit address bus (16 MB space)
ˇ Operating frequency : 25 MHz
ˇ 16- / 8-bit data bus
ˇ Basic external bus cycle : 2 clock cycles
ˇ Chip select output that can be set to a minimum 64-Kbyte units
ˇ Interface support for various memories

DRAM interface (areas 4, 5)

ˇ Automatic waiting cycle : Can be randomly set from 0 to 7 cycles per area
ˇ Unused data and address pins can be used as input/output ports.
ˇ Supports "little endian" mode (One area is selected from areas 1 to 5)

DRAM Interface
ˇ 2-bank individual control (area 4, 5)
ˇ Normal mode / high speed page mode
ˇ Basic bus cycles : normally 5 cycles, 1 cycle access is possible in high-speed page mode.
ˇ Programmable waveform : 1 cycle waiting can be inserted automatically in RAS and CAS.
ˇ DRAM refresh

CBR refresh (Interval is randomly set using the 6-bit timer.)
Self refresh mode

ˇ Supports addresses for 8, 9, 10 and 12 columns
ˇ 2CAS/1WE or 2WE/1CAS can be selected.

Cache Memory
ˇ 1 KB instruction cache
ˇ 2 way set associative
ˇ 32 blocks / way, 4 entries (4 words) / block
ˇ Lock function : Residing in the specified program codes at cache

DMA Controller (DMAC)
ˇ 5 channels
ˇ External

external 2.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle)

ˇ Internal

external 1.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle)

ˇ Address register (inc, dec, or reload are possible) : 32 bits

5 channels

ˇ Transfer count register (reload possible) : 16 bits

5 channels

ˇ Transfer factors : external pin / built-in resources interruption request / software
ˇ Transfer sequence

Step transfer / block transfer
Burst / consecutive transfer

ˇ Transfer data length : 8-bit, 16-bit or 32-bit can be selected
ˇ Suspension is possible using NMI / interruption request

MB91110 Series

UART
ˇ Fully duplicated double buffer
ˇ Data length : 7 to 9 bits (without parity) , 6 to 8 bits (with parity)
ˇ Asynchronous (start-stop synchronization) or CLK synchronized communication can be selected.
ˇ Multiprocessor mode
ˇ Dedicated baud rate generator is built-in.
ˇ External clock can be used as the transfer clock
ˇ Baud rate clock can be output
ˇ Error detection : parity, frame, overrun

PPG Timer
ˇ 16 bits, 6 channels (frequency setting register / duty setting register)
ˇ PWM function or one-shot function can be selected
ˇ Initiation : Software or external trigger can be selected

A/D Converter (sequential conversion type)
ˇ 10-bit resolution, 8 channels
ˇ Sequential comparison conversion : 5.6

s in the case of 25 MHz

ˇ Sample & hold circuit is built-in.
ˇ Conversion mode : Single, scan or repeat conversion can be selected.
ˇ Initiation : Software, external trigger or built-in timer can be selected.

Reloading Timer
ˇ 16-bit timer : 2 channels
ˇ Internal clock : 2 clock cycle resolutions, 2, 8 or 32 cycles can be selected.
ˇ Pin input : event counter input / gate function
ˇ Rectangular wave output

Other Interval Timer
ˇ Watchdog timer : 1 channel

Bit Search Module
ˇ Searches the first "1" / "0" change bit positions within 1 cycle from MSB in 1 word.

Interruption Controller
ˇ External interruption input : Mask impossible interruption (NMI) , normal interruption

8 (INT0 to INT7)

ˇ Internal interruption factors : UART, DMAC, A/D, reloading timer, PPG timer, delay interruption
ˇ Priority levels are programmable except for mask impossible interruption (16 levels)

Reset Factors
ˇ Power-on reset / hardware standby / watchdog timer / software reset / external reset

Low Power Consumption Mode
ˇ Sleep / stop mode

Clock Control
ˇ Gear functions : Operating clock frequencies peripheral to the CPU can be set randomly and independently.

Gear locks can be selected from 1/1, 1/2, 1/4 or 1/8 (or 1/2, 1/4, 1/8, or 1/16) .

Others
ˇ Package : LQFP-144
ˇ CMOS technology : 0.35

ˇ Power : 5.0 V

, 3.3 V

MB91110 Series

PIN ASSIGNMENT

(TOP VIEW)

(FPT-144P-M08)

PE3/TRG2, 5

PF0/INT0
PF1/INT1
PF2/INT2
PF3/INT3
PF4/INT4
PF5/INT5
PF6/INT6
PF7/INT7

PG0/DREQ0

PG1/DACK0

PG2/DEOP0

PG3/DREQ1

PG4/DACK1

PG5/DEOP1

PH0/DREQ2

PH1/DACK2

PH2/DEOP2

PH3/SI

PH4/SO

PH5/SCK

PH6/TI0

PH7/TO0

PI0/TI1

PI1/TO1

PI2/PPG0
PI3/PPG1
PI4/PPG2
PI5/PPG3
PI6/PPG4
PI7/PPG5

NMI
DW1/PB7
CS1H/PB6
CS1L/PB5
RAS1/PB4
V

DW0/PB3
CS0H/PB2
CS0L/PB1
RAS0/PB0
CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3
CS2/PA2
CS1/PA1
CS0
V

WR1/P85
WR0
RD
BRQ/P82
BGRNT/P81
RDY/P80
V

A23/P67
A22/P66
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
V

110

115

120

125

130

135

140

TRG1, 4/PE2

TRG0, 3/PE1

ATG/PE0

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

AVRL

AVRH

(OPEN)

HST

RST

MD2

MD1

MD0

P20/D16

P21/D17

P22/D18

P23/D19

P24/D20

P25/D21

P26/D22

P27/D23

D24

D25

D26

D27

D28

D29

D30

D31

A00

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

105

100

INDEX

MB91110 Series

PIN DESCRIPTIONS

(Continued)

Pin no.

Pin name

I/O*

Circuit type

Function

1
2
3
4
5
6
7
8

D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27

I/O

These pins use bits 16 to 23 of the external data bus.
They can be used as a port (P20 to P27) if the external bus
width is 8 bits.

10
11
12
13
14
15
16
17

D24
D25
D26
D27
D28
D29
D30
D31

I/O

These pins use bits 24 to 31 of the external data bus.

20
21
22
23
24
25
26
27

A00
A01
A02
A03
A04
A05
A06
A07

I/O

These pins use bits 00 to 07 of the external address bus.

29
30
31
32
33
34
35
36

A08
A09
A10
A11
A12
A13
A14
A15

I/O

These pins use bits 08 to 15 of the external address bus.

38
39
40
41
42
43
44
45

A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67

I/O

These pins use bits 16 to 23 of the external address bus.

RDY/P80

I/O

This is for external ready input. "0" is input if the bus cycle be-
ing executed is incomplete. It can be used as a port when not
otherwise used.

BGRNT/P81

I/O

This is the external bus open reception output. "L" is output if
the external bus is opened. It can be used as a port when not
otherwise used.

MB91110 Series

(Continued)

Pin no.

Pin name

I/O*

Circuit type

Function

BRQ/P82

I/O

This is the external bus open request input. "1" is input if the
external bus is to be opened. It can be used as a port when
not otherwise used.

This is the external bus read strobe.

WR0

This is the external bus write strobe.

WR1/P85

I/O

CS0

Chip select 0 output (Low active)

56
57
58
59
60

CS1/PA1
CS2/PA2
CS3/PA3
CS4/PA4
CS5/PA5

I/O

Chip select 1 output (Low active)
Chip select 2 output (Low active)
Chip select 3 output (Low active)
Chip select 4 output (Low active)
Chip select 5 output (Low active)
They can be used as ports when not otherwise used.

CLK/PA6

I/O

This is the system clock output. The same clock as the stan-
dard clock is output. This can be used as a port when not oth-
erwise used.

62
63
64
65
68
69
70
71

RAS0/PB0

CS0L/PB1

CS0H/PB2

DW0/PB3

RAS1/PB4

CS1L/PB5

CS1H/PB6

DW1/PB7

I/O

RAS output with DRAM bank 0.
CASL output with DRAM bank 0.
CASH output with DRAM bank 0.
WE output with DRAM bank 0. (Low active)
RAS output with DRAM bank 1.
CASL output with DRAM bank 1.
CASH output with DRAM bank 1.
WE output with DRAM bank 1. (Low active)
They can be used as ports when not otherwise used.

NMI

Non Maskable Interrupt (NMI) input. (Low active)

73
74
75

MD0
MD1
MD2

These are mode pins from 0 to 2.
Basic MCU operation modes are set using these pins.
They should be connected directly to V

or V

for use.

77
78

X0
X1

Clock (oscillation) input.
Clock (oscillation) output.

RST

This is the external reset input. (Low active)

HST

This is the hardware standby input. (Low active)

(OPEN)

Set this to OPEN.

84
85
86

(OPEN)
(OPEN)
(OPEN)

Set this to OPEN.

16-bit bus width

8-bit bus width

D31-24

WR0

D23-16

WR1

(Port is possible)

MB91110 Series

(Continued)

Pin no.

Pin name

I/O*

Circuit type

Function

87
88
89
90

(OPEN)
(OPEN)
(OPEN)
(OPEN)

Set this to OPEN.

(OPEN)

Set this to OPEN.

power supply for the A/D converter.

AVRH

A/D converter reference voltage (high potential side).
Be sure to turn on/off this pin with potential higher than AVRH
applied to V

AVRL

A/D converter reference voltage (low potential side).

power supply for the A/D converter.

96
97
98
99

100
101
102
103

AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7

[AN0 to 7] A/D converter analog input.

106

ATG/PE0

I/O

[ATG] This is the external trigger input for the A/D converter.
This function is always used if selected as the initiation factor
for A/D, so output by other functions should be stopped ex-
cept when it is carried out intentionally.

[PE0] This is a general-purpose input/output port.

107
108
109

TRG0, 3/PE1
TRG1, 4/PE2
TRG2, 5/PE3

I/O

[TRG0 to 5] These are external trigger input pins of the PPG.

[PE1 to 3] These are general-purpose input/output ports.

110
111
112
113
114
115
116
117

INT0/PF0
INT1/PF1
INT2/PF2
INT3/PF3
INT4/PF4
INT5/PF5
INT6/PF6
INT7/PF7

I/O

[INT0 to 7] These are external interruption request inputs.
This input is always used while the corresponding external
interruption is permitted, so output using other functions
should be stopped except when carried out intentionally.

[PF0 to 7] These are general-purpose input/output ports.

119

DREQ0/PG0

I/O

[DREQ0] This is the DMA external transfer request input (ch
0) . This input is always used if selected as the transfer factor
for DMAC, so outputs from other functions should be
stopped except when carried out intentionally.

[PG0] This is a multi-purpose input/output port.

MB91110 Series

(Continued)

Pin no.

Pin name

I/O*

Circuit type

Function

120

DACK0/PG1

I/O

[DACK0] This is the DMAC external transfer request recep-
tion output (ch 0) . This function is effective if the transfer re-
quest reception output specification of DMAC is permitted.

[PG1] This is a multi-purpose input/output port. This function
is effective if the transfer request reception output specifica-
tion of DMAC is prohibited.

121

DEOP0/PG2

I/O

[DEOP0] This is the DMA transfer end signal output (ch 0) .
This function is effective if the transfer end signal output
specification of DMAC is permitted.

[PG2] This is a multi-purpose input/output port. This function
is effective if the transfer end signal output specification of
DMAC is prohibited.

122

DREQ1/PG3

I/O

[DREQ1] This is the DMA external transfer request input (ch
1) . This input is always used if selected as the transfer factor
of DMAC, so output using other functions should be stopped
except when carried out intentionally.

[PG3] This is a multi-purpose input/output port.

123

DACK1/PG4

I/O

[DACK1] This is the DMAC external transfer request recep-
tion output (ch 1) . This function is effective if the transfer re-
quest reception output specification of DMAC is permitted.

[PG4] This is a multi-purpose input/output port. This function
is effective if the transfer request reception output specifica-
tion of DMAC is prohibited.

124

DEOP1/PG5

I/O

[DEOP1] This is the DMA transfer end signal output (ch 1) .
This function is effective if the transfer end signal output
specification of DMAC is permitted.

[PG5] This is a multi-purpose input/output port. This function
is effective if the transfer end signal output specification of
DMAC is prohibited.

127

DREQ2/PH0

I/O

[DREQ2] This is the DMA external transfer request input (ch
2) . This input is always used if selected as the transfer factor
of DMAC, so output using other functions should be stopped
except when carried out intentionally.

[PH0] This is a multi-purpose input/output port.

128

DACK2/PH1

I/O

[DACK2] This is the DMAC external transfer request recep-
tion output (ch 2) . This function is effective if the transfer re-
quest reception output specification of DMAC is permitted.

[PH1] This is a multi-purpose input/output port. This function
is effective if the transfer request reception output specifica-
tion of DMAC is prohibited.

MB91110 Series

(Continued)

Pin no.

Pin name

I/O*

Circuit type

Function

129

DEOP2/PH2

I/O

[DEOP2] This is the DMA transfer end signal output (ch 2) .
This function is effective if the transfer end signal output
specification of DMAC is permitted.

[PH2] This is a multi-purpose input/output port. This function
is effective if the transfer end signal output specification of
DMAC is prohibited.

130

SI/PH3

I/O

[SI] This is UART data input. This input is always used while
UART inputs, so outputs from other functions should be
stopped except when carried out intentionally.

[PH3] This is a general-purpose input/output port.

131

SO/PH4

I/O

[SO] This is UART data output. This function is effective
when UART data output specification is permitted.

[PH4] This is a general-purpose input/output port. This func-
tion is effective when UART data output specification is pro-
hibited.

132

SCK/PH5

I/O

[SCK] This is UART clock input/output. Clock output is effec-
tive when UART clock output specification is permitted.

[PH5] This is a general-purpose input/output port. This func-
tion is effective when UART clock output specification is pro-
hibited.

133

TI0/PH6

I/O

[TI0] This is reload timer 0 input. It is always used when re-
load timer input is permitted, so outputs from other functions
should be stopped except when carried out intentionally.

[PH6] This is a general-purpose input/output port.

134

TO0/PH7

I/O

[TO0] This is reload timer 0 Output. This function is effective
when reload timer specification is permitted.

[PH7] This is a general-purpose input/output port. This func-
tion is effective when reload timer specification is prohibited.

136

TI1/PI0

I/O

[TI1] This is reload timer 1 input. It is always used when re-
load timer input is permitted, so outputs from other functions
should be stopped except when carried out intentionally.

[PI0] This is a general-purpose input/output port.

137

TO1/PI1

I/O

[T01] This is the reload timer 1 output. This function is effec-
tive if the output specification of the reload timer is permitted.

[PI1] This is a multi-purpose input/output port. This function
is effective if the output specification of the reload timer is
prohibited.

MB91110 Series

(Continued)

* : I/O shown above indicates input/output classification.

Note : The I/O port and resource input/outputs for most of the above pins are multiplexed, i.e. Pxx/xxxx. In the event

of both the port and resource outputs were to use the same pins, the resource is given priority.

Pin no.

Pin name

I/O*

Circuit type

Function

138
139
140
141
142
143

PPG0/PI2
PPG1/PI3
PPG2/PI4
PPG3/PI5
PPG4/PI6
PPG5/PI7

I/O

[PPG0 to 5] This is the PPG timer 1 output. This function is
effective if the output specification of the PPG timer is permit-
ted.

[PI2 to 7] This is a multi-purpose input/output port. This func-
tion is effective if the output specification of the PPG timer is
prohibited.

18
46
66
76

104
125

This provides power for the 5 V digital circuit system.

47
82

126

This provides power for the 3 V digital circuit system.

19
28
37
54
67
79

105
118
135
144

This is the earth level for digital circuits.

MB91110 Series

HANDLING DEVICES

ˇ Preventing Latch-up

The "Latch-up" phenomenon may be generated if a voltage in excess of V

or lower than V

is applied to the

input/output pins, or if the voltage exceeds the rating between V

and V

. If latch-up is generated, the electrical

current increases significantly and may destroy certain components due to the excessive heat, so great care
must be taken to ensure that the maximum rating is not exceeded during use.

ˇ Handling Unused Input Pins

Input pins that are not used should be pulled up or down as they may cause erroneous operations if they are
left open.

ˇ External Reset Input

"L" level should be input to the RST pin, which is required for at least five machine cycles to ensure the internal
status is reset.

ˇ Using External Clocks

If external clock is used, X0 pin should be provided, and X1 pin should be provided with reverse phase to X0
pin input. If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the "H"
output. So, when STOP mode is specified, approximately 1 k

of resistance should be added externally. An

example of the external clock usage methods is shown in the following circuit.

Note : Resistance must be added to the X1 pin if the STOP mode (oscillation stop mode) is used.

ˇ Power Supply Pins

In products with multiple Vcc or Vss pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However you must connect the pins to an external power and
a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.

Make sure to connect Vcc and Vss pins via the lowest impedance to power lines.

It is recommended to provide a bypass capacitor of around 0.1 F between Vcc and Vss pins near the device.

ˇ Crystal Oscillator Circuits

Noise around the X0 or X1 pins may cause erroneous operation. Make sure to provide bypass capacitors via
shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure
that lines of oscillation circuits not cross the lines of other circuit.

A printed circuit board artwork surrounding the X0 and X1 pins with ground area for stabilizing the operation is
highly recommended .

MB91110

Example of External Clock Usage (normal case)

MB91110 Series

ˇ N.C. Pins

N.C. pins must be opened for use.

ˇ Mode Pins (MD0 to MD2)

Those pins must be directly connected to V

or V

for use.

Pattern length between V

or V

and each mode pin on the printed-circuit board should be arranged to be as

short as possible to prevent the test mode being erroneously turned on due to noise, they should also be
connected with low impedance.

ˇ In the Event that Power Is Turned on

The RST pin must be started from "L" level when the power is turned on, and when the power is adjusted to the
V

level it should be changed to the "H" level after being left for at least five cycles of the internal operation clock.

ˇ Original Oscillation Input in the Event that Power Is Turned on

The clock must be input until the waiting status for oscillation stability is reset in the event that power is turned on.

ˇ Hardware Standby in the Event that Power Is Turned on

Standby is not set in the event that power is turned on while the HST pin is set at "L" level. The HST pin becomes
effective after being reset, but it must first be returned to "H" level.

ˇ Power on Reset

When power is turned on, "Power on reset" must be executed. If the power voltage falls below the guaranteed
operating voltage, "Power on reset" must be executed by turning on power supply again.

ˇ Restrictions for Standby

Programs to be set for stop and sleep must be placed address area of the external memory. If placed in the
RAM address area on the I-bus, operation can not be guaranteed after returning.

ˇ Execution of Programs in I-RAM Areas

In the event that programs in the I-RAM areas are executed, enter the I-RAM areas in accordance with the JMP
system instruction. Conversely, when changing from programs in the I-RAM area to those in other areas, exit
in accordance with the JMP system instructions.

ˇ Caution on Operation during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.

MB91110 Series

BLOCK DIAGRAM

FR30 CPU

D-bus (32 bit)

Harvard

Prinston

Bus Converter

Bit Search Module

DMAC (5 ch)

DREQ0
DACK0
DEOP0

DREQ1
DACK1
DEOP1

DREQ2
DACK2
DEOP2

32 bit 16 bit

Bus Converter

X0 X1

RST
HST

Clock Control Unit

INT0

INT7

NMI

Interrupt Control Unit

AN0

AN7

ATG

AVRH AVRL

TI0 TI1

TO0 TO1

A/D Converter (8 ch)

Reload Timer (2 ch)

Port E

R-bus (16 bit)

UART

16 bit PPG Timer

(6 ch)

SI
SO
SCK

PPG0

PPG5

TRG0

TRG5

(32 bit)

C-bus

Port 0

DRAM Controller

Bus Controller

RAS0
CS0L
CS0H
DW0

RAS1
CS1L
CS1H
DW1

D31

D16

A23

A00

RD
WR0

WR 1

RDY
CLK
CS0

CS5

BRQ BGRNT

RAM

PLL
50 MHz

5 KB

Instruction RAM

Instruction Cache

1 KB

16 KB

50 MHz

25 MHz

50 MHz

25 MHz

I-bus

(16 bit)

Notes :

Pins are described per function. Some of the pins are multiplexed.

In the event that REALOS is used, an external interruption or built-in timer should be used to control

the time.

MB91110 Series

MEMORY SPACE

The FR30 series has 4 Gbytes (2

addresses) of logic address space which the CPU accesses linearly.

Memory Map

Note : MB91110 series only supports external ROM external bus mode.

ˇ Direct addressing area

The following areas of the address space are used for I/O. This area is called the "direct addressing area" and
the address of the operand can be specified directly during instruction. The direct area differs depending on
data size to be accessed.

Byte data access

: 0-0FF

Half-word data access

: 0-1FF

Word data access

: 0-3FF

0000 0000

0000 0400

0000 0800

0000 1000

0000 2400

0001 0000

0008 0000

000B C000

000C 0000

0010 0000

FFFF FFFF

I/O

I-RAM 16 KB

External ROM external bus modes

Access is prohibited

Built-in RAM 5 KB

Access is prohibited

External area

Direct addressing area

(Refer to "I/O MAP")

MB91110 Series

Registers

There are two types of multi-purpose registers in the FR family. One is a dedicated purpose register that exists
within the CPU and the other is a multi-purpose register that exists in the memory.

ˇ Dedicated Registers

ˇ Program Status (PS)

PS is the register that holds the program status and is classified into three categories, namely, Condition Code
Register (CCR) , System Condition Code Register (SCR) and Interruption Level Master Register (ILM) .

Program Counter (PC)

: 32-bit length; indicates instruction storage position.

Program Status (PS)

: 32-bit length; stores register pointers and condition codes.

Table Base Register (TBR)

: Holds the starting address of the vector table to be used for Exception, In-

terruption and Trapping (EIT) .

Return Pointer (RP)

: Holds the address to which you will return to from the sub-routine.

System Stuck Pointer (SSP) : Indicates the systems stuck position.

User Stuck Pointer (USP)

: Indicates the user's stuck position.

Multiplication and Division
Results Resister (MDH/MDL)

: 32-bit length; These are the registers for multiplication and division.

TBR

SSP

USP

MDH

MDL

XXXX XXXX

(Undecided)

XXXX XXXX

(Undecided)

XXXX XXXX

(Undecided)

XXXX XXXX

(Undecided)

XXXX XXXX

(Undecided)

0000 0000

000F FC00

32 bit

Program Counter

Program Status

Table Base Register

Return Pointer

System Stuck Pointer

User Stuck Pointer

Multiplication and Division
Results Resister

Initial values

ILM4 ILM3 ILM2

ILM

SCR

CCR

ILM1 ILM0

31 to 21

15 to 11

MB91110 Series

ˇ Condition Code Register (CCR)

ˇ System Condition Code Register (SCR)

ˇ Interruption Level Mask Register (ILM)

S flag

: Specifies the stuck pointer to be used as R15.

I flag

: Controls permission and prohibition of user interruption requests.

N flag

: Indicates codes when the computation results are defined as integers that are expressed in

complements of 2.

Z flag

: Indicates if arithmetic results were "0."

V flag

Indicates when operands are used for computation and defined as integers expressed in com-
plements of 2, and indicates whether or not an overflow is generated as a result of the compu-
tation.

C flag

: Indicates whether carrying or borrowing is generated from the highest bit as a result of the com-

putation.

T flag

: Specifies whether or not the step- trace- trap will be valid.

ILM4 to ILM0 : Holds the interruption level mask values, and those values that are held by the ILM are used

for the level mask. Interruption requests can only be accepted when the interruption levels
handled within the interruption requests to be input into the CPU are stronger than the levels
shown by the ILM.

ILM4

ILM3

ILM2

ILM1

ILM0

Interruption level

Strength

Strong

Weak

MB91110 Series

MULTI-PURPOSE REGISTERS

The multi-purpose registers are CPU registers (R0 to R15) which are used as accumulators for various compu-
tations and memory access pointers (field that indicates the address) .

Special purposes are assumed for the following three registers out of the 16 registers. Thus, some instructions
are emphasized.

R13 : Virtual accumulator (AC)

R14 : Frame Pointer (FP)

R15 : Stack Pointer (SP)

Initial values for R0 to R14 on resetting are unspecified. The initial value of R15 will be 0000 0000

(SSP value) .

ˇ Register bank configuration

R12

R13

R14

R15

AC (Accumulator)

FP (Frame Pointer)

SP (Stack Pointer)

XXXX XXXX

0000 0000

32-bit

Initial value

MB91110 Series

MODE SETTING

Pins

ˇ Mode pins and set mode

* : MB91110 series is not supported single chip mode.

Register

ˇ Mode register (MODR) and set mode

ˇ Bus mode set bit and its functions

Mode pins

Mode name

Reset vector

access areas

External data bus

width

Bus modes

MD2

MD1

MD0

External vector

mode 0

External

8-bit

External ROM external
bus mode

External vector

mode 1

External

16-bit

Setting is prohibited

Internal vector

mode

Internal

(Mode register)

Single chip mode*

Usage is prohibited

Functions

Remarks

Single chip mode

Not supported

Internal ROM external bus mode

Not supported

External ROM external bus mode

Setting is prohibited

Address

Initial value

Access

0000 07FF

XXXXXXXX

Bus mode set bit

W : Write only

X : Undecided

* : "0" should always be written for bits other than M1 and M0.

MB91110 Series

I/O MAP

(Continued)

Address

Register

Internal resource

+
+
+
+

000000

PDR2

(R/W)

Port data register

XXXXXXXX

000004

PDR6

(R/W)

XXXXXXXX

000008

PDRB

(R/W)

PDRA

(R/W)

PDR8

(R/W)

XXXXXXXX

XXXXXX

XXX

00000C

000010

PDRE

(R/W)

PDRF

(R/W)

XXXX

XXXXXXXX

000014

PDRG

(R/W)

PDRH

(R/W)

PDRI

(R/W)

XXXXXX

XXXXXXXX

000018

Reserved

00001C

Reserved

000020

SSR

(R/W)

SIDR/SODR (R/W)

SCR

(R/W)

SMR

(R/W)

UART

XXXXXXXX

000024

CDCR

(R/W)

0 - - 1 1 1 1 1

000028

TMRLR

(W)

TMR

(R)

Reload timer 0

XXXXXXXX XXXXXXXX

00002C

TMCSR

(R/W)

0 0

000030

TMRLR

(W)

TMR

(R)

Reload timer 1

XXXXXXXX XXXXXXXX

000034

TMCSR

(R/W)

0 0

000038

ADCR

(R)

ADCS

(R/W)

A/D converter
(Sequential
comparison type)

- -

- XX XXXXXXXX

0 0

00003C

Reserved

MB91110 Series

(Continued)

Address

Register

Internal resource

+
+
+
+

000040

Reserved

000044

Access is prohibited

PCSR

(W)

PPG0

XXXXXXXX XXXXXXXX

000048

PDUT

(W)

PCNH

(R/W)

PCNL

(R/W)

XXXXXXXX XXXXXXXX

00004C

Access is prohibited

PCSR

(W)

PPG1

XXXXXXXX XXXXXXXX

000050

PDUT

(W)

PCNH

(R/W)

PCNL

(R/W)

XXXXXXXX XXXXXXXX

000054

Access is prohibited

PCSR

(W)

PPG2

XXXXXXXX XXXXXXXX

000058

PDUT

(W)

PCNH

(R/W)

PCNL

(R/W)

XXXXXXXX XXXXXXXX

00005C

Access is prohibited

PCSR

(W)

PPG3

XXXXXXXX

000060

PDUT

(W)

PCNH

(R/W)

PCNL

(R/W)

XXXXXXXX XXXXXXXX

000064

Access is prohibited

PCSR

(W)

PPG4

XXXXXXXX XXXXXXXX

000068

PDUT

(W)

PCNH

(R/W)

PCNL

(R/W)

XXXXXXXX XXXXXXXX

00006C

Access is prohibited

PCSR

(W)

PPG5

XXXXXXXX XXXXXXXX

000070

PDUT

(W)

PCNH

(R/W)

PCNL

(R/W)

XXXXXXXX XXXXXXXX

000074

Reserved

000078

00007C

000080

MB91110 Series

(Continued)

Address

Register

Internal resource

+
+
+
+

0000C8

Reserved

0000CC

0000D0

DDRE

(W)

DDRF

(W)

Data direction
register

0000D4

DDRG

(W)

DDRH

(W)

DDRI

(W)

0000D8

0000FC

Reserved

000100

0001FC

Reserved

000200

DMACS0

(R/W)

DMA controller
channel 0

0 -

000204

DMACC0

(R/W)

- - - - XXXX

XXXX - XXX

XXXXXXXX

000208

DMASA0

(R/W)

XXXXXXXX

00020C

DMADA0

(R/W)

XXXXXXXX

000210

DMACS1

(R/W)

DMA controller
channel 1

0 -

000214

DMACC1

(R/W)

XXXX

XXX

XXXXXXXX

000218

DMASA1

(R/W)

XXXXXXXX

00021C

DMADA1

(R/W)

XXXXXXXX

MB91110 Series

(Continued)

Address

Register

Internal resource

+
+
+
+

000220

DMACS2

(R/W)

DMA controller
channel 2

000224

DMACC2

(R/W)

XXXX

XXX

XXXXXXXX

000228

DMASA2

(R/W)

XXXXXXXX

00022C

DMADA2

(R/W)

XXXXXXXX

000230

DMACS3

(R/W)

DMA controller
channel 3

0 -

000234

DMACC3

(R/W)

XXXX

XXX

XXXXXXXX

000238

DMASA3

(R/W)

XXXXXXXX

00023C

DMADA3

(R/W)

XXXXXXXX

000240

DMACS4

(R/W)

DMA controller
channel 4

0 -

000244

DMACC4

(R/W)

XXXX

XXX

XXXXXXXX

000248

DMASA4

(R/W)

XXXXXXXX

00024C

DMADA4

(R/W)

XXXXXXXX

000250

DMACR

(R/W)

Overall DMA
controller

- - - - - - - -

0 0 - - - - - -

- - - - - - - 0

000254

Reserved

000258

00025C

000260

MB91110 Series

(Continued)

Address

Register

Internal resource

+
+
+
+

000264

Reserved

000268

00026C

000270

000274

000278

0002FC

000300

0003E0

0003E4

ICHCR

(R/W)

Instruction cache

0 0 0 0 0 0

0003E8

Reserved

0003EC

IRMC

(R/W)

I-RAM control

0003F0

BSD0

(W)

Bit search module

XXXXXXXX

0003F4

BSD1

(R/W)

XXXXXXXX

0003F8

BSDC

(W)

XXXXXXXX

0003FC

BSRR

(R)

XXXXXXXX

000400

ICR00

(R/W)

ICR01

(R/W)

ICR02

(R/W)

ICR03

(R/W)

Interruption controller

000404

ICR04

(R/W)

ICR05

(R/W)

ICR06

(R/W)

ICR07

(R/W)

MB91110 Series

(Continued)

Address

Register

Internal resource

+
+
+
+

000408

ICR08

(R/W)

ICR09

(R/W)

ICR10

(R/W)

ICR11

(R/W)

Interruption controller

00040C

ICR12

(R/W)

ICR13

(R/W)

ICR14

(R/W)

ICR15

(R/W)

000410

ICR16

(R/W)

ICR17

(R/W)

ICR18

(R/W)

ICR19

(R/W)

000414

ICR20

(R/W)

ICR21

(R/W)

ICR22

(R/W)

ICR23

(R/W)

000418

ICR24

(R/W)

ICR25

(R/W)

ICR26

(R/W)

ICR27

(R/W)

00041C

ICR28

(R/W)

ICR29

(R/W)

ICR30

(R/W)

ICR31

(R/W)

000420

ICR32

(R/W)

ICR33

(R/W)

ICR34

(R/W)

ICR35

(R/W)

000424

ICR36

(R/W)

ICR37

(R/W)

ICR38

(R/W)

ICR39

(R/W)

000428

ICR40

(R/W)

ICR41

(R/W)

ICR42

(R/W)

ICR43

(R/W)

00042C

ICR44

(R/W)

ICR45

(R/W)

ICR46

(R/W)

ICR47

(R/W)

000430

DICR

(R/W)

HRCL

(R/W)

Delay interruption

000434

00047C

Reserved

000480

RSRR/WTCR (R/W)

STCR

(R/W)

PDRR

(R/W)

CTBR

(W)

Clock control area

1 XXXX

0 0

0 0 0 1 1 1

0 0 0 0

XXXXXXXX

000484

GCR

(R/W)

WPR

(W)

1 1 0 0 1 1

XXXXXXXX

000488

PCTR

(R/W)

PLL control register

0 0

00048C

0005FC

Reserved

MB91110 Series

(Continued)

Note : Do not execute RMW instructions to registers with write-only bits.

RMW instruction (RMW : Read / Modify / Write)

Data in areas with "

" or reserved ones is undecided.

Address

Register

Internal resource

+
+
+
+

000600

DDR2

(W)

Data direction
register

000604

DDR6

(W)

000608

DDRB

(W)

DDRA

(W)

DDR8

(W)

00060C

ASR1

(W)

AMR1

(W)

External bus
interface

000610

ASR2

(W)

AMR2

(W)

000614

ASR3

(W)

AMR3

(W)

000618

ASR4

(W)

AMR4

(W)

00061C

ASR5

(W)

AMR5

(W)

000620

AMD0

(R/W)

AMD1

(R/W) AMD32

(R/W)

AMD4

(R/W)

000624

AMD5

(R/W)

DSCR

(W)

RFCR

(R/W)

XXXXXX

000628

EPCR0

(W)

EPCR1

(W)

- - - - - - - -

00062C

DMCR4

(R/W)

DMCR5

(R/W)

000630

0007F8

Reserved

0007FC

LER

(W)

MODR

(W)

"Little endian" register
Mode register

XXXXXXXX

AND

Rj, @Ri

EOR

Rj, @Ri

ANDH

Rj, @Ri

ORH

Rj, @Ri

EORH

Rj, @Ri

ANDB

Rj, @Ri

ORB

Rj, @Ri

EORB

Rj, @Ri

BANDL

#u4, @Ri

BORL #u4, @Ri

BEORL

#u4, @Ri

BANDH

#u4, @Ri

BORH #u4, @Ri

BEORH

#u4, @Ri

MB91110 Series

INTERRUPTION VECTOR

Interruption factor and allocation of interruption vectors / interruption control registers are described in the
interruption vector table.

(Continued)

Interruption source

Interruption number

Interruption

level

Offset

Interruption vector

address to TBR of

default

Decimal

Hexadeci-

mal

Reset

3FC

000FFFFC

System reservation

3F8

000FFFF8

System reservation

3F4

000FFFF4

System reservation

3F0

000FFFF0

System reservation

3EC

000FFFEC

System reservation

3E8

000FFFE8

System reservation

3E4

000FFFE4

Coprocessor absence trap

3E0

000FFFE0

Coprocessor error trap

3DC

000FFFDC

INTE instruction

4 fixed

3D8

000FFFD8

System reservation

3D4

000FFFD4

System reservation

3D0

000FFFD0

Step trace trap

4 fixed

3CC

000FFFCC

System reservation

3C8

000FFFC8

Exceptions to undefined instructions

3C4

000FFFC4

NMI request

15 (F

) fixed

3C0

000FFFC0

System reservation

ICR00

3BC

000FFFBC

System reservation

ICR01

3B8

000FFFB8

External interruption 0

ICR02

3B4

000FFFB4

External interruption 1

ICR03

3B0

000FFFB0

External interruption 2

ICR04

3AC

000FFFAC

External interruption 3

ICR05

3A8

000FFFA8

External interruption 4

ICR06

3A4

000FFFA4

External interruption 5

ICR07

3A0

000FFFA0

External interruption 6

ICR08

39C

000FFF9C

External interruption 7

ICR09

398

000FFF98

System reservation

ICR10

394

000FFF94

UART reception completion

ICR11

390

000FFF90

System reservation

ICR12

38C

000FFF8C

System reservation

ICR13

388

000FFF88

UART transmission completion

ICR14

384

000FFF84

System reservation

ICR15

380

000FFF80

MB91110 Series

(Continued)

Interruption source

Interruption number

Interruption

level

Offset

Interruption vector

address to TBR of

default

Decimal

Hexadeci-

mal

System reservation

ICR16

37C

000FFF7C

DMAC0 (end, error)

ICR17

378

000FFF78

DMAC1 (end, error)

ICR18

374

000FFF74

DMAC2 (end, error)

ICR19

370

000FFF70

DMAC3 (end, error)

ICR20

36C

000FFF6C

DMAC4 (end, error)

ICR21

368

000FFF68

System reservation

ICR22

364

000FFF64

System reservation

ICR23

360

000FFF60

System reservation

ICR24

35C

000FFF5C

A/D sequential conversion type

ICR25

358

000FFF58

Reload timer 0

ICR26

354

000FFF54

Reload timer 1

ICR27

350

000FFF50

16-bit PPG timer 0

ICR28

34C

000FFF4C

16-bit PPG timer 1

ICR29

348

000FFF48

16-bit PPG timer 2

ICR30

344

000FFF44

16-bit PPG timer 3

ICR31

340

000FFF40

16-bit PPG timer 4

ICR32

33C

000FFF3C

16-bit PPG timer 5

ICR33

338

000FFF38

System reservation

ICR34

334

000FFF34

System reservation

ICR35

330

000FFF30

System reservation

ICR36

32C

000FFF2C

System reservation

ICR37

328

000FFF28

System reservation

ICR38

324

000FFF24

System reservation

ICR39

320

000FFF20

System reservation

ICR40

31C

000FFF1C

System reservation

ICR41

318

000FFF18

System reservation

ICR42

314

000FFF14

System reservation

ICR43

310

000FFF10

System reservation

ICR44

30C

000FFF0C

System reservation

ICR45

308

000FFF08

System reservation

ICR46

304

000FFF04

Delay interruption factor bit

ICR47

300

000FFF00

System reservation
(used under REALOS)

2FC

000FFEFC

MB91110 Series

(Continued)

*1 : ICR sets the interruption level for each interruption request using the register built into the interruption controller.

ICR is prepared in accordance with each interruption request.

*2 : TBR is the register that indicates the starting address of the vector table for EIT.

Addresses with added offset values that are specified per TBR and EIT factor will be the vector addresses.

*3 : REALOS OS/FR uses 0X40, 0X41 interruptions for system codes.

Reference :

The vector area for EIT is 1 KB in accordance with the address shown by TBR.
The size per vector is 4 bytes, and the relationship between the vector numbers and their addresses is shown
as follows.

Interruption source

Interruption number

Interruption

level

Offset

Interruption vector

address to TBR of

default

Decimal

Hexadeci-

mal

System reservation
(used under REALOS)

2F8

000FFEF8

Used under INT instruction

66
to

255

42
to

2F4

000

000FFEF4

000FFD00

vctadr

TBR

vctofs

TBR

(3FC

vct)

vctadr : vector address

vctofs : vector offset

vct : vector number

MB91110 Series

PERIPHERAL RESOURCES

I/O Port

MB91110 series can be used as the I/O port when settings for resources that handle each pin do not to use the
pins for input/output.

ˇ Block diagram

ˇ I/O Port Registers

I/O port is composed of the Port Data Register (PDR) and Data Direction Register (DDR) .

In cases where the input mode is DDR

"0"

For PDR reading : Level of external pins to be handled is read out.

For PDR writing : Set value is written in PDR.

In cases where the output mode is DDR

"1"

For PDR reading : PDR value is read out.

For PDR writing : Set value is written in PDR and the PDR value is simultaneously output to the

externally handled pin.

PDR

DDR

Data Bus

PDR read

PDR

Port Data Register

DDR

Data Direction Register

Resource input

Resource

output

Resource output
allowed

MB91110 Series

Port Data Register (PDR)

Port Data Register (PDR2-I) is the input/output data register for the I/O port.

Input/output control is carried out by the handled data direction register (DDR2-I) .

ˇ Port Data Register (PDR)

PDR2

Initial value

Access

Address : 000001

XXXXXXXX

R/W

PDR6

Initial value

Access

Address : 000005

XXXXXXXX

R/W

PDR8

Initial value

Access

Address : 00000B

- - X- - XXX

R/W

PDRA

Initial value

Access

Address : 000009

- XXXXXX-

R/W

PDRB

Initial value

Access

Address : 000008

XXXXXXXX

R/W

PDRE

Initial value

Access

Address : 000012

- - - - XXXX

R/W

PDRF

Initial value

Access

Address : 000013

XXXXXXXX

R/W

PDRG

Initial value

Access

Address : 000014

- - XXXXXX

R/W

PDRH

Initial value

Access

Address : 000015

XXXXXXXX

R/W

PDRI

Initial value

Access

Address : 000016

XXXXXXXX

R/W

P26

P27

P25

P24

P23

P22

P21

P20

P66

P67

P65

P64

P63

P62

P61

P60

P85

P82

P81

P80

PA6

PA5

PA4

PA3

PA2

PA1

PB6

PB7

PB5

PB4

PB3

PB2

PB1

PB0

PE3

PE2

PE1

PE0

PF6

PF7

PF5

PF4

PF3

PF2

PF1

PF0

PG5

PG4

PG3

PG2

PG1

PG0

PH6

PH7

PH5

PH4

PH3

PH2

PH1

PH0

PI6

PI7

PI5

PI4

PI3

PI2

PI1

PI0

MB91110 Series

Data Direction Register (DDR)

The Data Direction Register (DDR2-I) controls the input/output direction of the I/O port per bit.
0 is used for input and 1 is used to execute output control.

ˇ Data Direction Register (DDR)

DDR2

Initial value Access

Address : 000601

00000000

DDR6

Initial value Access

Address : 000605

00000000

DDR8

Initial value Access

Address : 00060B

- - 0 - - 000

DDRA

Initial value Access

Address : 000609

- 000000 -

DDRB

Initial value Access

Address : 000608

00000000

DDRE

Initial value Access

Address : 0000D2

- - - - 0000

DDRF

Initial value Access

Address : 0000D3

00000000

DDRG

Initial value Access

Address : 0000D4

- - 000000

DDRH

Initial value Access

Address : 0000D5

00000000

DDRI

Initial value Access

Address : 0000D6

00000000

P26

P27

P25

P24

P23

P22

P21

P20

P66

P67

P65

P64

P63

P62

P61

P60

P85

P82

P81

P80

PA6

PA5

PA4

PA3

PA2

PA1

PB6

PB7

PB5

PB4

PB3

PB2

PB1

PB0

PE3

PE2

PE1

PE0

PF6

PF7

PF5

PF4

PF3

PF2

PF1

PF0

PG5

PG4

PG3

PG2

PG1

PG0

PH6

PH7

PH5

PH4

PH3

PH2

PH1

PH0

PI6

PI7

PI5

PI4

PI3

PI2

PI1

PI0

MB91110 Series

Instruction Cache

The instruction cache is a temporary storage memory. In the event that the instruction codes are accessed from
a low speed external memory, it holds the accessed codes internally, and is used to increase the access speed
for all subsequent accesses.

Direct read or write access can not be done by instruction cache or instruction cache tag using software.

ˇ Cacheable area of the instruction cache

Instruction cache allows all space to become a cacheable area.
ˇ Even though details of the external memory are updated by DMA transfer, it is not coherent with the cache

details. In this case, coherency should be established by flushing the cache.

ˇ Instruction cache configuration
ˇ Basic instruction length of FR series : 2 bytes
ˇ Block layout : 2-way set associative type
ˇ Block

1 way is configured of 32 blocks.
1 block is 16 bytes (

4 sub blocks)

1 sub block is 4 bytes (

1 bus access unit)

The instruction cache configuration is shown in the following figure.

4 bytes

Way 1

Way 2

Cache tag

Sub lock 3

Sub lock 2

Sub lock 1

Sub lock 0

Block 0

Sub lock 3

Sub lock 2

Sub lock 1

Sub lock 0

Block 31

Block 0

Block 31

Sub lock 3

Sub lock 2

Sub lock 1

Sub lock 0

Sub lock 3

Sub lock 2

Sub lock 1

Sub lock 0

Cache tag

32 blocks

Instruction Cache Configuration

MB91110 Series

Clock Generator (Low power consumption mechanism)

The clock generation area is a module with the following functions.
ˇ CPU clock generation (including gear function)
ˇ Peripheral clock generation (including gear function)
ˇ Reset generation and holding factors
ˇ Standby function (including hardware standby)
ˇ Restraining DMA request
ˇ PLL (Phase Locked Loop) is built in

ˇ Register list

Address

Initial value Access

000480

000481

1XXXX- 00

000111 - -

R/W
R/W

000482

000483

- - - - 0000

XXXXXXXX

R/W

000484

000485

110011- 1

XXXXXXXX

R/W

000488

00 - - 0 - - -

R/W

STCR

CTBR

RSRR/WTCR

PDRR

WPR

GCR

PCTR

MB91110 Series

ˇ Block diagram

X0
X1

1/2

PLL

B
U
S

[ Gear control area ]

GCR register

PCTR register

CPU gear

Peripheral

gear

[ Stop/sleep control area ]

STCR register

[ DMA blocking circuit ]

PDRR register

[ Reset factor circuit ]

RSRR register

[ Watchdog control area ]

WPP register

CTBR register

Selection

circuit

Internal

clock

generation

circuit

Status

transfer

control

circuit

Watchdog F/F

Time base timer

Oscilla-

tion

circuit

Internal

interruption

Internal reset

CPU hold

Permission

HST pin

DMA request

Power on cell

RST pin

CPU clock

Internal

bus clock
External

bus clock
Peripheral

DMA clock

Internal

peripheral clock

STOP status

SLEEP status

CPU hold request

Internal reset

Reset

generation

F/F

Count

clock

MB91110 Series

Bus Interface Outline

The bus interface controls the interface with external memory and external I/O.

ˇ Bus Interface Characteristics
ˇ 24-bit (16 MB) address output
ˇ 6 individual banks using chip selection function

Random positional setting is possible on the logical address space at minimum 64-KB units.
Total 16 MB

6 areas can be set using the address pin and chip selection pin.

ˇ 16/8-bit bus width can be set per chip selection area.
ˇ Insertion of programmable "automatic memory wait" (maximum of 7 cycles)
ˇ Supports DRAM interface

3 types of DRAM interface

Double CAS DRAM (Normal DRAM I/F)
Single CAS DRAM
Hyper DRAM

2-bank individual control (control signal i.e. RAS and CAS)
DRAM can be selected from 2CAS/1WE or 1CAS/2WE.
Supports high-speed page mode
Supports CBR / self refresh
Programmable corrugation

ˇ Unused addresses / data pins can be used as I/O ports.
ˇ Supports "little endian" mode
ˇ Using clock doubler : Internal 50 MHz, external bus 25 MHz operation

ˇ Chip Selection Area

A total of six types of chip selection areas are prepared for the bus interface. The position of each area can be
randomly arranged per 64 KB at least using area selection registers (ASR1 to 5) and area mask registers (AMR1
to 5) in an area of 4 GB. In the event that access to an external bus is attempted in areas that are specified by
those registers, the supported chip selection signals (CS0 to CS5) become activated to "L". Such pins other
than CS0 are deactivated to "H" when reset.

Note : The area 0 is allocated to space outside the area specified by ASR1 to ASR5. External areas other than

0001 0000

to 0005 FFFF

are deemed area 0 on resetting.

MB91110 Series

ˇ Interface

The bus interface has the following interface types.
ˇ Normal bus interface
ˇ DRAM interface

These interfaces can only be used in predetermined areas. The following table shows each chip selection area
and the usable interface functions.Which interface is to be used is selected in the Area Mode Register (AMD) .
If no selection is made, it defaults to the normal bus interface.

Chip Selection Area and Selectable Bus Interfaces

ˇ Block Diagram

Areas

Selectable bus interface

Remarks

Normal bus

Time division

DRAM

On resetting

A-OUT

MUX

inpage

CS0

CS5

RAS0, RAS1
CS0L, CS1L
CS0H, CS1H
DW0, DW1

RD
WR0, WR1

BRQ
BGRNT
CLK
RDY

ADDRESS BUS DATA BUS

write buffer

read buffer

switch

EXTERNAL
DATA BUS

1or

address buffer

ASR
AMR

shifter

comparator

DATA BLOCK

ADDRESS BLOCK

EXTERNAL
ADDRESS BUS

DRAM control

underflow

DMCR

from TBT

refresh counter

External pin control area

Controls all blocks

registers & control

MB91110 Series

ˇ Register List

*1 : AMD (Area MoDe register)
*2 : DSCR (DRAM Signal Control Register)
*3 : LER (Little Endian Register)
*4 : MODR (MODe Register)

Address

Initial value

Access

00060C

00060E

00000000

00000001

00000000

W
W

000610

000612

00000000

00000010

00000000

W
W

000614

000616

00000000

00000011

00000000

W
W

000618

00061A

00000000

00000100

00000000

W
W

00061C

00061E

00000000

00000101

00000000

W
W

000620

000622

- - - 00111

0- - 00000

00000000

0- - 00000

R/W
R/W

000624

000626

0- - 00000

00000000

- -XXXXXX

0- - - 0000

R/W
R/W

000628

00062A

- - - - 1100

- 0000000

- - - - - - - -

11111111

W
W

00062C

00062E

00000000

0000000-

00000000

0000000-

R/W
R/W

0007FC

- - - - - - 00

XXXXXXXX

AMR1 (Area Mode Reg. 1)

AMR2 (Area Mode Reg. 2)

ASR1 (Area Select Reg. 1)

ASR2 (Area Select Reg. 2)

AMR3 (Area Mode Reg. 3)

ASR3 (Area Select Reg. 3)

AMR4 (Area Mode Reg. 4)

AMR5 (Area Mode Reg. 5)

ASR4 (Area Select Reg. 4)

ASR5 (Area Select Reg. 5)

RFCR (Refresh Control Register)

EPCR1 (External Pin Control 1)

EPCR0 (External Pin Control 0)

DMCR5 (DRAM Control Reg. 5)

DMCR4 (DRAM Control Reg. 4)

LER *

MODR *

AMD32 *

AMD4 *

AMD0 *

AMD1 *

AMD5 *

DSCR *

8 7

24 23

MB91110 Series

16-bit Reload Timer

The 16-bit timer is composed of a 16-bit down counter, 16-bit reload register, a pre-scalar for internal count clock
preparation and a control register. Selection of the input clock can be made from three types of internal clock
(machine clocks with 2, 8 and 32 cycles) and an external clock are selectable for input clock.

ˇ Characteristics of the 16-bit reload timer

The Pin Output (TO) outputs a toggle waveform whenever underflow is generated in reload mode, and outputs
rectangular waves indicating that it is counting in the case of one shot mode.

Pin Input (TI) can be used for event input in the case of external event count mode, trigger input or gate input
for internal clock mode.

If the external event count function is used as the reload mode, it can be used as the cycle device for the external
clock.

In this type, a 2-channel timer is built-in.

Channel 0 of the reload timer can start up DMA transfer using the interruption request signal.

The DMA controller clears the interruption flag of the reload timer at the same time as receiving the transfer
request.

The TO output from channel 0 for the reload timer is connected to the A/D converter inside the LSI. Thus, A/D
conversion can be started on a cycle set at the reload register.

MB91110 Series

ˇ Block Diagram

ˇ Register List

RELD

OUTE

OUTL

INTE

CNTE

TRG

OUT
CTL.

CSL1

CSL0

MOD2

MOD1

MOD0

IN CTL.

EXCK

GATE

IRQ

B
U
S

16-bit reload register

Reload

16-bit down counter

Clock selector

Re-
trigger

Port (TI)

Port (TO)

Pre-scalar
Clear

Internal clock

ˇ Control status register (TMCSR)

ˇ 16-bit timer register (TMR)

ˇ 16-bit reload register (TMRLR)

Address

Initial value

Access

000036

- - - - 0000

R/W

000037

00000000

R/W

Address

Initial value

Access

00002A

000032

XXXXXXXX

Address

Initial value

Access

000028

000030

XXXXXXXX

CSL1

CSL0

MOD2

MOD1

OUTE

MOD0

OUTL

RELD

INTE

CNTE

TRG

MB91110 Series

PPG Timer

The PPG timer can output pulses that are synchronized with soft triggers or externally. Also, the cycle and duty
of the output pulses can be changed randomly by replacing the two 16-bit register values. In this type, there
are 6 built-in channels with this function.

ˇ PPG timer function

The PPG timer has two functions as follows.
ˇ PWM function

This can be synchronized to the trigger and is programmable to output pulses while rewriting the above register
values. It can also be used as a D/A converter by using an additional circuit.

ˇ One-shot function

This detects the edge of the trigger input and outputs a single pulse.

ˇ Block Diagram

/ 2

/ 8

/ 32

/ 128

PCSR

PDUT

cmp

IRQ

Pre-scalar

Load

16-bit Down counter

Start

Borrow

PPG mask

PPG output

Reverse bit

Enable

TRG input
(only channels 0 to 2)

Edge

detection

Soft trigger

Interrup-

tion

selection

MB91110 Series

10. External Interruption/NMI Control Area

The external interruption / NMI control area controls the external interruption requests to be input to the NMI
and INT0 to INT7. "H" or "L" and "rising edge" or "falling edge" can be selected as the requested detection level
(except for NMI) . Also, four requests from INT0 to INT3 can be used as the DMA request.

ˇ Block diagram

ˇ Register list

INT0

INT7

NMI

R BUS

Interruption
requests

Interruption permission register

Gate

Factor F/F

Edge detection

circuit

Interruption factor register

Request level setting register

ˇ External interruption permission register (ENIR)

ˇ External interruption factors register (EIRR)

ˇ Request level setting register (ELVR)

Address

bit

Initial value Access

000095

00000000

R/W

Address

bit

000094

00000000

R/W

Address

bit

000098

00000000

R/W

bit

000099

00000000

R/W

EN6

EN7

EN5

EN4

EN3

EN2

EN1

EN0

ER6

ER7

ER5

ER4

ER3

ER2

ER1

ER0

LA7

LB7

LB6

LA6

LB5

LA5

LB4

LA4

LA3

LB3

LB2

LA2

LB1

LA1

LB0

LA0

MB91110 Series

12. Interruption Controller

The interruption controller carries out interruption reception and arbitration.

ˇ Hardware configuration of the interruption controller

This module is configured for the following items.
ˇ ICR register
ˇ Interruption priority judgement circuit
ˇ Interruption level, interruption number (vector) generation area
ˇ Cancellation request generation area for HOLD request

ˇ Major interruption controller functions

This module has the following functions.
ˇ Detection of NMI request / interruption request
ˇ Priority grade judgement (depending on the level and number)
ˇ Transferring interruption level of factors for the judgement results (to CPU)
ˇ Transferring interruption number of factors for the judgement results (to CPU)
ˇ Recovery instruction from stop mode by generating NMI / interruption
ˇ Cancellation of HOLD request to the bus master

MB91110 Series

ˇ Register list

Address

bit

Initial value

Acces

000400

ICR4 ICR3 ICR2 ICR1 ICR0

ICR00

- - - 11111

R/W

000401

ICR4 ICR3 ICR2 ICR1 ICR0

ICR01

- - - 11111

R/W

000402

ICR4 ICR3 ICR2 ICR1 ICR0

ICR02

- - - 11111

R/W

000403

ICR4 ICR3 ICR2 ICR1 ICR0

ICR03

- - - 11111

R/W

000404

ICR4 ICR3 ICR2 ICR1 ICR0

ICR04

- - - 11111

R/W

000405

ICR4 ICR3 ICR2 ICR1 ICR0

ICR05

- - - 11111

R/W

000406

ICR4 ICR3 ICR2 ICR1 ICR0

ICR06

- - - 11111

R/W

000407

ICR4 ICR3 ICR2 ICR1 ICR0

ICR07

- - - 11111

R/W

000408

ICR4 ICR3 ICR2 ICR1 ICR0

ICR08

- - - 11111

R/W

000409

ICR4 ICR3 ICR2 ICR1 ICR0

ICR09

- - - 11111

R/W

00040A

ICR4 ICR3 ICR2 ICR1 ICR0

ICR10

- - - 11111

R/W

00040B

ICR4 ICR3 ICR2 ICR1 ICR0

ICR11

- - - 11111

R/W

00040C

ICR4 ICR3 ICR2 ICR1 ICR0

ICR12

- - - 11111

R/W

00040D

ICR4 ICR3 ICR2 ICR1 ICR0

ICR13

- - - 11111

R/W

00040E

ICR4 ICR3 ICR2 ICR1 ICR0

ICR14

- - - 11111

R/W

00040F

ICR4 ICR3 ICR2 ICR1 ICR0

ICR15

- - - 11111

R/W

000410

ICR4 ICR3 ICR2 ICR1 ICR0

ICR16

- - - 11111

R/W

000411

ICR4 ICR3 ICR2 ICR1 ICR0

ICR17

- - - 11111

R/W

000412

ICR4 ICR3 ICR2 ICR1 ICR0

ICR18

- - - 11111

R/W

000413

ICR4 ICR3 ICR2 ICR1 ICR0

ICR19

- - - 11111

R/W

000414

ICR4 ICR3 ICR2 ICR1 ICR0

ICR20

- - - 11111

R/W

000415

ICR4 ICR3 ICR2 ICR1 ICR0

ICR21

- - - 11111

R/W

000416

ICR4 ICR3 ICR2 ICR1 ICR0

ICR22

- - - 11111

R/W

000417

ICR4 ICR3 ICR2 ICR1 ICR0

ICR23

- - - 11111

R/W

000418

ICR4 ICR3 ICR2 ICR1 ICR0

ICR24

- - - 11111

R/W

000419

ICR4 ICR3 ICR2 ICR1 ICR0

ICR25

- - - 11111

R/W

00041A

ICR4 ICR3 ICR2 ICR1 ICR0

ICR26

- - - 11111

R/W

00041B

ICR4 ICR3 ICR2 ICR1 ICR0

ICR27

- - - 11111

R/W

00041C

ICR4 ICR3 ICR2 ICR1 ICR0

ICR28

- - - 11111

R/W

00041D

ICR4 ICR3 ICR2 ICR1 ICR0

ICR29

- - - 11111

R/W

00041E

ICR4 ICR3 ICR2 ICR1 ICR0

ICR30

- - - 11111

R/W

00041F

ICR4 ICR3 ICR2 ICR1 ICR0

ICR31

- - - 11111

R/W

000420

ICR4 ICR3 ICR2 ICR1 ICR0

ICR32

- - - 11111

R/W

000421

ICR4 ICR3 ICR2 ICR1 ICR0

ICR33

- - - 11111

R/W

000422

ICR4 ICR3 ICR2 ICR1 ICR0

ICR34

- - - 11111

R/W

000423

ICR4 ICR3 ICR2 ICR1 ICR0

ICR35

- - - 11111

R/W

000424

ICR4 ICR3 ICR2 ICR1 ICR0

ICR36

- - - 11111

R/W

000425

ICR4 ICR3 ICR2 ICR1 ICR0

ICR37

- - - 11111

R/W

000426

ICR4 ICR3 ICR2 ICR1 ICR0

ICR38

- - - 11111

R/W

000427

ICR4 ICR3 ICR2 ICR1 ICR0

ICR39

- - - 11111

R/W

000428

ICR4 ICR3 ICR2 ICR1 ICR0

ICR40

- - - 11111

R/W

000429

ICR4 ICR3 ICR2 ICR1 ICR0

ICR41

- - - 11111

R/W

00042A

ICR4 ICR3 ICR2 ICR1 ICR0

ICR42

- - - 11111

R/W

00042B

ICR4 ICR3 ICR2 ICR1 ICR0

ICR43

- - - 11111

R/W

00042C

ICR4 ICR3 ICR2 ICR1 ICR0

ICR44

- - - 11111

R/W

00042D

ICR4 ICR3 ICR2 ICR1 ICR0

ICR45

- - - 11111

R/W

00042E

ICR4 ICR3 ICR2 ICR1 ICR0

ICR46

- - - 11111

R/W

00042F

ICR4 ICR3 ICR2 ICR1 ICR0

ICR47

- - - 11111

R/W

000431

LVL4

LVL3

LVL2

LVL1

LVL0

HRCL

- - - 11111

R/W

MB91110 Series

13. Interruption Control Register (ICR)

This function is set up per interruption input and sets the interruption level of interruption requests to be handled.

ˇ Register list

[bit 4 to 0] ICR4 to 0

The interruption level of the interruption requests that are handled is specified by the interruption level setting
bit. In cases where the interruption level that is set in this register is the same as or more than the level mask
value that is set (has been set) in the ILM register of the CPU, the interruption request is masked at the CPU
side. It is initialized to 11111

on resetting. The settable interruption level setting bit and interruption level are

shown in following Table.

Interruption Level Setting Bit and Interruption Level

Note: ICR 4 is fixed as "1" and can not be written as "0".

ICR4

ICR3

ICR2

ICR1

ICR0

Interruption level

System reservation

NMI

Maximum settable level

(High)

(Low)

Interruption is prohibited

bit 7

R/W

ICR4

ICR3

ICR2

ICR1

R/W

ICR0

MB91110 Series

14. 10-bit A/D Converter

The A/D converter is the module that converts analog input voltages to a digital value.

ˇ Characteristics of A/D Converter
ˇ Minimum converting time : 5.6

s/channel

ˇ Sample & hold circuit is built-in.
ˇ Resolution : 10 bits
ˇ Selection can be made for analog input from 8 channels.

ˇ Initiation of DMA transfer by interruption is possible.
ˇ Initiation factor can be selected from software, external trigger (falling edge) or reload timer (rising edge) .

ˇ Block Diagram

Single conversion mode

: 1 channel is selected for conversion

Scan conversion mode

: Converts multiple number of consecutive channels.

Maximum 8 channels are programmable.

Consecutive conversion mode : Repeatedly converts the specified channel.

Suspension / conversion mode : Suspends after converting 1 channel and waits until the next one is

started up (synchronization for starting conversion is possible)

AVR

MPX

AN0

AN1

AN2

AN3

ATG

AN4

AN5

AN6

AN7

ADCR

ADCS

B
U
S

Input circuit

Internal voltage generator

Data register

A/D control register 1

Starting up External trigger

Sequential comparison

Sample & hold circuit

Comparator

Decoder

TIM0 (Internal connection)
(Reload timer channel 0)

Starting up timer

(Peripheral system clock)

Operation clock

Pre-scalar

MB91110 Series

ˇ Block Diagram

MD1
MD0
CS2
CS1
CS0

SCKE
SOE

PEN
P
SBL
CL
A

REC
RXE
TXE

PE
ORE
FRE
RDRF
TDRE

RIE
TIE

R - BUS

SIDR

SODR

SCK

Control signal

Dedicated baud
rate generator

16-bit reload timer
(internal connection)

External clock

Start bit

detection circuit

Reception bit

counter

Reception parity

counter

Clock selection

circuit

Reception status

judgement circuit

Reception error
generation signal
for DMA (to DMAC)

SMR

SCR

SSR

Reception clock

Reception

control circuit

Shifter for reception

Shifter for

transmission

End of
reception

Start
transmission

Reception interruption
(to CPU)

Transmission
interruption (to CPU)

Transmission clock

Transmission
control circuit

Transmission

starting circuit

Transmission

bit counter

Transmission

parity counter

MB91110 Series

ˇ Register List

ˇ Serial Mode Register (SMR)

ˇ Serial Control Register (SCR)

ˇ Serial Input Data Register/Serial Output Data Register (SIDR/SODR)

ˇ Serial Status Register (SSR)

ˇ Communication Pre-scalar Control Register (CDCR)

Address

bit

Initial value

Access

000023

00000 - 00

R/W

bit

Initial value

Access

000022

00000100

R/W

bit

Initial value

Access

000021

XXXXXXXX

R/W

bit

Initial value

Access

000020

00001 - 00

R/W

bit

Initial value

Access

000025

0 - - 11111

R/W

MD0

MD1

CS2

CS1

CS0

SCKE

SOE

PEN

SBL

A/D

REC

RXE

TXE

ORE

FRE

RDRF

TDRE

RIE

TIE

DIV4

DIV3

DIV2

DIV1

DIV0

MB91110 Series

16. DMA Controller (DMAC)

The DMA controller is the module to realize Direct Memory Access (DMA) transfers with FR 30 series devices.
DMA transfers controlled by this module enable quick and direct transfer of all data without using the CPU and
thus system performance is increased.

ˇ Hardware Configuration of DMA Controller

This module is mainly configured of the following items.
ˇ Internal I/O access control circuit
ˇ 32-bit address counters (possible reload specification : 10)
ˇ 16-bit transfer number counters (possible reload specification : 5)
ˇ External transfer request input pin : DREQ0, DREQ1, DREQ2
ˇ External transfer request reception output pin : DACK0, DACK1, DACK2 (external bus synchronization)
ˇ External transfer termination output pin : DEOP0, DEOP1, DEOP2 (external bus synchronization)

ˇ Major Function of DMA Controller

There are the following functions for data transfer using this module.
ˇ Independent data transfer of a number of channels is possible (5 ch)
ˇ Priority ranking amongst channels

Fixed ranking (ch.0

ch.1

ch.2

ch.3

ch.4)

Ranking between channel 0 and 1 can be reversed.

ˇ Transfer request

Dedicated external pin input (Edge detection / level detection selection are possible for channels 0 to 2 only.)
Built-in peripheral request (interruption requests are shared. External interruption is included.)
Software request (register writing)

ˇ Transfer sequence

Consecutive / burst transfer
Step transfer / block transfer (Maximum 16 words are settable.)

ˇ Addressing mode : 32-bit full address specification (increase / decrease / fix)
ˇ Data types : Byte, half word, word length
ˇ Single shot or reload can be selected.

MB91110 Series

ˇ Block Diagram

DREQ0
DREQ1
DREQ2

DACK0
DACK1
DACK2

DEOP0
DEOP1
DEOP2

ACK.

FR30 CPU

BUS

External transfer

request input

Detection / processing

External transfer
request

Transfer request

processing

Each channel request

Peripheral interruption
request
Peripheral interruption
request

Controls arbitration of
requests, priority
judgement and decision
on transferring channels

Transfer start
request

Channel
instruction

Hold control

Hold request

Transfer state

machine

(bus control)

End

Data control

External input

setting

Each channel

request setting

Each channel

transfer mode setting

Each channel

address generation

control

Address counter

Control counting

address /

the number of times

Counter of the number

of transfer times

Interruption

control

Address

of times

Input setting register

Request setting register

Mode setting register

Address control register

Address registers

No. of times registers

Data buffer

MB91110 Series

ˇ Register List

*: Shaded areas indicate where nothing exists.

Address

bit

Initial value

Access

000200

ch.0

Control

status register

DMACS0

0 0

0 0 0 0 0 -

0 0 0 0

0 0 0 0 0 -

R/W

000204

ch.0

Addressing/transfer counting register

DMACC0

XXXX XXXX

XXX

XXXXXXXX XXXXXXXX

R/W

000208

ch.0

Transfer originator address register

DMASA0

XXXXXXXX XXXXXXXX

R/W

00020C

ch.0

Destination address register

DMADA0

XXXXXXXX XXXXXXXX

R/W

000210

ch.1

Control

status register

DMACS1

0 0

0 0 0 0 0 -

0 0 0 0

0 0 0 0 0 -

R/W

000214

ch.1

Addressing/transfer counting register

DMACC1

XXXX XXXX

XXX

XXXXXXXX XXXXXXXX

R/W

000218

ch.1

Transfer originator address register

DMASA1

XXXXXXXX XXXXXXXX

R/W

00021C

ch.1

Destination address register

DMADA1

XXXXXXXX XXXXXXXX

R/W

000220

ch.2

Control

status register

DMACS2

0 0

0 0 0 0 0 -

0 0 0 0

0 0 0 0 0 -

R/W

000224

ch.2

Addressing/transfer counting register

DMACC2

XXXX XXXX

XXX

XXXXXXXX XXXXXXXX

R/W

000228

ch.2

Transfer originator address register

DMASA2

XXXXXXXX XXXXXXXX

R/W

00022C

ch.2

Destination address register

DMADA2

XXXXXXXX XXXXXXXX

R/W

000230

ch.3

Control

status register

DMACS3

0 0

0 0 0 0 0 -

0 0 0 0

0 0 0 0 0 -

R/W

000234

ch.3

Addressing/transfer counting register

DMACC3

XXXX XXXX

XXX

XXXXXXXX XXXXXXXX

R/W

000238

ch.3

Transfer originator address register

DMASA3

XXXXXXXX XXXXXXXX

R/W

00023C

ch.3

Destination address register

DMADA3

XXXXXXXX XXXXXXXX

R/W

000240

ch.4

Control

status register

DMACS4

0 0

0 0 0 0 0 -

0 0 0 0

0 0 0 0 0 -

R/W

000244

ch.4

Addressing/transfer counting register

DMACC4

XXXX XXXX

XXX

XXXXXXXX XXXXXXXX

R/W

000248

ch.4

Transfer originator address register

DMASA4

XXXXXXXX XXXXXXXX

R/W

00024C

ch.4

Destination address register

DMADA4

XXXXXXXX XXXXXXXX

R/W

000250

Overall control register

DMACR

0 0

- 0

R/W

MB91110 Series

17. Bit Search Module

Bit search module searches for 0, 1 or change points on data that has been written in the input register, and
returns the detected bit position.

ˇ Block Diagram

ˇ Registers List

18. I-RAM

This type has 16 KB of built-in I-RAM. Efficient processing becomes possible by pre-arranging interruption
processing programs and such like in this area. Writing on I-RAM is possible via the data bus and is available
as RAM for data.

ˇ Register List

D-BUS

Input latch

Address
decoder

Detection

mode

Changing to 1 detection data

Bit search circuit

Detection results

Address

Initial value

Access

0003F0

Data register for 0 detection

(BSD0)

XXXXXXXX XXXXXXX

0003F4

Data register for 1 detection

(BSD1)

XXXXXXXX XXXXXXX

R/W

0003F8

Data Register for Change Point Detection

(BSDC)

XXXXXXXX XXXXXXX

0003FC

Detection Results Register

(BSRR)

XXXXXXXX XXXXXXX

IRMC

Initial value Access

Address : 0003EF

- - - - - - - 0

R/W

IRMD

MB91110 Series

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

AVRL

0 V)

*1 : V

3/V

5 must not be lower than V

0.3 V.

*2 : Care must be taken that AV

, AVRH and AVRL do not exceed V

0.3 V when the power is turned on.

Also care must be taken that AVRH and AVRL do not exceed AV

, and keep AVRH

AVRL.

*3 : Peak value of the pin concerned is regulated as the maximum output current.

*4 : Average current within 100 ms flowing in the pin concerned is regulated as the average output current.

*5 : Average current within 100 ms flowing in all pins concerned is regulated as the average total output current.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter

Symbol

Rating

Unit

Remarks

Min

Max

Power voltage

0.3

6.0

0.3

3.6

Analog power voltage

0.3

3.6

Standard analog voltage

AVRH, AVRL

0.3

3.6

Input voltage

0.3

Analog pin input voltage

0.3

Output voltage

0.3

Maximum "L" level output current

Average "L" level output current

OLAV

Maximum total "L" level output current

100

Average "L" level total output current

OLAV

Maximum "H" level output current

Average "H" level output current

OHAV

Maximum total "H" level output current

Average "H" level total output current

OHAV

Electricity consumption

650

Operating temperature

Storage temperature

Tstg

150

MB91110 Series

Recommended Operating Conditions

AVRL

0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

Parameter

Symbol

Value

Unit

Remarks

Min

Max

Power voltage

4.5

5.5

Keeping RAM status in the
case of normal operations /
stopping

3.135

3.465

Analog power voltage

3.0

3.465

Standard analog voltage

AVRH

Operating temperature

MB91110 Series

DC Characteristics

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

* : Hysteresis input pins : RST, HST, NMI, PE0/ATG, PE1/TRG0, 3, PE2/TRG1, 4, PE3/TRG2, 5,

PF0/INT0 to PF7/INT7, PG0/DREQ0, PG3/DREQ1, PH0/DREQ2, PH3/SI, PH5/SCK,
PH6/TI0, PI0/TI1, BGRNT/P81, WR1/P85, CS1/PA0 to CLK/PA6,
RAS0/PB0 to DW1/PB7

Parameter

Sym

bol

Pin name

Conditions

Value

Unit

Remarks

Min

Typ

Max

"H" level
input voltage

Input excluding
following

0.65

0.3

IHS

Refer to *

0.8

0.3

Hysteresis input

"L" level
input voltage

Input excluding
following

0.3

0.25

ILS

Refer to *

0.3

0.2

Hysteresis input

"H" level
output voltage

4.5 V

4.0 mA

0.5

"L" level
output voltage

4.5 V

4.0 mA

0.4

Input leak
current (Hi-Z
output leak
current)

5.5 V

0.45 V
< V

< V

Pull-up
resistance
value

PULL

RST

5.5 V

0.45 V

200

Power current

12.5 MHz

5.5 V

3.465 V

(4 times) in
case of 50 MHz
operation

100

150

CCS

12.5 MHz

5.5 V

3.465 V

In case of
sleeping

CCH

5.5 V

3.465 V

In case of
stopping

200

900

Input capacity

Other than V

VCC

, A

VSS

and

MB91110 Series

(1) Clock Timing

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

*1 : This is the value when 10 MHz, which is the minimum value of the clock frequency, is input to X0 and 1/2 cycle

of the oscillation circuit and gearing of 1/8 are used.

*2 : This is the value when doubler is used with a 50 MHz CPU.

Parameter

Sym-

bol

Pin

Name

Conditions

Value

Unit

Remarks

Min

Max

Clock frequency (1)

X0
X1

10.0

12.5

MHz

Self oscillation 12.5
MHz
Internal 50 MHz
operation (via PLL,
4 times)

Clock cycle time

X0
X1

100

Clock frequency (2)

X0
X1

MHz

Self oscillation
(1/2 cycle input)

Clock frequency (3)

X0
X1

MHz

External clock
(1/2 cycle input)

Clock cycle time

X0
X1

100

Input clock pulse width

X0
X1

Clock is input to
X0/X1

Clock is input to
X0 only

Input clock
rising/falling time

X0
X1

)

Internal operation
clock frequency

0.625*

MHz

CPU system

CPB

0.625*

25*

Bus system

CPP

0.625*

Peripheral system

Internal operation
clock cycle time

1600*

CPU system

CPB

40*

1600*

Bus system

CPP

1600*

Peripheral system

MB91110 Series

(2) Clock Output Timing

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

*1 : t

CYC

is frequency of 1 clock cycle including the gear cycle.

*2 : This standard value is in the case where the gear cycle is 1.

If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.

Minimum : (1

CYC

Maximum : (1

CYC

Gear cycle of 1 should be taken when using a doubler.

*3 : This standard value is in the case where the gear cycle is 1.

If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.

Minimum : n

CYC

Maximum : n

CYC

Gear cycle of 1 should be taken when using a doubler.

Parameter

Sym-

bol

Pin

Name

Condi-

tions

Value

Unit

Remarks

Min

Max

Cycle time

CYC

CLK

In case of using
doubler

CLK

CHCL

CLK

CYC

10 1

CYC

CLK

CLCH

CLK

CYC

10 1

CYC

CLK

CYC

CLCH

CHCL

MB91110 Series

The relationship between the CLK pin set using CHC/CCK1/CCK0 bit of the "Gear Control Register" (GCR) and
original oscillation input is as follows. However, original oscillation input indicates "X0 input clock" in this figure.

CYC

CCK1/0 : "00"
SLCT1, 0 : 01

CCK1, 0 : 01
SLCT1, 0 : 1X

CYC

ˇ PLL system (CHC bit of GCR : "0"setting)

ˇ 2 cycles system (CHC bit of GCR : "1"setting)

(When using doubler)

Original oscillation input

(a) Gear

1 CLK pin

Original oscillation input

(a) Gear

1 CLK pin

CCK1/0: "00"

(b) Gear

1/2 CLK pins

CCK1/0: "01"

1/4 CLK pins

CCK1/0: "10"

(d) Gear

1/8 CLK pins

CCK1/0: "11"

MB91110 Series

(4) Power On Reset

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

Parameter

Sym-

bol

Pin

Name

Conditions

Value

Unit

Remarks

Min

Max

Power startup time

5 V

is less than

0.2 V before
power is turned
on.

3.3 V

Power cut time

OFF

Repeated
operation

RST

RSTL

0.2 V

0.9

OFF

Other Points to Note

(1) Sudden changes in the power supply voltage may cause a power-on reset .To change the power
supply voltage while the device is in operation, it is recommended to rise the voltage smoothly to
suppress fluctuations as shown below.

(2) When power is turned on, it must be started while the RST pin is set to "L" level, after which wait for

RSTL

and change the level to "H" once the Vcc power level is reached.

It is recommended to keep the rising speed of
the supply voltage at 50 mV/ms or slower.

3 / AV

/ AVRH should be supplied after supplying V

/ AVRH should be supplied at the same time after supplying V

MB91110 Series

(5) Normal Bus Access Read/Write Operation

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

*1 : Time (t

CYC

number of cycles extended) needs to be added to this standard if the bus is extended by automatic

waiting insertion and RDY input.

*2 : Values of this standard are in case of gear cycle

If the gear cycle is set to 1/2, 1/4 or 1/8, calculations should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.

Calculation formula : (2

CYC

Parameter

Sym-

bol

Pin Name

Condi-

tions

Value

Unit Remarks

Min

Max

CS0 to CS5 delay time

CHCSL

CLK

CS0 to CS5

CS0 to CS5 delay time

CHCSH

Address delay time

CHAV

CLK

A23 to A00

Data delay time (write)

CHDV

CLK

D31 to D16

RD delay time

CLRL

CLK

RD delay time

CLRH

WR0 to WR1 delay time

CLWL

CLK

WR0 to WR1

WR0 to WR1 delay time

CLWH

Valid address

Valid data input time

Read

AVDV

A23 to A00

D31 to D16

CYC

*1
*2

Valid data input time

RLDV

D31 to D16

CYC

Data setup

time

DSRH

Data holding time

RHDX

MB91110 Series

(7) Holding timing

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

Note : It takes at least one cycle from loading the BRQ to when BGRNT is changed.

Parameter

Sym-

bol

Pin Name

Condi-

tions

Value

Unit

Remarks

Min

Max

BGRNT delay time

CHBGL

CLK

BGRNT

BGRNT delay time

CHBGH

Pin floating

BGRNT

time

XHAL

BGRNT

CYC

BGRNT

Pin valid time

HAHV

CYC

CLK

2.4 V

CHBGL

0.8 V

2.4 V

CHBGH

BRQ

BGRNT

Each pin

CYC

HAHV

XHAL

High impedance

MB91110 Series

(8) Read/Write Cycle of the Normal DRAM Mode

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

*1 : If either the Q1 or A4 cycle is extended for one cycle, the t

CYC

time needs to be added to this standard.

*2 : Values of this standard are in case of gear cycle

If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.

Calculation formula : (3

CYC

Parameter

Sym-

bol

Pin Name

Condi-

tions

Value

Unit Remarks

Min

Max

RAS delay time

CLRAH

CLK

RAS

RAS delay time

CHRAL

CAS delay time

CLCASL

CLK

CAS

CAS delay time

CLCASH

ROW address delay time

CHRAV

CLK

A23 to A00

COLUMN address delay time

CHCAV

DW delay time

CHDWL

CLK

DW delay time

CHDWH

Output data delay time

CHDV1

CLK

D31 to D16

RAS

valid data input time

RLDV

RAS

D31 to D16

CYC

*1
*2

CAS

valid data input time

CLDV

CAS

D31 to D16

CYC

CAS

data holding time

CADH

MB91110 Series

(9) High Speed Page Read/Write Cycle of the Normal DRAM Mode

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

* : When Q4 cycle is extended for 1 cycle, add t

CYC

time to this rating.

Parameter

Sym-

bol

Pin Name

Condi-

tions

Value

Unit

Remarks

Min

Max

RAS delay time

CLRAH

CLK, RAS

CAS delay time

CLCASL

CLK

CAS

CAS delay time

CLCASH

COLUMN address delay time

CHCAV

CLK

A23 to A00

DW delay time

CHDWH

CLK, DW

Output data delay time

CHDV1

CLK

D31 to D16

CAS

valid data input time

CLDV

CAS

D31 to D16

CYC

CAS

data holding time

CADH

MB91110 Series

(10) Single DRAM Timing

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

Parameter

Sym-

bol

Pin Name

Condi-

tions

Value

Unit

Remarks

Min

Max

RAS delay time

CLRAH2

CLK

RAS

RAS delay time

CHRAL2

CAS delay time

CHCASL2

CLK

CAS

CYC

CAS delay time

CHCASH2

ROW address delay time

CHRAV2

CLK

A23 to A00

COLUMN address delay time

CHCAV2

DW delay time

CHDWL2

CLK

DW delay time

CHDWH2

Output data delay time

CHDV2

CLK

D31 to D16

CAS

valid data input time

CLDV2

CAS

D31 to D16

CYC

CAS

data holding time

CADH2

MB91110 Series

COLUMN-2

CHCASH2

CHRAL2

CHDWH2

CHDWL2

CHDV2

D31 to D16
(Write)

CLK

D31 to D16
(Read)

RAS

CAS

A23 to A00

DW
(Write)

2.4 V

0.8 V

2.4 V
0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

Q4S

CADH2

CLDV2

CHRAV2

CHCAV2

CHCASL2

CYC

2.4 V

CLRAH2

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

COLUMN-0

COLUMN-1

ROW address

Read-0

Read-1

Read-2

Write-0

Write-1

Write-2

*1 : Q4S cycle indicates the Q4SR (read) or Q4SW (write) cycle of the Single DRAM cycle.
*2 :

indicates when a bus cycle is started from the high-speed page mode.

MB91110 Series

(11) Hyper DRAM Timing

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

Parameter

Sym-

bol

Pin Name

Condi-

tions

Value

Unit Remarks

Min

Max

RAS delay time

CLRAH3

CLK

RAS

RAS delay time

CHRAL3

CAS delay time

CHCASL3

CLK

CAS

CYC

CAS delay time

CHCASH3

ROW address delay time

CHRAV3

CLK

A23 to A00

COLUMN address delay time

CHCAV3

RD delay time

CHRL3

CLK

RD delay time

CHRH3

RD delay time

CLRL3

DW delay time

CHDWL3

CLK

DW delay time

CHDWH3

Output data delay time

CHDV3

CLK

D31 to D16

CAS

valid data input time

CLDV3

CAS

D31 to D16

CYC

CAS

data holding time

CADH3

MB91110 Series

CHCASH3

CHRAL3

CHDWH3

CHDWL3

CHDV3

D31 to D16
(Write)

CLK

D31 to D16
(Read)

RAS

CAS

RD
(Read)

A23 to A00

DW
(Write)

2.4 V

0.8 V

2.4 V
0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

Q4H

0.8 V

CADV3

CLDV3

CHRAV3

CLRL3

0.8 V

CHRL3

CHCASL3

CYC

2.4 V

CLRAH3

2.4 V

0.8 V

2.4 V

0.8 V

COLUMN-0

COLUMN-1

COLUMN-2

CHRH3

CHCAV3

0.8 V

2.4 V

0.8 V

ROW address

Read-0

Read-1

Write-2

Write-1

Write-0

*1 : Q4H cycle indicates the Q4HR (read) or Q4HW (write) cycle of the Hyper DRAM cycle.
*2 :

indicates when a bus cycle is started from the high-speed page mode.

MB91110 Series

(14) UART Timing

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

Notes :

This is the AC standard in the case of CLK synchronous mode.

CYCP

is the cycle time of the peripheral system clock.

Parameter

Symbol Pin Name

Conditions

Value

Unit

Remarks

Min

Max

Serial clock cycle time

SCYC

Internal shift

clock mode

8 t

CYCP

SCLK

SOUT

Delay time

SLOV

Valid SIN

SCLK

IVSH

100

SCLK

Valid

SIN holding lock

SHIX

Serial clock "H" pulse width

SHSL

External shift

clock mode

4 t

CYCP

Serial clock "L" pulse width

SLSH

4 t

CYCP

SCLK

SOUT

Delay time

SLOV

150

Valid SIN

SCLK

IVSH

SCLK

Valid

SIN holding lock

SHIX

MB91110 Series

(16) DMA Controller Timing

5 V

, V

3.3 V

, V

AVRL

0 V, T

C to

Parameter

Sym-

bol

Pin Name

Condi-

tions

Value

Unit

Remarks

Min

Max

DREQ input pulse
width

DRWH

DREQ0 to DREQ2

2 t

CYC

DACK delay time
(Normal bus)
(Normal DRAM)

CLDL

CLK

DACK0 to DACK2

CLDH

EOP delay time
(Normal bus)
(Normal DRAM)

CLEL

CLK

DEOP0 to DEOP2

CLEH

DACK delay time
(Single DRAM)
(Hyper DRAM)

CHDL

CLK

DACK0 to DACK2

CYC

CHDH

EOP delay time
(Single DRAM)
(Hyper DRAM)

CHEL

CLK

DEOP0 to DEOP2

CYC

CHEH

CLK

DREQ0 to DREQ2

2.4 V

0.8 V

2.4 V

DACK0 to DACK2
DEOP0 to DEOP2

DACK0 to DACK2
DEOP0 to DEOP2
(Single DRAM)
(Hyper DRAM)

CYC

DRWH

CLDL

CLEL

CHDL

CHEL

CLDH

CLEH

CHDH

MB91110 Series

A/D Converter Electrical Characteristics

5 V

, V

AVRH

3.3 V

, V

AVRL

0 V, T

C to

*1 : In case of V

3.3 V

5%, machine clock 25 MHz

*2 : This is the current in the case that the A/D converter is not activated and the CPU is stopped (in case of

VCC

AVRH

3.465 V)

Notes :

As the AVRH becomes smaller, the tolerance becomes relatively larger.

Output impedance of external circuits other than analog input must be used under the following

condition.

Output impedance of external circuits < 7 k

If the output impedance of the external circuits is too high, the sampling time for the analog voltage may be

insufficient.

Parameter

Sym-

bol

Pin Name

Value

Unit

Min

Typ

Max

Resolution

BIT

Conversion error

3.0

LSB

Linearity error

2.5

LSB

Differential linearity error

1.9

LSB

Zero transition error

AN0 to AN7

1.5

0.5

2.5

LSB

Full-scale transition error

FST

AN0 to AN7

AVRH

4.5

AVRH

1.5

AVRH

0.5

LSB

Conversion time

5.6*

Analog port input current

AIN

AN0 to AN7

0.1

Analog input voltage

AIN

AN0 to AN7

AVRH

Standard voltage

AVRH

Power supply current

Standard voltage current supplied

AVRH

110

Tolerance between channels

AN0 to AN7

LSB

ON1

: 5 k

ON2

: 620

ON3

: 620

ON4

: 620

: 2 pF

ON1

ON2

ON3

ON4

Analog input

Sample holding circuit

Comparator

Note : Figures described above should be considered as standard.

MB91110 Series

Definition of A/D Converter Terms

ˇ Resolution

Analog changes that can be identified by A/D converter

ˇ Linearity error

Difference between the straight line linking the zero transition point (00 0000 0000

00 0000 0001) to the

full-scale transition point (11 1111 1110

11 1111 1111) and actual conversion characteristics.

ˇ Differential linearity error

Difference compared to the ideal input voltage value required to change the output code 1LSB

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

{1 LSB

}

(Actual measured value)

Digital output

Actual conversion characteristics

Ideal characteristics

Analog input

Actual conversion
characteristics

FST

(Actual

measured value)

AVRL

AVRH

Actual conversion
characteristics

Ideal characteristics

(Actual measured value)

1)T

(Actual measured value)

Digital output

Analog input

Linearity error of digital output N

{1 LSB

}

1 LSB

[LSB]

Differential linearity error of digital output N

V (

)

1 LSB

FST

1022

[V]

1 LSB (Ideal value)

AVRH

AVRL

1024

[V]

: Voltage with digital output transferred from (000)

to (001)

FST

: Voltage with digital output transferred from (3FE)

to (3FF)

: Voltage with digital output transferred from (N

to N

[LSB]

[Linearity error]

[Differential linearity error]

MB91110 Series

ˇ Total error

This indicates the difference between the actual and theoretical values and includes zero transition, full-scale
transition and linearity error.

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

1.5 LSB

0.5 LSB

{1 LSB

0.5 LSB}

Digital output

Analog input

Actual conversion
characteristics

Ideal characteristics

(Actual measured value)

Total tolerance of digital output N

{1 LSB

0.5 LSB}

1 LSB

[LSB]

(Ideal value)

AVRL

0.5 LSB [V]

FST

(Ideal value)

AVRH

1.5 LSB [V]

: Voltage with digital output transferred from (N

to N

[Total error]

MB91110 Series

EXAMPLE CHARACTERISTICS

4.5

5.5

300

250

200

150

100

[V]

[mV]

= 4.0 mA, T

= 25 °C

4.5

5.5

4.5

3.5

[V]

= - 4.0 mA, T

= 25 °C

100

90
80
70
60
50

Frequency

[MHz]

CC3

[mV]

CC3

40
30
20
10

100

[V]

CC3

[mA]

CC3

3.5

4.5

6.5

[V]

CC5

[mA]

CC5

5.5

100

Frequency

[MHz]

CC5

[mA]

CC5

[V]

= 25 °C

125

100

= 3.3 V, T

= 25 °C

f = 50.0 MHz, T

= 25 °C

= 5.0 V, T

= 25 °C

f = 25.0 MHz, T

= 25 °C

Pull-up resistance

Resistor value (k

)

MB91110 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0204

FUJITSU LIMITED Printed in Japan

Part Number MB91110PMT2

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