DS07-13501-6E

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

MC-16F MB90210 Series

MB90214/P214A/P214B/W214A/W214B/V210

OUTLINE

The MB90210 series is a line of 16-bit microcontrollers particularly suitable for system control of video cameras,
VTRs, and copiers. The F

MC-16F CPU integrated in this series is based on the F

MC*-16, while providing

enhanced instructions for high-level languages and supporting extended addressing modes.

The MB90210 series incorporates a variety of peripheral resources such as a PWC timer with 4 channels, a 10-
bit A/D converter with 8 channels, UART serial ports with 3 channels (1 channel for CTS and 1 channel for dual
input/output pin switching), 16-bit reload timers with 8 channels, and an 8-bit PPG timer with 1 channel.

MB90P214B/W214B is under development.

*: F

MC stands for FUJITSU Flexible Microcontroller.

PACKAGE

80-pin Plastic QFP

(FPT-80P-M06)

80-pin Ceramic QFP

(FPT-80C-C02)

MB90210 Series

FEATURES

MC-16F CPU

· Minimum execution time: 62.5 ns/16-MHz oscillation (using a duty control system)
· Instruction sets optimized for controllers

Upward object-compatible with the F

MC-16(H)

Various data types (bit, byte, word, and long-word)
Instruction cycle improved to speed up operation
Extended addressing modes: 25 types
High coding efficiency
Access method (bank access with linear pointer)
Enhanced multiplication and division instructions (with signed instructions added)
Higher-precision operation using a 32-bit accumulator

· Extended intelligent I/O service (Automatic transfer function independent of instructions) access area

expanded to 64 Kbytes

· Enhanced instruction set applicable to high-level language (C) and multitasking

System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instruction
Stack check function

· Increased execution speed: 8-byte instruction queue
· Powerful interrupt functions: 8 levels and 29 sources

Integrated Peripheral Resources

· ROM

: 64 Kbytes (MB90214)

EPROM : 64 Kbytes (MB90W214A/W214B)
OTPROM: 64Kbytes (MB90P214A/P214B)

· RAM: 3 Kbytes (MB90214)

4 Kbytes (MB90P214A/P214B/W214A/W214B/V210)

· General-purpose ports: max. 65 channels
· PWC timer with time measurement function: 4 channels
· 10-bit A/D converter: 8 channels
· UART: 3 channels
· Including: 1 channel with CTS function

1 channel with I/O pin switching function

· 16-bit reload timer

Toggled output, external clock, and gate functions: 4 channels

External clock and gate functions: 4 channels

· 8-bit PPG timer: 1 channel
· DTP/External-interrupt inputs: 4 channels
· Write-inhibit RAM: 256 bytes (MB90V210: 512 bytes)
· Timebase counter: 18 bits
· Clock gear function
· Low-power consumption mode

Sleep mode
Stop mode
Hardware standby mode

MB90210 Series

PRODUCT LINEUP

MB90P214A

MB90P214B

MB90W214A

MB90W214B

MB90V210

Classification

Mask ROM product

OTPROM product

EPROM product

For evaluation

ROM size

64 Kbytes

RAM size

3 Kbytes

4 Kbytes

CPU functions

The number of instructions:

412

Instruction bit length:

8 or 16 bits

Instruction length:

1 to 7 bytes

Data bit length:

1, 4, 8, 16, or 32 bits

Minimum execution time:

62.5 ns/16 MHz

Interrupt processing time:

1.0

s/16 MHz (min.)

Ports

I/O ports (N-ch open-drain):

I/O ports (CMOS):

Total:

PWC timer

Number of channels: 4

16-bit reload timer operation (operating clock cycle: 0.25

s to 1.31 ms)

16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width

measurement, inter-edge measurement, and divided-frequency measurement)

10-bit
A/D converter

Resolution: 10 or 8 bits, Number of inputs: 8

Single conversion mode (conversion for each input channel)

Scan conversion mode (continuous conversion for up to 8 consecutive channels)

Continuous conversion mode (repeated conversion for a selected channel)

Stop conversion mode (conversion every fixed cycle)

UART

Number of channels: 3

(1 channel with CTS function; 1 channel with I/O pin switching function)

Clock-synchronous transfer mode

(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)

Asynchronous transfer mode

(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)

Timer

Number of channels: 4 channels

2 types

16-bit reload timer operation (operating clock cycle: 0.25

s to 1.05 s)

8-bit PPG timer

Number of channels: 1

8-bit PPG operation (operating clock cycle: 0.25

s to 6 s)

DTP/External
interrupt

Number of inputs: 4

External interrupt mode (allowing interrupts to activate at four different request levels)

Simple DMA start mode (allowing extended I

OS to activate at two different request levels)

Write-inhibit RAM

RAM size: 256 bytes (MB90V210: 512 bytes)

RAM write-protectable with WI pin

Standby mode

Stop mode (activated by software or hardware) and sleep mode

Gear function

Machine clock operating frequency switching: 16, 8, 4, or 1 MHz (at 16 MHz oscillation)

Package

FPT-80P-M06

FPT-80C-C02

PGA-256C-A02

MB90214

Part number

Item

MB90210 Series

PIN ASSIGNMENT

P00/D00
P01/D01
P02/D02
P03/D03
P04/D04
P05/D05
P06/D06
P07/D07
P10/D08

P12/D10
P13/D11
P14/D12
P15/D13

P11/D09

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

RST

P57/WI

P56/RD

P55/WRL

P54/WRH/CTS0/INT3

P53/HRQ

P52/HAK

P51/RDY

P50/CLK

P82/INT2/ATG

P81/INT1

P80/INT0

P75/SOD0

P74/SID0

P73/SCK0

P72/SOD1

P71/SID1

P70/SCK1

HST

MD2

MD1

MD0

P16D14

P17D15

P20A00/TIN0

P21/A01/TIN1

P22/A02/TIN2

P23/A03/TIN3

P24/A04/TIN4

P25/A05/TIN5

P26/A06/TIN6

P27/A07/TIN7

31/A09/

PPG

P32/A10/TOUT0

P36/A14/SCK3

P37/A15/S

I D3

P40/A16/SOD3

P30/A08

P34/A12/TOUT2

P41/A17/SC

P42/A18/S

I D2

P43/A19/S

OD2

P44/A20/

PWC0/POUT0

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
V

P61/AN1
P60/AN0
AV

AVRL

PWC3/P47/A23/POUT3
PWC2/P46/A22/POUT2
PWC1/P45/A21/POUT1

AVRH

(Top view)

(FPT-80P-M06)
(FPT-80C-C02)

P33/A11/TOUT1

P35/A13/TOUT3

MB90210 Series

PIN DESCRIPTION

* : FPT-80P-M06, FPT-80C-C02

(Continued)

Pin no.

Pin name

Circuit

type

Function

QFP*

64,

X0,
X1

Crystal oscillator pins (16 MHz)

RST

External reset request input pin

Power supply

Digital circuit power supply pin

11,
34,

Power supply

Digital circuit grounding level

67 to 74

P00 to P07

General-purpose I/O ports
These ports are available only in the single-chip mode.

D00 to D07

I/O pins for the lower eight bits of external data bus
These pins are available in an external-bus mode.

75 to 80,

P10 to P15,
P16,
P17

General-purpose I/O ports
These ports are available in the single-chip mode and in an
external-bus mode with the 8-bit data bus specified.

D08 to D13,
D14,
D15

I/O pins for the upper eight bits of external data bus
These pins are available in an external-bus mode with the 16-bit
data bus specified.

3 to 6

P20 to P23

General-purpose I/O ports
These ports are available only in the single-chip mode.

A00 to A03

Output pins for external address buses A00 to A03
These pins are available in an external-bus mode.

TIN0 to TIN3

16-bit reload timer 1 (ch.0 to ch.3) input pins
These pins are available when the 16-bit reload timer 1 (ch.0 to
ch.3) input specification is "enabled". The data on the pin is read
as the 16-bit reload timer 1 (ch.0 to ch.3) input (TIN0 to TIN3).

7 to 10

P24 to P27

General-purpose I/O ports
These ports are available only in the single-chip mode.

A04 to A07

Output pins for external address buses A04 to A07
These pins are available in an external-bus mode.

TIN4 to TIN7

16-bit reload timer 2 (ch.4 to ch.7) input pins
These pins are available when the 16-bit reload timer 2 (ch.4 to
ch.7) input specification is "enabled". The data on the pin is read
as the 16-bit reload timer 2 (ch.4 to ch.7) input (TIN4 to TIN7).

P30

General-purpose I/O port
This port is available in the single-chip mode or when the middle
address control register setting is "port."

A08

Output pin for external address bus A08
This pin is available in an external-bus mode and when the middle
address control register set to "address."

MB90210 Series

* : FPT-80P-M06, FPT-80C-C02

(Continued)

Pin no.

Pin name

Circuit

type

Function

QFP*

P31

General-purpose I/O port
This port is available in the single-chip mode or when the middle
address control register setting is "port", with the 8-bit PPG
output is disabled.

A09

Output pin for external address bus A09
This pin is available in an external-bus mode and when the middle
address control register setting is "address."

PPG

PPG timer output pin
This pin is available when the PPG operation mode control
register specification is the PPG output pin.

14 to 17

P32 to P35

General-purpose I/O ports
These ports are available in the single-chip mode or when the
middle address control register setting is "port", with the 16-bit
reload timer 1 (ch.0 to ch.3) output is disabled.

A10 to A13

Output pins for external address buses A10 to A13
These pins are available in an external-bus mode and when the
middle address control register setting is "address."

TOUT0 to TOUT3

16-bit reload timer 1 (ch.0 to ch.3) output pin
These pins are available when the 16-bit reload timer 1 (ch.0 to
ch.3) is output operation.

P36

General-purpose I/O port
This port is available when the UART (ch.2) clock output is
disabled either in the single-chip mode or when the middle
address control register setting is "port."

A14

Output pin for external address bus A14
This pin is available when the UART (ch.2) clock output is
disabled in an external-bus mode and when the middle address
control register setting is "address."

SCK3

UART (ch.2) clock output pin (SCK3)
This pin is available when the UART (ch.2) clock output is
enabled.
UART (ch.2) external clock input pin (SCK3)
This pin is available when the port is in input mode and the UART
(ch.2) specification is external clock mode.

P37

General-purpose I/O port
This port is available in the single-chip mode or when the middle
address control register setting is "port."

A15

Output pin for external address bus A15
This pin is available in an external-bus mode and when middle
address control register setting is "address."

SID3

UART (ch.2) serial data input pin (SID3)
Since this input is used whenever the SID3 is in input operation,
the output by any other function must be suspended unless the
output is intentionally performed.

MB90210 Series

* : FPT-80P-M06, FPT-80C-C02

(Continued)

Pin no.

Pin name

Circuit

type

Function

QFP*

P40

General-purpose I/O port
This port is available when the UART (ch.2) serial data output
from SOD3 is disabled either in the single-chip mode or when the
upper address control register setting is "port."

A16

Output pin for external address bus A16
This pin is available when the UART (ch.2) serial data output
from SOD3 is disabled in an external-bus mode and when the
upper address control register setting is "address."

SOD3

UART (ch.2) serial data output pin (SOD3)
This pin is available when the UART (ch.2) serial data output is
enabled.

P41

General-purpose I/O port
This port is available when the UART (ch.2) clock output is
disabled either in the single-chip mode or when the upper
address control register setting is "port."

A17

Output pin for external address bus A17
This pin is available when the UART (ch.2) clock output is
disabled in an external-bus mode and when the upper address
control register setting is "address."

SCK2

UART (ch.2) clock output pin (SCK2)
This pin is available when the UART (ch.2) clock output is
enabled.
UART (ch.2) external clock input pin (SCK2)
This pin is available when the port is in input mode and the UART
(ch.2) specification is external clock mode.

P42

General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is "port."

A18

Output pin for external address bus A18
This pin is available in an external-bus mode and when the upper
address control register setting is "address."

SID2

UART (ch.2) serial data input pin (SID2)
Since this input is used whenever the SID2 is in input operation,
the output by any other function must be suspended unless the
output is intentionally performed.

P43

General-purpose I/O port
This port is available when the UART (ch.2) serial data output
from SOD2 is disabled either in the single-chip mode or when the
upper address control register setting is "port."

A19

Output pin for external address bus A19
This pin is available when the UART (ch.2) serial data output
from SOD2 is disabled in an external-bus mode and when the
upper address control register setting is "address."

SOD2

UART (ch.2) serial data output pin (SOD2)
This pin is available when the UART (ch.2) serial data output
from SOD2 is enabled.

MB90210 Series

* : FPT-80P-M06, FPT-80C-C02

(Continued)

Pin no.

Pin name

Circuit

type

Function

QFP*

PWC0

PWC timer input pin
Since this input is used whenever the PWC0 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

POUT0

PWC timer output pin
This pin is available when the PWC0 is output operation.

P45

General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is "port."

A21

Output pin for external address bus A21
This pin is available in an external-bus mode and when the upper
address control register setting is "address."

PWC1

PWC timer data sample input pin
Since this input is used whenever the PWC1 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

POUT1

PWC timer output pin
This pin is available when the PWC1 is output operation.

P46

General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is "port."

A22

Output pin for external address bus A22
This pin is available in an external-bus mode and when the upper
address control register setting is "address."

PWC2

PWC timer input pin
Since this input is used whenever the PWC2 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

POUT2

PWC timer output pin
This pin is available when the PWC2 is output operation.

P47

General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is "port."

A23

Output pin for external address bus A23
This pin is available in an external-bus mode and when the upper
address control register setting is "address."

PWC3

PWC timer input pin
Since this input is used whenever the PWC3 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

POUT3

PWC timer output pin
This pin is available when the PWC3 is output operation.

MB90210 Series

* : FPT-80P-M06, FPT-80C-C02

(Continued)

Pin no.

Pin name

Circuit

type

Function

QFP*

P50

General-purpose I/O port
This port is available in the single-chip mode and when the CLK
output is disabled.

CLK

CLK output pin
This pin is available in an external-bus mode with the CLK output
enabled.

P51

General-purpose I/O port
This port is available in the single-chip mode or when the ready
function is disable.

RDY

Ready signal input pin
This pin is available in an external-bus mode and when the ready
function is enabled.

P52

General-purpose I/O port
This port is available in the single-chip mode or when the hold
function is disabled.

HAK

Hold acknowledge output pin
This pin is available in an external-bus mode and when the hold
function is enabled.

P53

General-purpose I/O port
This port is available in the single-chip mode or when the hold
function is disabled in an external-bus mode.

HRQ

Hold request input pin
This pin is available in an external-bus mode and when the hold
function is enabled.
Since this input is used during this operation at any time, the
output by any other function must be suspended unless the
output is intentionally performed.

P54

General-purpose I/O port
This port is available in the single-chip mode, in the external bus
8-bit mode, or when the WRH pin output is disabled.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V

level to use these pins in input mode.

CTS0

UART (ch.0) clear-to-send input pin
Since this input is used whenever the UART (ch.0) CTS function
is enabled, the output by any other function must be suspended
unless the output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V

level to use these pins in input mode.

WRH

Write strobe output pin for the upper eight bits of data bus
This pin is available in the external bus 16-bit mode with the
WRH pin output enabled in an external-bus mode.

MB90210 Series

* : FPT-80P-M06, FPT-80C-C02

(Continued)

Pin no.

Pin name

Circuit

type

Function

QFP*

INT3

External interrupt request input pin
Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V

level to use these pins in input mode.

P55

General-purpose I/O port
This port is available in the single-chip mode or when the WRL
pin output is disabled.

WRL

Write strobe output pin for the lower eight bits of data bus
This pin is available in an external-bus mode and when the WRL
pin output is enabled.

P56

General-purpose I/O port
This port is available in the single-chip mode.

Data bus read strobe output pin
This pin is available in an external-bus mode.

P57

General-purpose I/O port
This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V

level to use these pins in input mode.

RAM write disable request input
Since this input is used during this operation at any time, the
output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V

level to use these pins in input mode.

32,
33,

35 to 40

P60,
P61,
P62 to P67

Open-drain I/O ports
These ports are available when the analog input enable register
setting is "port."

AN0,
AN1,
AN2 to AN7

10-bit A/D converter analog input pins
These pins are available when the analog input enable register
setting is "analog input."

41 to 43

MD0 to MD2

Operation mode select signal input pins
Connect these pins directly to V

or V

HST

Hardware standby input pin

P70

General-purpose I/O port
This port is available when the UART (ch.1) clock output is
disabled.

MB90210 Series

* : FPT-80P-M06, FPT-80C-C02

(Continued)

Pin no.

Pin name

Circuit

type

Function

QFP*

SCK1

UART (ch.1) clock output pin
This pin is available when the UART (ch.1) clock output is
enabled.
UART (ch.1) external clock input pin
This pin is available when the port is in input mode and the UART
(ch.1) specification is external clock mode.

P71

General-purpose I/O port
This port is always available.

SID1

UART (ch.1) serial data input pin
Since this input is used whenever the UART (ch.1) is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

P72

General-purpose I/O port
This port is available when the UART (ch.1) serial data output is
disabled.

SOD1

UART (ch.1) serial data output pin
This pin is available when the UART (ch.1) serial data output is
enabled.

P73

General-purpose I/O port
This port is available when the UART (ch.0) clock output is
disabled.

SCK0

UART (ch.0) clock output pin
This pin is available when the UART (ch.0) clock output is
enabled.
UART (ch.0) external clock input pin
This pin is available when the port is in input mode and the UART
(ch.0) specification is external clock mode.

P74

General-purpose I/O port
This port is always available.

SID0

UART (ch.0) serial data input pin
Since this input is used whenever the UART (ch.0) is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

P75

General-purpose I/O port
This port is available when the UART (ch.0) serial data output is
disabled.

SOD0

UART (ch.0) serial data output pin
This pin is available when the UART (ch.0) serial data output is
enabled.

51,

P80,
P81

General-purpose I/O port
This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V

level to use these pins in input mode.

MB90210 Series

(Continued)

* : FPT-80P-M06, FPT-80C-C02

Pin no.

Pin name

Circuit

type

Function

QFP*

51,

INT0,
INT1

level to use these pins in input mode.

P82

General-purpose I/O port
This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V

level to use these pins in input mode.

INT2

level to use these pins in input mode.

ATG

10-bit A/D converter trigger input pin
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V

level to use these pins in input mode.

Power supply

Analog circuit power supply pin
This power supply must be turned on or off with a potential equal
to or higher than AV

applied to V

Be sure that AV

= V

before use and during operation.

AVRH

Power supply

Analog circuit reference voltage input pin
This pins must be turned on or off with a potential equal to or
higher than AVRH applied to AV

AVRL

Power supply

Analog circuit reference voltage input pin

Power supply

Analog circuit grounding level

MB90210 Series

I/O CIRCUIT TYPE

(Continued)

Type

Circuit

Remarks

· Oscillation feedback resistor: Approx.1 M

MB90214
MB90P214B
MB90W214B

· Oscillation feedback resistor: Approx.1 M

MB90P214A
MB90W214A

· CMOS-level I/O

Standby control provided
MB90214: With or without pull-up/pull-down

reisistor optional

MB90P214A/P214B: Without pull-up/pull-down

resistor

MB90W214A/W214B: Without pull-up/pull-down

resistor

· N-ch open-drain output
· CMOS-level hysteresis input

A/D control provided

· CMOS-level output
· CMOS-level hysteresis input

Standby control not provided
MB90214: With or without pull-up/pull-down

reisistor optional

MB90P214A/P214B: Without pull-up/pull-down

resistor

MB90W214A/W214B: Without pull-up/pull-down

resistor

Standby control

Digital output

Digital input

Standby control

Digital input

Digital output

A/D input

Digital output

Digital input

MB90210 Series

(Continued)

Note: The pull-up and pull-down resistors are always connected, regardless of the state.

Type

Circuit

Remarks

· CMOS-level output
· CMOS-level hysteresis input

Standby control provided
MB90214: With or without pull-up/pull-down

reisistor optional

MB90P214A/P214B: Without pull-up/pull-down

resistor

MB90W214A/W214B: Without pull-up/pull-down

resistor

· CMOS-level input with no standby control

Mask ROM products only:
MD2: With pull-down resistor
MD1: With pull-up resistor
MD0: With pull-down resistor

· COMS-level input with no standby control

MD2 of OTPROM products/EPROM products
only

· CMOS-level hysteresis input

Standby control not provided

· With input analog filter (40 ns Typ.)

· CMOS-level hysteresis input

Standby control not provided

· With input analog filter (40 ns Typ.)
· With pull-up resistor

MB90214: With or without pull-up/pull-down

resistor optional

MB90P214A/W214A/P214B/W214B:

With pull-up resistor

Digital input

Digital output

Digital input

power supply

Analog filter

Digital input

Pull-up
resistor

Digital input

Analog filter

: P-type transistor

: N-type transistor

MB90210 Series

HANDLING DEVICES

1. Preventing Latchup

CMOS ICs may cause latchup when a voltage higher than V

or lower than V

is applied to input or output

pins, or when a voltage exceeding the rating is applied between V

and V

If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let any voltage exceed the maximum rating.

Also, take care to prevent the analog power supply (AV

and AVRH) and analog input from exceeding the digital

power supply (V

) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.

3. Treatment of Pins when A/D is not Used

Connect to be AV

= AVRH = V

and AV

= AVRL = V

even if the A/D converter is not in use.

4. Precautions when Using an External Clock

To reset the internal circuit properly by the Low-level input to the RST pin, the "L" level input to the RST pin
must be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.

5. V

and V

Pins

Apply equal potential to the V

and V

pins.

6. Supply Voltage Variation

The operation assurance range for the V

supply voltage is as given in the ratings. However, sudden changes

in the supply voltage can cause misoperation, even if the voltage remains within the rated range. Therefore, it
is important to supply a stable voltage to the IC. The recommended power supply control guidelines are that
the commercial frequency (50 to 60 Hz) ripple variation (P-P value) on V

should be less than 10% of the

standard V

value and that the transient rate of change during sudden changes, such as during power supply

switching, should be less than 0.1 V/ms.

7. Notes on Using an External Clock

When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation
stabilization time is required even for power-on reset and wake-up from stop mode.

MB90210

Note: When using an external clock, be sure to input external clock more than 6 machine cycles after

setting the HST pin to "L" to transfer to the hardware standby mode.

Use of External Clock

MB90210 Series

PROGRAMMING FOR MB90P214A/P214B/W214A/W214B

In EPROM mode, the MB90P214A/P214B/W214A/W214B functions equivalent to the MBM27C1000. This
allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated
socket adapter (do not use the electronic signature mode).

1. Program Mode

When shipped from Fujitsu, and after each erasure, all bits (64 K

8 bits) in the MB90P214A/P214B/W214A/

W214B are in the "1" state. Data is written to the ROM by selectively programming "0's" into the desired bit
locations. Bits cannot be set to "1" electrically.

2. Programming Procedure

(1) Set the EPROM programmer to MBM27C1000.

(2) Load program data into the EPROM programmer at 10000

to 1FFFF

Note that ROM addresses FF0000

to FFFFFF

in the operation mode in the MB90P214A/P214B/W214A/

W214B series assign to 10000

to 1FFFF

in the EPROM mode (on the EPROM programmer).

(3) Mount the MB90P214A/P214B/W214A/W214B on the adapter socket, then fit the adapter socket onto the

EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting
orientations.

(4) Start programming the program data to the device.

(5) If programming has not successfully resulted, connect a capacitor of approx. 0.1

F between V

and GND,

between V

and GND.

(6) Since the MB90P214A and MB90W214A have CMOS-level input, programming to them may be impossible

depending on the output level of the general-purpose programmer. In that case, connect a pull-up resistor
to the adapter socket side.

Note: The mask ROM products (MB90214) does not support EPROM mode. Data cannot, therefore, be read by

the EPROM programmer.

FFFFFF

10000

1FFFF

Operation mode

EPROM mode

(Corresponding addresses on the EPROM mode)

FF0000

* : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 10000

/1FFFF

MB90210 Series

3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

Advantest Corp.:

TEL: Except JAPAN (81)-3-3930-4111

4. Erase Procedure

Data written in the MB90W214A/W214B are erased (from "0" to "1") by exposing the chip to ultraviolet rays with
a wavelength of 2,537 Å through the translucent cover.

Recommended irradiation dosage for exposure is 10 Wsec/cm

. This amount is reached in 15 to 20 minutes

with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface
illuminance is 1200

W/cm

If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a
longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the
package).

The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition,
check the life span of the lamp and control the illuminance appropriately.

Data in the MB90W214A/W214B are erased by exposure to light with a wavelength of 4000 Å or less.

Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure
results in a much lower erasure rate than exposure to 2537 Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4000 Å or less, cover the translucent part, for example, with a protective seal to prevent
the chip from being exposed to the light.

Exposure to light with a wavelength of 4,000 to 5,000 Å or more will not erase data in the device. If the light
applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to
such light even though the wavelength is 4,000 Å or more.

Part No.

MB90P214B

Package

QFP-80

Compatible socket adapter

Sun Hayato Co., Ltd.

ROM-80QF-32DP-16F

Recommended

programmer

manufacturer

and programmer

name

Advantest corp.

R4945A

(main unit)

R49451A

(adapter)

Recommended

MB90210 Series

5. Recommended Screening Conditions

High temperature aging is recommended as the pre-assembly screening procedure.

6. Programming Yeild

MB90P214A/P214B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.

7. Pin Assignment in EPROM Mode

(1) Pins compatible with MBM27C1000

MBM27C1000

MB90P214A, MB90P214B,

MB90W214A, MB90W214B

MBM27C1000

MB90P214A, MB90P214B,

MB90W214A, MB90W214B

Pin no.

Pin name

Pin no.

Pin name

Pin no.

Pin name

Pin no.

Pin name

MD2 (V

)

P55

PGM

P56

A15

P37

N.C.

A12

P34

A14

P36

A07

P27

A13

P35

A06

P26

A08

P30

A05

P25

A09

P31

A04

P24

A11

P33

A03

P23

A16

P40

A02

P22

A10

P32

A01

P21

P54

A00

P20

D07

P07

D00

P00

D06

P06

D01

P01

D05

P05

D02

P02

D04

P04

GND

D03

P03

Program, verify

Aging

+150

C, 48 Hrs.

Data verification

Assembly

MB90210 Series

(2) Power supply and ground connection pins

(3) Pins other than MBM27C1000-compatible pins

Type

Pin no.

Pin name

Power supply

41
42
44
66

MD0
MD1
HST
V

GND

11
30
31
34
56
57
62
63

AVRL
AV

P52
P53
RST
V

Pin no.

Pin name

Treatment

Pull up to 4.7 k

Open

1
2

27
28
29
32
33
35

40
45

50
51
to
53
54
55
61
75

P16
P17
P41
to
P47
AV

AVRH
P60
P61
P62
to
P67
P70
to
P75
P80
to
P82
P50
P51
P57
P10
to
P15

Connect a pull-up resistor of approximately 1 M

to each pin.

MB90210 Series

BLOCK DIAGRAM

UART

PWC
timer

× 4

16-bit
timer 1

DTP/External
interrupt

× 4

External bus
interface

16-bit
timer 2

MC-16F

CPU

RAM

ROM

10-bit
A/D converter
8 ch.

CTS0
SCK3
SID3
SOD3
SCK2
SID2
SOD2
SCK1
SID1
SOD1
SCK0
SID0
SOD0

TOUT0 to
TOUT3
TIN0 to
TIN3

ATG
AN0 to
AN7
AV

AVRH
AVRL
AV

PWC0 to PWC3
/POUT0 to POUT3

INT0 to INT3

D00 to D15
A00 to A23
CLK
RDY
HAK
HRQ
WRH
WRL
RD

TIN4 to
TIN7

Internal data bus

8-bit
PPG timer

PPG

8-bit
PPG timer

P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P75
P80 to P82

8-bit
PPG timer

I/O port

Write-inhibit

RAM

Clock controller

X1
X0
RST
HST
MD2
MD1
MD0

MB90210 Series

PROGRAMMING MODEL

Accumulator

User stack pointer

System stack pointer

Processor status

Program counter

User stack upper register

System stack upper register

User stack lower register

System stack lower register

Direct page register

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

Max.32 banks

RW 7

RW 6

RW 5

RW 4

R 7

R 5

R 3

R 1

R 6

R 4

R 2

R 0

RW3

RW 2

RW 1

RW 0

RL 3

RL 2

RL 1

RL 0

000180

+ RP

ILM

Processor Status (PS)

General-purpose Registers

Dedicated Registers

USP

SSP

USPCU

SSPCU

USPCL

SSPCL

DPR

PCB

DTB

USB

SSB

ADB

8 bits

16 bits

32 bits

C C R

16 bits

MSB

LSB

Upper

Lower

MB90210 Series

MEMORY MAP

Single chip

Internal ROM
and external bus

External ROM
and external bus

FFFFFF

Address #1

010000

Address #2

Address #4

Address #5

Address #6

Peripherals

RAM

Registers

RAM

Write-inhibit RAM

ROM area

FF bank

image

ROM area

000380

000180

0000C0

000000

000100

: Internal

: External

: No access

ROM area

FF bank

image

Write-inhibit RAM

Registers

Peripherals

Address #3

Type

Address #1

Address #2

Address #3

Address #4

Address #5

Address #6

MB90214

FF0000

004000

001300

001200

001100

000D00

MB90P214A/P214B
MB90W214A/W214B

FF0000

004000

001300

001200

001100

MB90V210

(FE0000

)

004000

001300

001100

MB90210 Series

I/O MAP

(Continued)

Address

Register

name

Access

Resource

name

Initial value

000000

Port 0 data register

PDR0

R/W

Port 0

XXXXXXXX

000001

Port 1 data register

PDR1

R/W

Port 1

XXXXXXXX

000002

Port 2 data register

PDR2

R/W

Port 2

XXXXXXXX

000003

Port 3 data register

PDR3

R/W

Port 3

XXXXXXXX

000004

Port 4 data register

PDR4

R/W

Port 4

XXXXXXXX

000005

Port 5 data register

PDR5

R/W

Port 5

XXXXXXXX

000006

Port 6 data register

PDR6

R/W

Port 6

1 1 1 1 1 1 1 1

000007

Port 7 data register

PDR7

R/W

Port 7

XXXXXX

000008

Port 8 data register

PDR8

R/W

Port 8

XX X

000009

to 0F

(Reserved area) *

000010

Port 0 data direction register

DDR0

R/W

Port 0

0 0 0 0 0 0 0 0

000011

Port1 data direction register

DDR1

R/W

Port 1

0 0 0 0 0 0 0 0

000012

Port 2 data direction register

DDR2

R/W

Port 2

0 0 0 0 0 0 0 0

000013

Port 3 data direction register

DDR3

R/W

Port 3

0 0 0 0 0 0 0 0

000014

Port 4 data direction register

DDR4

R/W

Port 4

0 0 0 0 0 0 0 0

000015

Port 5 data direction register

DDR5

R/W

Port 5

0 0 0 0 0 0 0 0

000016

Analog input enable register

ADER

R/W

Port 6

1 1 1 1 1 1 1 1

000017

Port 7 data direction register

DDR7

R/W

Port 7

0 0 0 0 0 0

000018

Port 8 data direction register

DDR8

R/W

Port 8

0 0 0

000019

to 1F

(Reserved area) *

000020

Mode control register 0

UMC0

R/W

UART (ch.0)

0 0 0 0 0 1 0 0

000021

Status register 0

USR0

R/W

0 0 0 1 0 0 0 0

000022

Input data register 0/output data
register 0

UIDR0/

UODR0

R/W

XXXXXXXX

000023

Rate and data register 0

URD0

R/W

0 0 0 0 0 0 0 0

000024

Mode control register 1

UMC1

R/W

UART (ch.1)

0 0 0 0 0 1 0 0

000025

Status register 1

USR1

R/W

0 0 0 1 0 0 0 0

000026

Input data register 1/output data
register 1

UIDR1/

UODR1

R/W

XXXXXXXX

000027

Rate and data register 1

URD1

R/W

0 0 0 0 0 0 0 0

MB90210 Series

(Continued)

Address

Register

name

Access

Resource

name

Initial value

000028

Mode control register 2

UMC2

R/W

UART (ch.2)

0 0 0 0 0 1 0 0

000029

Status register 2

USR2

R/W

0 0 0 1 0 0 0 0

00002A

Input data register 2/output data
register 2

UIDR2/

UODR2

R/W

XXXXXXXX

00002B

Rate and data register 2

URD2

R/W

0 0 0 0 0 0 0 0

00002C

UART redirect control register

URDR

R/W

UART (ch.0/2)

0 0000

00002D

to 2F

(Reserved area) *

000030

Interrupt/DTP enable register

ENIR

R/W

DTP/external
interrupt

0000

000031

Interrupt/DTP factor register

EIRR

R/W

0000

000032

Request level setting register

ELVR

R/W

0 0 0 0 0 0 0 0

000033

(Reserved area) *

000034

AD control status register

ADCS

R/W

10-bit A/D
converter

0 0 0 0 0 0 0 0

000035

0 0 0 0 0 0 0 0

000036

to 37

AD data register

ADCD

R/W

XXXXXXXX

0 XX

000038

to 39

Timer control status register 0

TMCSR0

R/W

16-bit reload
timer 1 (ch.0)

0 0 0 0 0 0 0 0
0 0 0 0

00003A

to 3B

Timer control status register 1

TMCSR1

R/W

16-bit reload
timer 1 (ch.1)

0 0 0 0 0 0 0 0
0 0 0 0

00003C

to 3D

Timer control status register 2

TMCSR2

R/W

16-bit reload
timer 1 (ch.2)

0 0 0 0 0 0 0 0
0 0 0 0

00003E

to 3F

Timer control status register 3

TMCSR3

R/W

16-bit reload
timer 1 (ch.3)

0 0 0 0 0 0 0 0
0 0 0 0

000040

Timer 0 timer register

TMR0

16-bit reload
timer 1 (ch.0)

XXXXXXXX

000041

XXXXXXXX

000042

Timer 0 reload register

TMRLR0

XXXXXXXX

000043

XXXXXXXX

000044

Timer 1 timer register

TMR1

16-bit reload
timer 1 (ch.1)

XXXXXXXX

000045

XXXXXXXX

000046

Timer 1 reload register

TMRLR1

XXXXXXXX

000047

XXXXXXXX

MB90210 Series

(Continued)

Address

Register

name

Access

Resource

name

Initial value

000048

Timer 2 timer register

TMR2

16-bit reload
timer 1 (ch.2)

XXXXXXXX

000049

XXXXXXXX

00004A

Timer 2 reload register

TMRLR2

XXXXXXXX

00004B

XXXXXXXX

00004C

Timer 3 timer register

TMR3

16-bit reload
timer 1 (ch.3)

XXXXXXXX

00004D

XXXXXXXX

00004E

Timer 3 reload register

TMRLR3

XXXXXXXX

00004F

XXXXXXXX

000050

Timer 4 timer register

TMR4

16-bit reload
timer 2 (ch.4)

XXXXXXXX

000051

XXXXXXXX

000052

Timer 4 reload register

TMRLR4

XXXXXXXX

000053

XXXXXXXX

000054

Timer 5 timer register

TMR5

16-bit reload
timer 2 (ch.5)

XXXXXXXX

000055

XXXXXXXX

000056

Timer 5 reload register

TMRLR5

XXXXXXXX

000057

XXXXXXXX

000058

Timer 6 timer register

TMR6

16-bit reload
timer 2 (ch.6)

XXXXXXXX

000059

XXXXXXXX

00005A

Timer 6 reload register

TMRLR6

XXXXXXXX

00005B

XXXXXXXX

00005C

Timer 7 timer register

TMR7

16-bit reload
timer 2 (ch.7)

XXXXXXXX

00005D

XXXXXXXX

00005E

Timer 7 reload register

TMRLR7

XXXXXXXX

00005F

XXXXXXXX

000060

Timer control status register 4

TMCSR4

R/W

16-bit reload
timer 2 (ch.4)

0 0 0 0 0 0 0 0

000061

(Reserved area) *

000062

Timer control status register 5

TMCSR5

R/W

16-bit reload
timer 2 (ch.5)

0 0 0 0 0 0 0 0

000063

(Reserved area) *

000064

Timer control status register 6

TMCSR6

R/W

16-bit reload
timer 2 (ch.6)

0 0 0 0 0 0 0 0

000065

(Reserved area) *

MB90210 Series

(Continued)

Address

Register

name

Access

Resource

name

Initial value

000066

Timer control status register 7

TMCSR7

R/W

16-bit reload
timer 2 (ch.7)

0 0 0 0 0 0 0 0

000067

(Reserved area) *

000068

PWC0 divide ratio register

DIVR0

R/W

PWC timer
(ch.0)

0 0

000069

(Reserved area) *

00006A

PWC1 divide ratio register

DIVR1

R/W

PWC timer
(ch.1)

0 0

00006B

(Reserved area) *

00006C

PWC2 divide ratio register

DIVR2

R/W

PWC timer
(ch.2)

0 0

00006D

(Reserved area) *

00006E

PWC3 divide ratio register

DIVR3

R/W

PWC timer
(ch.3)

0 0

00006F

(Reserved area) *

000070

PWC0 control status register

PWCSR0

R/W

PWC timer
(ch.0)

0 0 0 0 0 0 0 0

000071

0 0 0 0 0 0 0 0

000072

PWC0 data buffer register

PWCR0

R/W

0 0 0 0 0 0 0 0

000073

0 0 0 0 0 0 0 0

000074

PWC1 control status register

PWCSR1

R/W

PWC timer
(ch.1)

0 0 0 0 0 0 0 0

000075

0 0 0 0 0 0 0 0

000076

PWC1 data buffer register

PWCR1

R/W

0 0 0 0 0 0 0 0

000077

0 0 0 0 0 0 0 0

000078

PWC2 control status register

PWCSR2

R/W

PWC timer
(ch.2)

0 0 0 0 0 0 0 0

000079

0 0 0 0 0 0 0 0

00007A

PWC2 data buffer register

PWCR2

R/W

0 0 0 0 0 0 0 0

00007B

0 0 0 0 0 0 0 0

00007C

PWC3 control status register

PWCSR3

R/W

PWC timer
(ch.3)

0 0 0 0 0 0 0 0

00007D

0 0 0 0 0 0 0 0

00007E

PWC3 data buffer register

PWCR3

R/W

0 0 0 0 0 0 0 0

00007F

0 0 0 0 0 0 0 0

000080

to 87

(Reserved area) *

000088

PPG operation mode control register

PPGC

R/W

8-bit PPG timer

0 0 0 0 0 1

000089

(Reserved area) *

MB90210 Series

(Continued)

Address

Register

name

Access

Resource

name

Initial value

00008A

PPG reload register

PRL

R/W

8-bit PPG timer

XXXXXXXX

00008B

XXXXXXXX

00008C

to 8D

(Reserved area) *

00008E

WI control register

WICR

R/W

Write-inhibit RAM

00008F

to 9E

(Reserved area) *

00009F

Delayed interrupt source generate/
release register

DIRR

R/W

Delayed interrupt
generation module

0000A0

Standby control register

STBYC

R/W

Low-power
consumption
mode

0 0 0 1

0000A1

to A2

(Reserved area) *

0000A3

Middle address control register

MACR

External pin

########

0000A4

Upper address control register

HACR

########

0000A5

External pin control register

EPCR

##00#00

0000A6

to A7

(Reserved area) *

0000A8

Watchdog timer control register

WTC

R/W

Watchdog timer

XXXXXXXX

0000A9

Timebase timer control register

TBTC

R/W

Timebase timer

1 0 0 0 0 0

0000AA

to AF

(Reserved area) *

0000B0

Interrupt control register 00

ICR00

R/W

Interrupt
controller

0 0 0 0 0 1 1 1

0000B1

Interrupt control register 01

ICR01

R/W

0 0 0 0 0 1 1 1

0000B2

Interrupt control register 02

ICR02

R/W

0 0 0 0 0 1 1 1

0000B3

Interrupt control register 03

ICR03

R/W

0 0 0 0 0 1 1 1

0000B4

Interrupt control register 04

ICR04

R/W

0 0 0 0 0 1 1 1

0000B5

Interrupt control register 05

ICR05

R/W

0 0 0 0 0 1 1 1

0000B6

Interrupt control register 06

ICR06

R/W

0 0 0 0 0 1 1 1

0000B7

Interrupt control register 07

ICR07

R/W

0 0 0 0 0 1 1 1

0000B8

Interrupt control register 08

ICR08

R/W

0 0 0 0 0 1 1 1

0000B9

Interrupt control register 09

ICR09

R/W

0 0 0 0 0 1 1 1

MB90210 Series

(Continued)

Initial value
0: The initial value of this bit is 0.
1: The initial value of this bit is 1.
X: The initial value of this bit is undefined.
: This bit is not used. The initial value is undefined.

: The initial value of this bit varies with the reset source.

#: The initial value of this bit varies with the operation mode.

*1: Access inhibited
*2: The only area available for the external access below address 0000FF

is this area. Accesses to these addresses

are handled as accesses to an external I/O area.

*3: When the external bus is enabled, do not access any register not serving as a general-purpose port in the areas

from address 000000

to 000005

and from 000010

to 000015

*4: Writing to bit 15 is possible. Writing to other bits is used as a test function.

Address

Register

name

Access

Resource

name

Initial value

0000BA

Interrupt control register 10

ICR10

R/W

Interrupt
controller

0 0 0 0 0 1 1 1

0000BB

Interrupt control register 11

ICR11

R/W

0 0 0 0 0 1 1 1

0000BC

Interrupt control register 12

ICR12

R/W

0 0 0 0 0 1 1 1

0000BD

Interrupt control register 13

ICR13

R/W

0 0 0 0 0 1 1 1

0000BE

Interrupt control register 14

ICR14

R/W

0 0 0 0 0 1 1 1

0000BF

Interrupt control register 15

ICR15

R/W

0 0 0 0 0 1 1 1

0000C0

to FF

(External area) *

MB90210 Series

INTERRUPT SOURCES AND INTERRUPT VECTORS/INTERRUPT
CONTROL REGISTERS

(Continued)

Interrupt source

support

Interrupt vector

Interrupt control register

No.

Address

ICR

Address

Reset

# 08

FFFFDC

INT9 instruction

# 09

FFFFD8

Exceptional

# 10

FFFFD4

UART interrupt #0

# 11

FFFFD0

ICR00

000B0

UART interrupt #1

# 12

FFFFCC

UART interrupt #2

# 13

FFFFC8

ICR01

000B1

UART interrupt #3

# 14

FFFFC4

PWC timer # 0 · count completed

# 15

FFFFC0

ICR02

000B2

PWC timer # 0 · overflow

# 16

FFFFBC

PWC timer # 1 · count completed

# 17

FFFFB8

ICR03

000B3

PWC timer # 1 · overflow

# 18

FFFFB4

PWC timer # 2 · count completed

# 19

FFFFB0

ICR04

000B4

PWC timer # 2 · overflow

# 20

FFFFAC

PWC timer # 3 · count completed

# 21

FFFFA8

ICR05

000B5

PWC timer # 3 · overflow

# 22

FFFFA4

16-bit reload timer 1 # 0 overflow

# 23

FFFFA0

ICR06

000B6

16-bit reload timer 1 # 1 overflow

# 24

FFFF9C

16-bit reload timer 1 # 2 overflow

# 25

FFFF98

ICR07

000B7

16-bit reload timer 1 # 3 overflow

# 26

FFFF94

16-bit reload timer 2 # 4 overflow

# 27

FFFF90

ICR08

000B8

16-bit reload timer 2 # 5 overflow

# 28

FFFF8C

16-bit reload timer 2 # 6 overflow

# 29

FFFF88

ICR09

000B9

16-bit reload timer 2 # 7 overflow

# 30

FFFF84

A/D converter count completed

# 31

FFFF80

ICR10

000BA

Timebase timer interval interrupt

# 32

FFFF7C

UART2 · transmission completed

# 33

FFFF78

ICR11

000BB

UART2 · reception completed

# 34

FFFF74

MB90210 Series

(Continued)

: EI

OS is supported (with stop request).

: EI

OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI

OS is used

for one of the two, EI

OS and ordinary interrupt are not both available for the other (with stop request).

: EI

OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI

OS is used

for one of the two, EI

OS and ordinary interrupt are not both available for the other (with no stop request).

: EI

OS is not supported.

Interrupt source

support

Interrupt vector

Interrupt control register

No.

Address

ICR

Address

UART1 · transmission completed

# 35

FFFF70

ICR12

0000BC

UART1 · reception completed

# 36

FFFF6C

UART0 · transmission completed

# 37

FFFF68

ICR13

0000BD

UART0 · reception completed

# 39

FFFF60

ICR14

0000BE

Delayed interrupt generation module

# 42

FFFF54

ICR15

0000BF

Stack fault

# 255

FFFC00

MB90210 Series

PERIPHERAL RESOURCES

1. Parallel Ports

The MB90210 series has 57 I/O pins and 8 open-drain I/O pins.

Ports 0 to 5, 7, and 8 are I/O ports. Each of these ports serves as an input port when the data direction register
value is 0 and as an output port when the value is 1.

Port 6 is an open-drain port, which may be used as a port when the analog input enable register value is 0.

(1) Register Configuration

Port data registers 0 to 8 (PDR0 to PDR8)

Port direction registers 0 to 5, 7, and 8 (DDR0 to DDR5, DDR7, and DDR8)

000001

000003

000005

000007

PDR1
PDR3
PDR5
PDR7

Address:

Port data register

000000

000002

000004

000006

000008

PDR0
PDR2
PDR4
PDR6
PDR8

Address:

Port data register

Bit

PDx7

PDx0

PDx1

PDx2

PDx3

PDx4

PDx5

PDx6

PDx7

PDx0

PDx1

PDx2

PDx3

PDx4

PDx5

PDx6

PDRx

Only for the PDR6

Note: No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8.

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(1)

(R/W)

(X)

(1)

(R/W)

(X)

(1)

(R/W)

(X)

(1)

(R/W)

(X)

(1)

(R/W)

(X)

(1)

(R/W)

(X)

(1)

(R/W)

(X)

(1)

Read/write
Initial value

000011

000013

000015

000017

DDR1
DDR3
DDR5
DDR7

Address:

Port direction register

000010

000012

000014

000018

DDR0
DDR2
DDR4
DDR8

Address:

Port direction register

Bit

DDx7

DDx0

DDx1

DDx2

DDx3

DDx4

DDx5

DDx6

DDx7

DDx0

DDx1

DDx2

DDx3

DDx4

DDx5

DDx6

DDRx

No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8.
Port 6 has no DDR.

Note:

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

( 0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

MB90210 Series

(2) Block Diagram

Analog input enable register (ADER)

000016

ADER

Address:

Analog input enable register

Bit

ADE7

ADE0

ADE1

ADE2

ADE3

ADE4

ADE5

ADE6

ADER

(R/W)

(1)

(R/W)

(1)

(R/W)

(1)

(R/W)

(1)

(R/W)

(1)

(R/W)

(1)

(R/W)

(1)

(R/W)

(1)

Read/write
Initial value

Port data register read

Port data register write

Port direction register write

Port direction register read

Port data register

Port direction register

Port data register read

Port data register write

Analog input enable register write

Analog input enable register read

Port data register

Analog input enable register

RMW
(Read-modify-write instruction)

Internal data bus

I/O port (Port 0 to 5, 7, and 8)

I/O port with an open-drain output (Port 6)

MB90210 Series

2. 16-bit Reload Timer 1 (with Event Count Function)

The 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output
pin (TOUT), and a control register. The input clock can be selected from among three internal clocks and one
external clock. At the output pin (TOUT), the pulses in the toggled output waveform are output in the reload
mode; the rectangular pulses indicating that the timer is counting are in the single-shot mode. The input pin
(TIN) can be used for event input in the event count mode, and for trigger input or gate input in the internal clock
mode.

MB90210 series contains four channels for this timer.

(1) Register Configuration

Timer control status register (TMCSR)

Timer register (TMR)

000039

00003B

00003D

00003F

ch.0
ch.1
ch.2
ch.3

Address:

Timer control status register (Upper byte)

000038

00003A

00003C

00003E

ch.0
ch.1
ch.2
ch.3

Address:

Timer control status register (Lower byte)

Bit

MDO0

TRG

CNTE

INTE

RELD

OUTL

OUTE

MOD1

MOD2

CSL0

CSL1

TMCSRx

(--)
(--)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

000041

000045

000049

00004D

ch.0
ch.1
ch.2
ch.3

Address:

Timer register (Upper byte)

000040

000044

000048

00004C

ch.0
ch.1
ch.2
ch.3

Address:

Timer register (Lower byte)

Bit

TMRx

(R)
(X)

Read/write
Initial value

MB90210 Series

(2) Block Diagram

Reload register (TMRLR)

000043

000047

00004B

00004F

ch.0
ch.1
ch.2
ch.3

Address:

Reload register (Upper byte)

000042

000046

00004A

00004E

ch.0
ch.1
ch.2
ch.3

Address:

Reroal register (Lower byte)

Bit

TMRLRx

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

Read/write
Initial value

16-bit reload register

Internal data bus

16-bit down counter

Reload

GATE

OUT
CTL.

Clock selector

CSL 1

CSL 0

Retrigger

IN CTL

EXCK

Prescaler clear

MOD 2

MOD 1

MOD 0

RELD

OUTE

OUTL

I NTE

CNTE

TRG

EI OSCLR

IRQ

Clear

Port (TIN)

Port (TOUT)

UART (timer 1 ch.2 output)
A/D (timer 1 ch.3 output)

Internal clock

MB90210 Series

3. 16-bit Reload Timer 2 (with Gate Mode)

The 16-bit reload timer 2 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), and an
8-bit control register. The input clock can be selected from among four internal clocks.

The MB90210 series contains four channels for this timer.

(1) Register Configuration

Timer control status register (TMCSR)

Timer register (TMR)

Reload register (TMRLR)

000060

000062

000064

000066

ch.4
ch.5
ch.6
ch.7

Address:

Timer control status register

Bit

CSL1

STRT

INTE

RELD

GATL

GATE

CSL0

TMCSRx

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

000051

000055

000059

00005D

ch.4
ch.5
ch.6
ch.7

Address:

Timer register (Upper byte)

000050

000054

000058

00005C

ch.4
ch.5
ch.6
ch.7

Address:

Timer register (Lower byte)

Bit

TMRx

(R)
(X)

Read/write
Initial value

000053

000057

00005B

00005F

ch.4
ch.5
ch.6
ch.7

Address:

Reload register (Upper byte)

000052

000056

00005A

00005E

ch.4
ch.5
ch.6
ch.7

Address:

Reload register (Lower byte)

Bit

TMRLRx

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

(W)

(X)

Read/write
Initial value

MB90210 Series

4. UART

The UART is a serial I/O port for synchronous or asynchronous communication with external resources. It has
the following features:

· Full duplex double buffer
· Data transfer synchronous or asynchronous with clock pulses
· Multiprocessor mode support (Mode 2)
· Built-in dedicated baud-rate generator (Nine types)
· Arbitrary baud-rate setting from external clock input or internal timer

(Use the 16-bit reroad timer 1 channel 2 for internal timer.)

· Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit))
· Variable data length (7 to 9 bit no parity, 6 to 8 bit with parity)
· Error detection function (Framing, overrun, parity)
· Interrupt function (Two sources for transmission and reception)
· Transfer in NRZ format

The MB90210 series contains three channels for the UART.
UART channel 0 has the CTS function.
UART channel 2 provides dual I/O pin switching.

(1) Register Configuration

000021

000025

000029

ch.0
ch.1
ch.2

Address:

Status register

000022

000026

00002A

ch.0
ch.1
ch.2

Address:

Input data register/output data register

Bit

RDRF

TBF

RBF

TIE

RIE

TDRE

ORFE

UIDR (read)/
UODR (write)

USR

(R)

(0)

(R)

(0)

(R)

(0)

(R)

(1)

(R/W)

(0)

(R)

(0)

(R)

(0)

(R/W)

(0)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

Read/write
Initial value

000020

000024

000028

ch.0
ch.1
ch.2

Address:

Serial mode control register

Bit

PEN

SOE

SCKE

RFC

SMDE

MC0

MC1

SBL

UMC

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(W)

(1)

Read/write
Initial value

Status register (USR)

Serial mode control register (UMC)

Input data register (UIDR)/output data register (UODR)

MB90210 Series

000023

000027

00002B

ch.0
ch.1
ch.2

Address:

Rate and data register

00002C

Address:

UART redirect control register

Bit

SEL3

UDPE

CTSE

CSP

CTE

BCH

BCH0

RC0

RC1

RC2

RC3

URDR

URDx

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(--)
(--)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

Rate and data register (URD)

UART redirect control register (URDR)

MB90210 Series

(2) Block Diagram

CONTROL BUS

Dedicated baud-rate clock

External clock

16-bit reload timer 1 channel 2
(internally connected)

Clock

selector circuit Receiving clock pulse

Transmitting clock pulse

Reception interrupt
(To CPU)

SCK0 to SCK3

Transmission interrupt
(To CPU)

Transmission control circuit

SOD0 to SOD3

Transmission shifter

UODR

Start of
transmission

Reception control circuit

Start bit detector

Transmission control

circuit

Transmission bit

counter

Transmission parity

counter

Received bit counter

Recieved parity

bit counter

Reception shifter

Internal data bus

End of reception

SIDR

Reception error
occurence signal for
EI

OS (To CPU)

Reception status

detection circuit

UMC

USR

URD

PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE

RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF

BCH
RC3
RC2
RC1
RC0
BCH0
P
D8

CONTROL BUS

SID0 to SID3

MB90210 Series

5. 10-bit A/D Converter

The 10-bit A/D converter converts the analog input voltage to a digital value. It has the following features:

· Conversion time: min.6.125

s per channel (at 16-MHz machine clock)

· RC-type successive approximation with built-in sample-and-hold circuit
· 10-bit or 8-bit resolution
· Eight analog input channels programmable for selection

Single conversion mode: Selects and converts one channel.
Scan conversion mode: Converts multiple consecutive channels (up to eight channels programmable).
Consecutive conversion mode: Converts a specified channel repeatedly.
Stop conversion mode: Converts one channel and suspends its own operation until the next activation (allowing
synchronized conversion start).

· On completion of A/D conversion, the converter can generate an interrupt request to the CPU. This interrupt

generation can activate the EI

OS to transfer the A/D conversion result to memory, making the converter

suitable for continuous operation.

· Conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected.

Use the 16-bit reroad timer 1 channel 3 for the timer.

(1) Register Configuration

000035

Address:

A/D Control status register (Upper byte)

000034

Address:

A/D Control status register (Lower byte)

Bit

MD1

ANE0

ANE1

ANE2

ANS0

ANS1

ANS2

MD0

BUSY

STRT

STS0

STS1

PAUS

INTE

INT

ADCS0

ADCS1

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(W)

(0)

(--)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

000037

Address:

A/D Data register (Upper byte)

000036

Address:

A/D Data register (Lower byte)

Bit

S10

ADCD0

ADCD1

(W)

(0)

(--)
(--)

(R)
(X)

(--)
(--)

(R)
(X)

Read/write
Initial value

A/D Control status register (ADCS1 and ADCS0)

A/D Data registers (ADCD1 and ADCD0)

MB90210 Series

6. PWC(Pulse Width Count) Timer

The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count
function and a reload timer function. The hardware configuration of this module is a 16-bit up-count timer, an
input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. Using
these components, the PWC timer provides the following features:

· Timer functions:

An interrupt request can be generated at set time intervals.
Pulse signals synchronized with the timer cycle can be output.
The reference internal clock can be selected from among three internal clocks.

· Pulse-width count functions:

The time between arbitrary pulse input events can be counted.
The reference internal clock can be selected from among three internal clocks.
Various count modes:

"H" pulse width (

) /"L" pulse width (

)

Rising-edge cycle (

) /Falling-edge cycle (

)

Count between edges (

)

Cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input
pulse, with an 8 bit input divider.
An interrupt request can be generated once counting has been performed.
The number of times counting is to be performed (once or subsequently) can
be selected.

The MB90210 series contains four channels for the PWC timer.

(1) Register Configuration

PWC control status register (PWCSR)

000071

000075

000079

00007D

ch.0
ch.1
ch.2
ch.3

Address:

PWC control status register (Upper byte)

000070

000074

000078

00007C

ch.0
ch.1
ch.2
ch.3

Address:

PWC control status register (Lower byte)

Bit

CKS1

MOD0

MOD1

MOD2

S/C

PIS0

PIS1

CKS0

STRT

POUT

ERR

OVIE

OVIR

EDIE

EDIR

STOP

PWCSRx

(R/W)

(0)

(R/W)

(0)

(R)

(0)

(R/W)

(0)

(R/W)

(0)

(R)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

MB90210 Series

000073

000077

00007B

00007F

ch.0
ch.1
ch.2
ch.3

Address:

PWC data buffer register (Upper byte)

000072

000076

00007A

00007E

ch.0
ch.1
ch.2
ch.3

Address:

PWC data buffer register (Lower byte)

Bit

PWCR

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

000068

00006A

00006C

00006E

ch.0
ch.1
ch.2
ch.3

Address:

Divide ratio control register

Bit

DIV0

DIV1

DIVR

(--)
(--)

(R/W)

(0)

(R/W)

(0)

(--)
(--)

Read/write
Initial value

PWC data buffer register (PWCR)

PWC divide ratio control register (DIVR)

MB90210 Series

(2) Block Diagram

Clock

divider

Internal clock
(machine clock/4)

CKS 1
CKS 0

Divider clear

PIS 1
PIS 0

PWC0
PWC1
PWC2
PWC3

F.F.

POUT
*

Overflow

Divide ratio

select

DIVR

PWCSR

Channel

POUT pin

* : The POUT pins of the MB90210 series are assigned as follows:

Count edge end

Count end interrupt edge

Overflow interrupt request

Control bit output

Flag setting, etc.

Edge

detection

Count start edge

ERR

PIS 1
PIS 0

CKS 1
CKS 0

8-bit

divider

Dividing
ON/OFF

End edge
select

Start edge

select

Control circuit

Internal data bus

16-bit up-count timer

ch.0

ch.1

ch.2

ch.3

PWC

P44/A20/PWC0/POUT0

P45/A21/PWC1/POUT1

P46/A22/PWC2/POUT2

P47/A23/PWC3/POUT3

Error detection

Write enable

PWCR

Timer clear

Count enable

Clock

Overflow

Data transfer

Reload

ERR

PWCR read

MB90210 Series

7. 8-bit PPG Timer

This block is an 8-bit reload timer module for PPG output by controlling pulse output according to the timer
operation.

The hardware configuration of this block is an 8-bit down counter, two 8-bit reload registers, an 8-bit control
register, and an external pulse output pin. Using these components, the module provides the following features:

PPG output operation:

The module outputs pulse waves of any period and duty factor. It can also be used as
a D/A converter using an external circuit.

(1) Register Configuration

00008B

Address:

PPG reload register

00008A

Address:

PPG reload register

Bit

PRLL

PRLH

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

Read/write
Initial value

000088

Address:

PPG operation mode control register

Bit

PEN

Reserved

PUF

Reserved

POE

PCKS

PPGC

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(--)
(--)

(R/W)

(1)

(--)
(--)

Read/write
Initial value

PPG operation mode control register (PPGC)

PPG reload registers (PRLL and RRLH)

MB90210 Series

8. DTP/External Interrupt

The data transfer peripheral (DTP) is located between external peripherals and the F

MC-16F CPU. It receives

a DMA request or an interrupt request generated by the external peripherals and reports it to the F

MC-16F

CPU to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels
of "H" and "L" for extended intelligent I/O service or, and four request levels of "H," "L," rising edge and falling
edge for external interrupt requests.

(1) Register Configuration

000030

Address:

Interrupt/DTP enable register

Bit

EN0

EN1

EN2

EN3

ENIR

(--)
(--)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

000031

Address:

Interrupt/DTP source register

Bit

ER0

ER1

ER2

ER3

EIRR

(--)
(--)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

000032

Address:

Request level setting register

Bit

LB3

LA0

LB0

LA1

LB1

LA2

LB2

LA3

ELVR

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

Read/write
Initial value

Interrupt/DTP enable register (ENIR)

Interrupt/DTP source register (EIRR)

Request level setting register (ELVR)

MB90210 Series

9. Watchdog Timer and Timebase Timer

The watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase timer as
the clock source, a control register, and a watchdog reset control section. The timebase timer consists of an 18-
bit timer and an interval interrupt control circuit.

(1) Register Configuration

0000A9

Address:

Timebase timer control register

0000A8

Address:

Watchdog timer control register

Bit

PONR

WT0

WT1

WTE

SRST

ERST

WRST

STBR

Reserved

TBC0

TBC1

TBR

TBOF

TBIE

WTC

TBTC

(W)

(1)

(--)
(--)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R)

(0)

(R)
(X)

(W)

(X)

(W)

(X)

(W)

(X)

Read/write
Initial value

Watchdog timer control register (WTC)

Timebase timer control register (TBTC)

MB90210 Series

10. Delayed Interrupt Generation Module

The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module
allows an interrupt request to the F

MC-16F CPU to generate or cancel by software.

(1) Register Configuration

(2) Block Diagram

Delayed interrupt source generate/release register (DIRR)

00009F

Address:

Delayed interrupt source generate/release register

Bit

DIRR

(--)
(--)

(R/W)

(0)

(--)
(--)

Read/write
Initial value

Delayed interrupt source
generate/release register

Source latch

Internal data bus

MB90210 Series

11. Write-inhibit RAM

The write-inhibit RAM is write-protectable with the WI pin input. Maintaining the "L" level input to the WI pin
prevents a certain area of RAM from being written. The WI pin has a 4-machine-cycle filter.

(1) Register Configuration

(2) Write-inhibit RAM Area

Write-inhibit RAM area

001100

to 0011FF

(MB90214/P214A/P214B/W214A/W214B)

001100

to 0012FF

(MB90V210)

(3) Block Diagram

WI control register (WICR)

00008E

Address:

WI control register

Bit

WICR

(--)
(--)

(R/W)

(1)

(--)
(--)

Read/write
Initial value

W I

4-machine-cycle
skew removal
4-machine-cycle
skew removal

S Q

Access to other area

Internal data bus

Preceded

Write-inhibit

circuit

Select

RAM

decoder

Write-
inhibit

RAM

MB90210 Series

12. Low-power Consumption Modes, Oscillation Stabilization Delay Time, and Gear Function

The MB90210 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware
standby mode, and gear function.

Sleep mode is used to suspend only the CPU operation clock; the other components remain in operation. Stop
mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data.

The clock gear function divides the external clock frequency, which is used usually as it is, to provide a lower
machine clock frequency. This function can therefore lower the overall operation speed without changing the
oscillation frequency. The function can select the machine clock as a division of the frequency of crystal oscillation
or external clock input by 1, 2, 4, or 16.

The OSC1 and OSC0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode
or hardware standby mode.

(1) Register Configuration

Standby control register (STBYC)

0000A0

Address:

Standby control register

Bit

STP

CLK0

CLK1

OSC0

OSC1

RST

SPL

SLP

STBYC

(W)

(0)

(W)

(0)

(R/W)

(0)

(R/W)

(1)

(R/W)

(*)

(R/W)

(*)

(R/W)

(*)

(R/W)

(*)

Read/write
Initial value

Note: The initial value(*) of bit0 to bit3 is changed by reset source.

MB90210 Series

ELECTRICAL CHARACTERISTICS (MB90V210, device used for evaluation, is excluded)

1. Absolute Maximum Ratings

= AV

= 0.0 V)

*1: V

and V

must not exceed V

+ 0.3 V.

*2: Output pins

P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82

*3: Output pins

P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P75, P80 to P82

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter

Symbol

Pin

name

Value

Unit

Remarks

Min.

Max.

Power supply voltage

0.3

+ 7.0

Program voltage

0.3

13.0

MB90P214A/W214A
MB90P214B/W214B

Analog power supply voltage

0.3

+ 0.3

Power supply voltage
for A/D converter

AVRH
AVRL

0.3

Reference voltage for A/D
converter

Input voltage

0.3

+ 0.3

Output voltage

0.3

+ 0.3

"L" level output current

Rush current

"L" level total output current

Total output current

"H" level output current

Rush current

"H" level total output current

Total output current

Power consumption

650

Operating temperature

+105

MB90214/P214B/W214B

+85

MB90P214A/W214A

Storage temperature

Tstg

+150

MB90210 Series

2. Recommended Operating Conditions

= AV

= 0.0 V)

* : Excluding the temperature rise due to the heat produced.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device's electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.

Parameter

Symbol

Pin

name

Value

Unit

Remarks

Min.

Max.

Power supply voltage

4.5

5.5

When operating

3.0

5.5

Retains the RAM state in stop
mode

Analog power supply
voltage

4.5

+ 0.3

Power supply voltage for A/D
converter

AVRH

AVRL

Reference voltage for A/D
converter

AVRL

AVRH

Clock frequency

MHz

Operating temperature

+105

Single-chip mode
MB90214/P214B/W214B

+85

Single-chip mode
MB90P214A/W214A

+70

External bus mode

MB90210 Series

3. DC Characteristics

Single-chip mode MB90214/P214B/W214B : (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +105

MB90P214A/W214A

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +85

External bus mode

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +70

(Continued)

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

"H" level input
voltage

0.7 V

+ 0.3

CMOS level input

IHS

0.8 V

+ 0.3

Hysteresis input

IHM

MD0 to MD2

0.3

+ 0.3

"L" level input
voltage

0.3

0.3 V

CMOS level input

ILS

0.3

0.2 V

Hysteresis input

ILM

MD0 to MD2

0.3

+ 0.3

"H" level output
voltage

= 4.5 V

= 4.0 mA

0.5

OH1

= 4.5 V

= 2.0 mA

2.3

"L" level output
voltage

= 4.5 V

= 4.0 mA

0.4

OL1

= 4.5 V

= 2.0 mA

2.3

Input leakage
current

*1
*2

=5.5 V

0.2 V

0.8

Except pins with
pull-up/pull-down
resistor and RST
pin

=5.5 V

0.2 V

0.8 V

Analog power
supply voltage

= 16 MHz

In stop mode,
T

= +25

Input capacitance C

Pull-up resistor

puIU

RST

110

MB90214
MB90P214A/
W214A/P214B/
W214B

MD1

110

300

650

MB90214

Generic pin

110

MB90214

Pull-down resistor R

puID

MD0, MD2

110

300

650

MB90214

Generic pin

110

MB90214

MB90210 Series

(Continued)

*1: CMOS level input (P00 to P07, P10 to P17, X0)
*2: Hysteresis input pins (RST, HST, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67 P70 to P75, P80

to P82)

*3: Output pins (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82)
*4: Output pins (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to

P75, P80 to P82)

*5: The current value applies to the CPU stop mode with A/D converter inactive (V

= AV

= AVRH = +5.5 V).

*6: Other than V

, V

, AV

and AV

*7: A list of availabilities of pull-up/pull-down resistors

*8: V

= +5.0 V, V

= 0.0 V, T

= +25

C, F

= 16 MHz

*9: Measurement condition of power supply current; external clock pin and output pin are open.

Measurement condition of V

; see the table above mentioned.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

Power supply
voltage*

= 16 MHz

50*

mA MB90214

70*

100

MB90P214A/
W214A
MB90P214B/
W214B

CCS

= 16 MHz

mA In sleep mode

CCH

= +25

In stop mode
In hardware
standby input
time

Pin name

MB90214

MB90P214A/W214A

MB90P214B/W214B

RST

Availability of pull-up resistors is

optionally defined.

Pull-up resistors

available

Pull-up resistors

available

MD1

Pull-up resistors available

Unavailable

MD0, MD2

Pull-down resistors available

Unavailable

Generic pin

Availability of pull-up/pull-down

resistors is optionally defined.

Unavailable

MB90210 Series

2. AC Characteristics

(1) Clock Timing Standards

Single-chip mode MB90214/P214B/W214B : (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +105

MB90P214A/W214A

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +85

External bus mode

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +70

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

Clock frequency

X0, X1

MHz

Clock cycle time

X0, X1

62.5

100

1/F

Input clock pulse width

0.4 t

0.6 t

Duty ratio: 60%

Input clock rising/falling time

+ t

Clock Conditions

Clock Input Timings

0.7 V

0.3 V

When a crystal

ceramic resonator is used

When an external clock is used

Open

= C

= 10 pF

Select the optimum capacity value for the resonator.

MB90210 Series

(2) Clock Output Timing Standards

External mode: (V

= +4.5 to +5.5 V, V

= 0.0 V, T

= 40

C to +70

* : t

CYC

= n/F

, n gear ratio (1, 2, 4, 16)

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

Machine cycle time

CYC

CLK

Load condition:
80 pF

62.5

1600

CLK

CHCL

CYC

2 20

CYC

Relationship between Clock Frequency and Power Supply Voltage

[V]

5.5

4.5

[MHz]

Operation assurance range

Single-chip mode

External bus mode

(MB90214/P214B/W214B)
(MB90P214A/W214A)

: (T

= 40

C to +105

C, F

= 10 to 16 MHz)

: (T

= 40

C to +85

C, F

= 10 to 16 MHz)

: (T

= 40

C to +70

C, F

= 10 to 16 MHz)

CYC

CHCL

CLK

1/2 V

MB90210 Series

(3) Recommended Resonator Manufacturers

(4) Reset and Hardware Standby Input Standards

Single-chip mode MB90214/P214B/W214B : (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +105

MB90P214A/W214A

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +85

External bus mode

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +70

* : The machine cycle (t

CYC

) at hardware standby input is set to 1/16 divided oscillation.

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

Reset input time

RSTL

RST

5 t

CYC

Hardware standby input time t

HSTL

HST

5 t

CYC

X 0

X 1

*1: Fujitsu Acoustic Resonator

FAR

Inquiry: FUJITSU LIMITED

FAR part number

(built-in capacitor type)

Frequency

Initial deviation of

FAR frequency

= +25

Temperature

characteristics of

FAR frequency

= 20

C to +60

Load

capacitance*

FAR-C4C F-1 6000- 02

16.00

0.5%

Built-in

FAR-C4C F-1 6000- 12

0.5%

Sample Application of Piezoelectric Resonator (FAR Series)

RSTL

, t

HSTL

RST
HST

0.2 V

MB90210 Series

(5) Power on Supply Specifications (Power-on Reset)

Single-chip mode MB90214/P214B/W214B : (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +105

MB90P214A/W214A

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +85

External bus mode

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +70

* : Before the power rising, V

must be less than +0.2 V.

Notes:

The above specifications are for the power-on reset.

Always apply power-on reset using these specifications, regardless of whether or not
the power-on reset is needed.

There are some internal registers (such as STBYC) which are only initialized by the power-on reset.

Note: Caution on switching power supply

Abrupt change of supply voltage may initiate power-on reset, even if the above requirements are not met.
It is, therefore, recommended to power up gradually during the instantaneous change of power supply as
shown in the figure below.

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

Power supply rising time

Power supply cut-off time

OFF

0.2 V

4.5 V

OFF

0.2 V

Power-on Reset

Main power
supply voltage

Subpower
supply voltage

The rising edge should be 50 mV/ms or less.

Changing Power Supply

MB90210 Series

(6) Bus Read Timing

= +4.5 to +5.5 , V

= 0.0 V, T

= 40

C to +70

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Valid address

time

AVRL

A23 to A00

Load
condition:
80 pF

CYC

/2 20

RD pulse width

RLRH

CYC

valid data input

RLDV

D15 to D00

CYC

data hold time

RHDX

Valid address

valid data

input

AVDV

3 t

CYC

/2 40

address valid time

RHAX

A23 to A00

CYC

/2 20

Valid address

CLK

time

AVCH

A23 to A00
CLK

CYC

/2 25

CLK

time

RLCL

RD, CLK

CYC

/2 25

RLRH

RLCL

AVCH

AVRL

RHAX

RHDX

RLDV

AVDV

0.7 V

0.3 V

0.7 V

0.3 V

CLK

0.7 V

0.3 V

0.7 V

0.3 V

A23 to A00

D15 to D00

Read data

MB90210 Series

(7) Bus Write Timing

= +4.5 to +5.5 V, V

= 0.0 V, T

= 40

C to +70

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

Valid address

time t

AVWL

A23 to A00

Load
condition:
80 pF

CYC

/2 20

pulse width

WLWH

WRL, WRH

CYC

Valid data output

time

DVWH

D15 to D00

CYC

data hold time

WHDX

CYC

/2 20

address valid time t

WHAX

A23 to A00

CYC

/2 20

CLK

time

WLCH

WRL, WRH, CLK

CYC

/2 25

WLWH

WLCL

WHAX

CLK

WR
(WRL, WRH)

WHDX

Write data

DVWH

AVWL

Un-

defined

0.7 V

0.3 V

A23 to A00

D15 to D00

MB90210 Series

(8) Ready Signal Input Timing

= +4.5 to +5.5 V, V

= 0.0 V, T

= 40

C to +70

Note: Use the auto-ready function if the RDY setup time is insufficient.

(9) Hold Timing

= +4.5 to +5.5 V, V

= 0.0 V, T

= 40

C to +70

Note: It takes at least one cycle for HAK to vary after HRQ is fetched.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RDY setup time

RYHS

RDY

Load condition:
80 pF

RDY hold time

RYHH

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Pin floating

HAK

time

XHAL

HAK

Load condition:
80 pF

CYC

HAK

pin valid time

HAHV

CYC

RYHS

RYHH

RYHS

RYHH

CLK

0.7 V

0.8 V

0.2 V

A23 to A00

RD/WR
(WRL, WRH)

RDY

No wait

Wait

XHAL

HAHV

High impedance

HRQ

HAK

Each pin

0.8 V

0.2 V

0.3 V

0.7 V

MB90210 Series

(10) UART Timing

Single-chip mode

MB90214/P214B/W214B : (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +105

MB90P214A/W214A

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +85

External bus mode

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +70

Notes:

These AC characteristics assume the CLK synchronous mode.

CYC

is the machine cycle (unit: ns).

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Serial clock cycle time t

SCYC

Load condition:
80 pF

8 t

CYC

Internal shift
clock mode
output pin

SCLK

SOUT

delay time

SLOV

Valid SIN

SCLK

IVSH

100

SCLK

Valid SIN

hold time

SHIX

Serial clock "H" pulse
width

SHSL

4 t

CYC

External shift
clock mode
output pin

Serial clock "L" pulse
width

SLSH

4 t

CYC

SCLK

SOUT

delay time

SLOV

150

Valid SIN

SCLK

IVSH

SCLK

Valid SIN

hold time

SHIX

MB90210 Series

(11) Resource Input Timing

Single-chip mode

MB90214/P214B/W214B : (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +105

MB90P214A/W214A

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +85

External bus mode

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +70

(12) Resource Output Timing

Single-chip mode

MB90214/P214B/W214B : (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +105

MB90P214A/W214A

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +85

External bus mode

: (V

= +4.5 V to +5.5 V, V

= 0.0 V, T

= 40

C to +70

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

Input pulse width

TIWH

TIWL

TIN0 to TIN3

Load
condition:
80 pF

4 t

CYC

External event
count input mode

2 t

CYC

Trigger input/
Gate input mode

TIN4 to TIN7

2 t

CYC

Gate input mode

PWC0 to PWC3

2 t

CYC

INT0 to INT3

3 t

CYC

ATG

2 t

CYC

WIWL

4 t

CYC

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

CLK

OUT

transition time

TOUT0 to TOUT3
PPG
POUT0 to POUT3

Load condition:
80 pF

TIWH

TIN0 to TIN7
PWC0 to PWC3
INT0 to INT3
WI

0.8 V

0.2 V

TIWL

, t

WIWL

CLK

TOUT0 to TOUT3
PPG
POUT0 to POUT3

0.7 V

0.3V

MB90210 Series

5. A/D Converter Electrical Characteristics

Single-chip mode MB90214/P214B/W214B:

(AV

= V

= +5.0

10%, AV

= V

= 0.0 V, T

= 40

C to +105

C, +4.5 V

AVRH AVRL)

Single-chip mode MBP90214A/W214A:

(AV

= V

= +5.0

10%, AV

= V

= 0.0 V, T

= 40

C to +85

C, +4.5 V

AVRH AVRL)

External bus mode:

(AV

= V

= +5.0

10%, AV

= V

= 0.0 V, T

= 40

C to +70

C, +4.5 V

AVRH AVRL)

* : The current value applies to the CPU stop mode with the A/D converter inactive (V

= AV

= AVRH = +5.5 V).

Notes: (1) The smaller the | AVRH AVRL |, the greater the error would become relatively.

(2) Use the output impedance of the external circuit for analog input under the following conditions:

External circuit output impedance < approx. 10 k

(Sampling period

3.75

s, t

CYC

= 62.5 ns)

(3) Precision values are standard values applicable to sleep mode.
(4) If V

/AV

or V

/AV

is caused by a noise to drop to below the analog input voltage, the analog input

current is likely to increase. In such cases, a bypass capacitor or the like should be provided in the external
circuit to suppress the noise.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

Resolution n

bit

Total error

3.0

+3.0

LSB

Linearity error

2.0

+2.0

LSB

Differential
linearity error

1.5

LSB

Zero transition
voltage

AN0 to AN7

AVRL 1.5 AVRL + 0.5 AVRL + 2.5

LSB

Full-scale
transition voltage

FST

AVRH 3.5 AVRH 1.5 AVRH

+ 0.5

LSB

Conversion time

Sampling period

CONV

CYC

= 62.5 ns

6.125

98 machine

cycles

SAMP

3.75

60 machine

cycles

Analog port input
current

AIN

AN0 to AN7

0.1

Analog input
voltage

AIN

AVRL

AVRH

Analog reference
voltage

AVRH

AVRL

AVRH

Reference voltage
supply current

AVRH

200

500

Interchannel
disparity

AN0 to AN7

LSB

MB90210 Series

6. A/D Converter Glossary

Resolution: Analog changes that are identifiable with the A/D converter

When the number of bits is 10, analog voltage can be divided into 2

= 1024.

Total error: Difference between actual and logical values. This error is caused by a zero transition error,

full-scale transition error, linearity error, differential linearity error, or by noise.

Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000"

"00

0000 0001") with the full-scale transition point ("11 1111 1111"

"11 1111 1110") from actual

conversion characteristics

Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value.

Equivalent Circuit of Analog Input Circuit

Note: The values shown here are reference values.

Analog input

Comparator

ON2

ON1

: Approx. 1.5 k

ON2

: Approx. 1.5 k

: Approx. 60 pF

: Approx. 4 pF

External impedance

Digital output

11 1111 1111
11 1111 1110
11 1111 1101

N + 1
N
N 1

00 0000 0010
00 0000 0001
00 0000 0000

·
·
·
·

1LSB

FST

1022

Linearity error

1LSB theoretical value

1LSB + V

)

1LSB

N = 0 to 1022
V

NT (N = 0)

= V

NT (N = 1022)

= V

FST

Differential linearity error

(N 1) T

1LSB

N = 1 to 1022

Total error

{ ( N + 0.5 )

1LSB theoretical value }

1LSB theoretical value

N = 0 to 1022

FST

(N1)T

Theoretical value
Actual conversion value

Total error

Linerity error

(N+1)T

AVRH (V)

AVRL

1LSB + V

Theoretical value V

MB90210 Series

EXAMPLE CHARACTERISTICS

(1) Power Supply Current

Note: These are not assured value of characteristics but example characteristics.

(2) Output Voltage

Note: These are not assured value of characteristics but example characteristics.

vs. T

example characteristics

100

150

(

100

(mA)

= 16 MHz

External clock input
V

= 5.5 V

MB90P214A

MB90214

CCH

vs. T

example characteristics

100

150

(

CCH

(

= 5.5 V

vs. I

example characteristics

(mA)

5.5

5.0

4.5

4.0

3.5

3.0

(V)

= +25

= 5.0 V

vs. I

example characteristics

(mA)

2.0

1.5

1.0

0.5

0.0

0.5

(V)

= +25

= 5.0 V

MB90210 Series

(3) Pull-up/Pull-down Resistor

Note: These are not assured value of characteristics but example characteristics.

(4) Analog Filter

Note: These are not assured value of characteristics but example characteristics.

Pull-down resistor example characteristics

100

150

(

100

pul

D (k

)

= 4.5 V

= 5.0 V

= 5.5 V

Pull-up resistor example characteristics

100

150

(

100

pul

U (k

)

= 4.5 V

= 5.0 V

= 5.5 V

Pull-up resistor example characteristics

100

150

(

500

400

300

200

100

pul

U (k

)

= 5.5 V

Pull-down resistor example characteristics

100

150

(

500

400

300

200

100

pul

D (k

)

= 5.5 V

Analog filter example characteristics

4.0

4.5

5.0

5.5

6.0

(V)

Input pulse width (ns)

Filtering enable

= +25

MB90210 Series

INSTRUCTIONS (421 INSTRUCTIONS)

Table 1 Description of Items in Instruction List

Item

Description

Mnemonic

English upper case and symbol: Described directly in assembler code.
English lower case: Converted in assembler code.
Number of letters after English lower case: Describes bit width in code.

Describes number of bytes.

Describes number of cycles.
For other letters in other items, refer to table 4.

Describes correction value for calculating number of actual states.
Number of actual states is calculated by adding value in the ~section.

Operation

Describes operation of instructions.

Describes a special operation to 15 bits to 08 bits of the accumulator.
Z : Transfer 0.
X : Sign-extend and transfer.
: No transmission

Describes a special operation to the upper 16-bit of the accumulator.
* : Transmit from AL to AH.
: No transfer.
Z : Transfer 00

to AH.

X : Sign-extend AL and transfer 00

or FF

to AH.

Describes status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero),
V (overflow), and C (carry) flags.
* : Changes after execution of instruction.
: No changes.
S : Set after execution of instruction.
R : Reset after execution of instruction.

RMW

Describes whether or not the instruction is a read-modify-write type (a data is read out from
memory etc. in single cycle, and the result is written into memory etc.).
* : Read-modify-write instruction
: Not read-modify-write instruction
Note: Not used to addresses having different functions for reading and writing operations.

MB90210 Series

Table 2 Description of Symbols in Instruction Table

Item

Description

32-bit accumlator
The bit length is dependent on the instructions to be used.
Byte : Lower 8-bit of AL
Word :16-bit of AL
Long : AL: 32-bit of AH

Upper 16-bit of A

Lower 16-bit of A

Stack pointer (USP or SSP)

Program counter

SPCU

Stack pointer upper limited register

SPCL

Stack pointer lower limited register

PCB

Program bank register

DTB

Data bank register

ADB

Additional data bank register

SSB

System stack bank register

USB

User stack bank register

SPB

Current stack bank register (SSB or USB)

DPR

Direct page register

brg1

DTB, ADB, SSB, USB, DPR, PCB

brg2

DTB, ADB, SSB, USB, DPR

R0, R1, R2, R3, R4, R5, R6, R7

RWi

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RWj

RW0, RW1, RW2, RW3

RLi

RL0, RL1, RL2, RL3

dir

addr16
addr24

ad24 0 to 15

ad24 16 to 23

Specify shortened direct address.
Specify direct address.
Specify physical direct address.
bit0 to bit15 of addr24
bit16 to bit 23 of addr24

I/O area (000000

to 0000FF

)

#imm4
#imm8

#imm16
#imm32

ext (imm8)

4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data calculated by sign-extending an 8-bit immediate data

disp8

disp16

8-bit displacement
16-bit displacement

Bit offset value

vct4
vct8

Vector number (0 to 15)
Vector number (0 to 255)

( )b

Bit address

rel

ear

eam

Specify PC relative branch.
Specify effective address (code 00 to 07).
Specify effective address (code 08 to 1F).

rlst

MB90210 Series

Table 3 Effective Address Field

Note: Number of bytes for address extension corresponds to "+" in the # (number of bytes) part in the instruction

table.

Code

Symbol

Address type

Number of bytes in address

extension block*

00
01
02
03
04
05
06
07

R0
R1
R2
R3
R4
R5
R6
R7

RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7

RL0

(RL0)

RL1

(RL1)

RL2

(RL2)

RL3

(RL3)

08
09

0A
0B

@RW0
@RW1
@RW2
@RW3

0C
0D
0E

@RW0 +
@RW1 +
@RW2 +
@RW3 +

10
11
12
13
14
15
16
17

@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8

18
19

1A
1B

@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16

1C
1D
1E

@RW0 + RW7
@RW1 + RW7

@PC + disp16

addr16

0
0
2
2

MB90210 Series

Table 4 Number of Execution Cycles in Addressing Modes

Note: (a) is used for ~ (number of cycles) and B (correction value) in instruction table.

Table 5 Correction Value for Number of Cycles for Calculating Actual Number of Cycles

Notes: (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table.

Code

Operand

(a)*

Number of execution cycles for addressing modes

00 to 07

RWi

RLi

Listed in instruction table

08 to 0B

@RWj

0C to 0F

@RWj +

10 to 17

@RWi + disp8

18 to 1B

@RWj + disp16

1C
1D
1E

@RW0 + RW7
@RW1 + RW7

@PC + disp16

addr16

2
2
2
1

Operand

(b)*

(c)*

(d)*

byte

word

long

Internal register

Internal RAM even address
Internal RAM odd address

+0
+0

+0
+1

+0
+2

Other than internal RAM even address
Other than internal RAM odd address

+1
+1

+1
+3

+2
+6

External data bus 8-bit

MB90210 Series

Table 6 Transmission Instruction (Byte) [50 Instructions]

Note: For (a) and (b), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

Mnemonic

Operation

LH AH

C RMW

MOV

A, dir

MOV

A, addr16

MOV

A, Ri

MOV

A, ear

MOV

A, eam

MOV

A, io

MOV

A, #imm8

MOV

A, @A

MOV

A, @RLi + disp8

MOV

A, @SP + disp8

MOVP A, addr24
MOVP A, @A
MOVN A, #imm4

MOVX A, dir
MOVX A, addr16
MOVX A, Ri
MOVX A, ear
MOVX A, eam
MOVX A, io
MOVX A, #imm8
MOVX A, @A
MOVX A, @RWi + disp8
MOVX A, @RLi + disp8
MOVX A, @SP + disp8

MOVPX

A, addr24

MOVPX

A, @A

MOV

dir, A

MOV

addr16, A

MOV

Ri, A

MOV

ear, A

MOV

eam, A

MOV

io, A

MOV

@RLi + disp8, A

MOV

@SP + disp8, A

MOVP addr24, A

MOV

Ri, ear

MOV

Ri, eam

MOVP @A, Ri
MOV

ear, Ri

MOV

eam, Ri

MOV

Ri, #imm8

MOV

io, #imm8

MOV

dir, #imm8

MOV

ear, #imm8

MOV

eam, #imm8

MOV

@AL, AH

XCH

A, ear

XCH

A, eam

XCH

Ri, ear

XCH

Ri, eam

2
3
1
2

2 +

2
2
2
3
3
5
2
1

2
3
2
2

2 +

2
2
2
2
3
3
5
2

2
3
1
2

2 +

2
3
3
5

2 +

2
2

2 +

2
3
3
3

3 +

2 +

2
2
1
1

2 + (a)

2
2
2
6
3
3
2
1

2
2
1
1

2 + (a)

2
2
2
3
6
3
3
2

2
2
1
2

2 + (a)

2
6
3
3

3 + (a)

3
3

3 + (a)

2
3
3
2

2 + (a)

3 + (a)

5 + (a)

(b)
(b)

0
0

(b)
(b)

(b)
(b)
(b)
(b)
(b)

(b)
(b)

0
0

(b)
(b)

(b)
(b)
(b)
(b)
(b)
(b)

(b)
(b)

0
0

(b)
(b)
(b)
(b)
(b)

(b)
(b)

(b)

(b)
(b)

(b)

byte (A)

(dir)

byte (A)

(addr16)

byte (A)

(Ri)

byte (A)

(ear)

byte (A)

(eam)

byte (A)

(io)

byte (A)

imm8

byte (A)

((A))

byte (A)

((RLi) + disp8)

byte (A)

((SP) + disp8)

byte (A)

(addr24)

byte (A)

((A))

byte (A)

imm4

byte (A)

(dir)

byte (A)

(addr16)

byte (A)

(Ri)

byte (A)

(ear)

byte (A)

(eam)

byte (A)

(io)

byte (A)

imm8

byte (A)

((A))

byte (A)

((RWi) + disp8)

byte (A)

((RLi) + disp8)

byte (A)

((SP) + disp8)

byte (A)

(addr24)

byte (A)

((A))

byte (dir)

(A)

byte (addr16)

(A)

byte (Ri)

(A)

byte (ear)

(A)

byte (eam)

(A)

byte (io)

(A)

byte ((RLi) + disp8)

(A)

byte ((SP) + disp8)

(A)

byte (addr24)

(A)

byte (Ri)

(ear)

byte (Ri)

(eam)

byte ((A))

(Ri)

byte (ear)

(Ri)

byte (eam)

(Ri)

byte (Ri)

imm8

byte (io)

imm8

byte (dir)

imm8

byte (ear)

imm8

byte (eam)

imm8

byte ((A))

(AH)

byte (A)

(ear)

byte (A)

(eam)

byte (Ri)

(ear)

byte (Ri)

(eam)

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

X
X
X
X
X
X
X
X
X
X
X
X
X

Z
Z

*
*
*
*
*
*
*

*
*
*

*
*
*
*
*
*
*

*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*

*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*

*
*
*
*
*
*

MB90210 Series

Table 7 Transmission Instruction (Word) [40 Instructions]

Note: For (a) and (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

Mnemonic

Operation

LH AH

C RMW

MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
MOVW A, #imm16
MOVW A, @RWi + disp8
MOVW A, @RLi + disp8
MOVW A, @SP + disp8

MOVPW

A, addr24

MOVPW

A, @A

MOVW dir, A
MOVW addr16, A
MOVW SP, #imm16
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi + disp8, A
MOVW @RLi + disp8, A
MOVW @SP + disp8, A

MOVPW

addr24, A

MOVPW

@A, RWi

MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16

MOVW @AL, AH

XCHW

A, ear

XCHW

A, eam

XCHW

RWi, ear

XCHW

RWi, eam

2
3
1
1
2

2 +

2
2
3
2
3
3
5
2

2
3
4
1
1
2

2 +

2
2
3
3
5
2
2

2 +

3
4
4

4 +

2 +

2
2
2
1
1

2 + (a)

2
2
2
3
6
3
3
2

2
2
2
2
1
2

2 + (a)

2
3
6
3
3
3
2

3 + (a)

2
3
2

2 + (a)

3 + (a)

5 + (a)

0
0
0

0
0
0
0

(c)

word (A)

(dir)

word (A)

(addr16)

word (A)

(SP)

word (A)

(RWi)

word (A)

(ear)

word (A)

(eam)

word (A)

(io)

word (A)

((A))

word (A)

imm16

word (A)

((RWi) +disp8)

word (A)

((RLi) +disp8)

word (A)

((SP) + disp8)

word (A)

(addr24)

word (A)

((A))

word (dir)

(A)

word (addr16)

(A)

word (SP)

imm16

word (SP)

(A)

word (RWi)

(A)

word (ear)

(A)

word (eam)

(A)

word (io)

(A)

word ((RWi) +disp8)

(A)

word ((RLi) +disp8)

(A)

word ((SP) + disp8)

(A)

word (addr24)

(A)

word ((A))

(RWi)

word (RWi)

(ear)

word (RWi)

(eam)

word (ear)

(RWi)

word (eam)

(RWi)

word (RWi)

imm16

word (io)

imm16

word (ear)

imm16

word (eam)

imm16

word ((A))

(AH)

word (A)

(ear)

word (A)

(eam)

word (RWi)

(ear)

word (RWi)

(eam)

*
*
*
*
*
*
*

*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

MB90210 Series

Table 8 Transmission Instruction (Long) [11 Instructions]

Note: For (a) and (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

Mnemonic

Operation

LH AH

C RMW

MOVL

A, ear

long (A)

(ear)

MOVL

A, eam

2 +

3 + (a)

(d)

long (A)

(eam)

MOVL

A, #imm32

long (A)

imm32

MOVL

A, @SP + disp8

(d)

long (A)

((SP) + disp8)

MOVPL A, addr24

(d)

long (A)

(addr24)

MOVPL A, @A

(d)

long (A)

((A))

MOVPL @A, RLi

(d)

long ((A))

(RLi)

MOVL

@SP + disp8, A

(d)

long ((SP) + disp8)

(A)

MOVPL addr24, A

(d)

long (addr24)

(A)

MOVL

ear, A

long (ear)

(A)

MOVL

eam, A

2 +

3 + (a)

(d)

long (eam)

(A)

MB90210 Series

Table 9 Add/Subtract (Byte, Word, Long) [42 Instructions]

Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

Mnemonic

Operation

LH AH

C RMW

ADD

A,#imm8

ADD

A, dir

ADD

A, ear

ADD

A, eam

ADD

ear, A

ADD

eam, A

ADDC

A, ear

ADDC

A, eam

ADDDC A
SUB

A, #imm8

SUB

A, dir

SUB

A, ear

SUB

A, eam

SUB

ear, A

SUB

eam, A

SUBC

A, ear

SUBC

A, eam

SUBDC A

2
2
2

2 +

1
2

2 +

1
2
2
2

2 +

1
2

2 +

2
3
2

3 + (a)

2
2

3 + (a)

3
2
3
2

3 + (a)

2
2

3 + (a)

(b)

0
0

(b)

0
0

(b)

0
0

(b)

byte (A)

(A) +imm8

byte (A)

(A) +(dir)

byte (A)

(A) +(ear)

byte (A)

(A) +(eam)

byte (ear)

(ear) + (A)

byte (eam)

(eam) + (A)

byte (A)

(AH) + (AL) + (C)

byte (A)

(A) + (ear) + (C)

byte (A)

(A) + (eam) + (C)

byte (A)

(AH) + (AL) + (C) (decimal)

byte (A)

(A) imm8

byte (A)

(A) (dir)

byte (A)

(A) (ear)

byte (A)

(A) (eam)

byte (ear)

(ear) (A)

byte (eam)

(eam) (A)

byte (A)

(AH) (AL) (C)

byte (A)

(A) (ear) (C)

byte (A)

(A) (eam) (C)

byte (A)

(AH) (AL) (C) (decimal)

Z
Z
Z
Z

Z
Z
Z
Z
Z
Z
Z
Z
Z

Z
Z
Z
Z

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*

ADDW

A, ear

ADDW

A, eam

ADDW

A, #imm16

ADDW

ear, A

ADDW

eam, A

ADDCW A, ear
ADDCW A, eam
SUBW

SUBW

A, ear

SUBW

A, eam

SUBW

A, #imm16

SUBW

ear, A

SUBW

eam, A

SUBCW A, ear
SUBCW A, eam

1
2

2 +

3
2

2 +

1
2

2 +

3
2

2 +

2
2

3 + (a)

2
2

3 + (a)

2
2

3 + (a)

2
2

3 + (a)

0
0

(c)

0
0

(c)

0
0

(c)

0
0

(c)

word (A)

(AH) + (AL)

word (A)

(A) + (ear)

word (A)

(A) + (eam)

word (A)

(A) + imm16

word (ear) (ear) + (A)
word (eam) (eam) + (A)
word (A)

(A) + (ear) + (C)

word (A)

(A) + (eam) + (C)

word (A)

(AH) (AL)

word (A)

(A) (ear)

word (A)

(A) (eam)

word (A)

(A) imm16

word (ear)

(ear) (A)

word (eam)

(eam) (A)

word (A)

(A) (ear) (C)

word (A)

(A) (eam) (C)

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*

ADDL

A, ear

ADDL

A, eam

ADDL

A, #imm32

SUBL

A, ear

SUBL

A, eam

SUBL

A, #imm32

2 +

5
2

2 +

6 + (a)

4
5

6 + (a)

(d)

0
0

(d)

long (A)

(A) + (ear)

long (A)

(A) + (eam)

long (A)

(A) + imm32

long (A)

(A) (ear)

long (A)

(A) (eam)

long (A)

(A) imm32

*
*
*
*
*
*

MB90210 Series

Table 10 Increment/Decrement (Byte, Word, Long) [12 Instructions]

Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

Table 11 Compare (Byte, Word, Long) [11 Instructions]

Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

Mnemonic

Operation

LH AH

C RMW

INC

ear

INC

eam

DEC

ear

DEC

eam

2 +

3 + (a)

(b)

byte (ear)

(ear) +1

byte (eam)

(eam) +1

byte (ear)

(ear) 1

byte (eam)

(eam) 1

*
*

INCW

ear

INCW

eam

DECW

ear

DECW

eam

2 +

3 + (a)

(c)

word (ear)

(ear) +1

word (eam)

(eam) +1

word (ear)

(ear) 1

word (eam)

(eam) 1

*
*

INCL

ear

INCL

eam

DECL

ear

DECL

eam

2 +

5 + (a)

(d)

long (ear)

(ear) +1

long (eam)

(eam) +1

long (ear)

(ear) 1

long (eam)

(eam) 1

*
*

Mnemonic

Operation

LH AH

C RMW

CMP

A, ear

CMP

A, eam

CMP

A, #imm8

1
2

2 +

1
2

3 + (a)

0
0

(b)

byte (AH) (AL)
byte (A) (ear)
byte (A) (eam)
byte (A) imm8

*
*
*
*

CMPW A
CMPW A, ear
CMPW A, eam
CMPW

A, #imm16

1
2

2 +

1
2

3 + (a)

0
0

(c)

word (AH) (AL)
word (A) (ear)
word (A) (eam)
word (A) imm16

*
*
*
*

CMPL

A, ear

CMPL

A, eam

CMPL

A, #imm32

2 +

7 + (a)

(d)

word (A) (ear)
word (A) (eam)
word (A) imm32

*
*
*

MB90210 Series

Table 12 Unsigned Multiply/Division (Word, Long) [11 Instructions]

Note: For (b) and (c), refer to "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of

Cycles."

*1: Set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation.
*2: Set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation.
*3: Set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation.
*4: Set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation.
*5: Set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation.
*6: When the division-by-0, (b) for an overflow, and 2

(b) for normal operation.

*7: When the division-by-0, (c) for an overflow, and 2

*8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero.
*9: Set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero.
*10:Set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero.
*11:Set to 3 when word (AH) is zero, 11 when word (AH) is not zero.
*12:Set to 4 when word (ear) is zero, 11 when word (ear) is not zero.
*13:Set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero.

Mnemonic

Operation

LH AH

C RMW

DIVU

A, ear

DIVU

A, eam

DIVUW

A, ear

DIVUW

A, eam

MULU

A, ear

MULU

A, eam

MULUW A
MULUW A, ear
MULUW A, eam

2 +

1
2

2 +

1
2

2 +

*8
*9

*10
*11
*12
*13

0
0

(b)

0
0

(c)

word (AH) /byte (AL)

Quotient

byte (AL)

Remainder

byte (AH)

word (A)/byte (ear)

Quotient

byte (A)

Remainder

byte (ear)

word (A)/byte (eam)

Quotient

byte (A)

Remainder

byte (eam)

long (A)/word (ear)

Quotient

word (A)

Remainder

word (ear)

long (A)/word (eam)

Quotient

word (A)

Remainder

word (eam)

byte (AH) byte (AL)

word (A)

byte (A) byte (ear)

word (A)

byte (A) byte (eam)

word (A)

word (AH) word (AL)

long (A)

word (A) word (ear)

long (A)

word (A) word (eam)

long (A)

MB90210 Series

Table 13 Signed multiplication/division (Word, Long) [11 Instructions]

For (b) and (c), refer to "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."

*1: Set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation.
*2: Set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation.
*3: Set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
*4: Positive divided: Set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation.

Negative divided: Set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation.

*5: Positive divided: Set to 4 + (a) for divide-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation.

Negative divided: Set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal
operation.

*6: Set to (b) when the division-by-0 or an overflow, and 2

(b) for normal operation.

*7: Set to (c) when the division-by-0 or an overflow, and 2

*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10:Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11:Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12:Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13:Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.

Note: When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two

values because of detection before and after an operation.
When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.

Mnemonic

Operation

LH AH

C RMW

DIV

word (AH)/byte (AL)

Quotient

byte (AL)

Remainder

byte (AH)

DIV

A, ear

word (A)/byte (ear)

Quotient

byte (A)

Remainder

byte (ear)

DIV

A, eam

2 + *3

*6 word (A)/byte (eam)

Quotient

byte (A)

Remainder

byte (eam)

DIVW

A, ear

long (A)/word (ear)

Quotient

word (A)

Remainder

word (ear)

DIVW

A, eam

2 + *5

*7 long (A)/word (eam)

Quotient

word (A)

Remainder

word (eam)

MUL

byte (AH)

byte (AL)

word (A)

MUL

A, ear

byte (A)

byte (ear)

word (A)

MUL

A, eam

2 + *10 (b)

byte (A)

byte (eam)

word (A)

MULW

*11

word (AH)

word (AL)

long (A)

MULW

A, ear

*12

word (A)

word (ear)

long (A)

MULW

A, eam

2 + *13 (b) word

(A)

word

(eam)

long

(A)

MB90210 Series

Table 14 Logic 1 (Byte, Word) [39 Instructions]

Note: For (a) to (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

Mnemonic

Operation

LH AH

C RMW

AND

A, #imm8

AND

A, ear

AND

A, eam

AND

ear, A

AND

eam, A

A, #imm8

A, ear

A, eam

ear, A

eam, A

XOR

A, #imm8

XOR

A, ear

XOR

A, eam

XOR

ear, A

XOR

eam, A

NOT

ear

NOT

eam

2
2

2 +

2
2

2 +

2
2

2 +

1
2

2 +

2
2

3 + (a)

2
2

3 + (a)

2
2

3 + (a)

2
2

3 + (a)

0
0

(b)

0
0

(b)

0
0

(b)

0
0

(b)

byte (A)

(A) and imm8

byte (A)

(A) and (ear)

byte (A)

(A) and (eam)

byte (ear)

(ear) and (A)

byte (eam)

(eam) and (A)

byte (A)

(A) or imm8

byte (A)

(A) or (ear)

byte (A)

(A) or (eam)

byte (ear)

(ear) or (A)

byte (eam)

(eam) or (A)

byte (A)

(A) xor imm8

byte (A)

(A) xor (ear)

byte (A)

(A) xor (eam)

byte (ear)

(ear) xor (A)

byte (eam)

(eam) xor (A)

byte (A)

not (A)

byte (ear)

not (ear)

byte (eam)

not (eam)

*
*
*
*
*

*
*
*
*
*
*
*
*

*
*
*
*
*

*
*
*
*
*
*
*
*

R
R
R
R
R

R
R
R
R
R
R
R
R

*
*

ANDW A
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A

ORW

A, #imm16

ORW

A, ear

ORW

A, eam

ORW

ear, A

ORW

eam, A

XORW A
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
NOTW A
NOTW ear
NOTW eam

1
3
2

2 +

1
3
2

2 +

1
3
2

2 +

1
2

2 +

2
2
2

3 + (a)

2
2
2

3 + (a)

2
2
2

3 + (a)

2
3

3 + (a)

0
0
0

(c)

0
0
0

(c)

0
0
0

(c)

0
0

(c)

word (A)

(AH) and (A)

word (A)

(A) and imm16

word (A)

(A) and (ear)

word (A)

(A) and (eam)

word (ear)

(ear) and (A)

word (eam)

(eam) and (A)

word (A)

(AH) or (A)

word (A)

(A) or imm16

word (A)

(A) or (ear)

word (A)

(A) or (eam)

word (ear)

(ear) or (A)

word (eam)

(eam) or (A)

word (A)

(AH) xor (A)

word (A)

(A) xor imm16

word (A)

(A) xor (ear)

word (A)

(A) xor (eam)

word (ear)

(ear) xor (A)

word (eam)

(eam) xor (A)

word (A)

not (A)

word (ear)

not (ear)

word (eam)

not (eam)

*
*
*
*
*
*

*
*
*
*
*
*
*
*
*

*
*
*
*
*
*

*
*
*
*
*
*
*
*
*

R
R
R
R
R
R

R
R
R
R
R
R
R
R
R

*
*

MB90210 Series

Table 15 Logic 2 (Long) [6 Instructions]

Note: For (a) and (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

Table 16 Sign Reverse (Byte, Word) [6 Instructions]

Note: For (a) and (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

Table 17 Absolute Values (Byte, Word, Long) [3 Instructions]

Table 18 Normalize Instruction (Long) [1 Instruction]

* : Set to 5 when the accumulator is all "0", otherwise set to 5 + (R0).

Mnemonic

Operation

LH AH

C RMW

ANDL

A, ear

ANDL

A, eam

ORL

A, ear

ORL

A, eam

XORL

A, ear

XORL

A, eam

2 +

6 + (a)

(d)

long (A)

(A) and (ear)

long (A)

(A) and (eam)

long (A)

(A) or (ear)

long (A)

(A) or (eam)

long (A)

(A) xor (ear)

long (A)

(A) xor (eam)

*
*

R
R

Mnemonic

Operation

LH AH

RMW

NEG

ear

NEG

eam

2 +

5 + (a)

2
0

(b)

byte (A)

0 (A)

byte (ear)

0 (ear)

byte (eam)

0 (eam)

*
*

NEGW A

NEGW ear
NEGW eam

2 +

5 + (a)

2
0

(c)

word (A)

0 (A)

word (ear)

0 (ear)

word (eam)

0 (eam)

*
*

Mnemonic

Operation

LH AH

C RMW

ABS

ABSW

ABSL

2
2
2

2
2
4

0
0
0

byte (A)

Absolute value (A)

word (A)

Absolute value (A)

long (A)

Absolute value (A)

*
*
*

Mnemonic

Operation

LH AH

RMW

NRML

A, R0

long (A)

Shift to where "1"

is originally located
byte (R0)

Number of shifts

in the operation

MB90210 Series

Table 19 Shift Type Instruction (Byte, Word, Long) [27 Instructions]

Note: For (a) and (b), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

*1: Set to 3 when R0 is 0, otherwise 3 + (R0).
*2: Set to 3 when R0 is 0, otherwise 4 + (R0).
*3: Set to 3 when imm8 is 0, otherwise 3 + imm8.
*4: Set to 3 when imm8 is 0, otherwise 4 + imm8.

Mnemonic

Operation

LH AH

V C

RMW

RORC A
ROLC A

RORC ear
RORC eam
ROLC ear
ROLC eam

ASR

A, R0

LSR

A, R0

LSL

A, R0

ASR

A, #imm8

LSR

A, #imm8

LSL

A, #imm8

2
2

2 +

2
2
2

3
3
3

2
2

3 + (a)

*1
*1
*1

*3
*3
*3

0
0

(b)

0
0
0

byte (A)

With right-rotate carry

byte (A)

With left-rotate carry

byte (ear)

With right-rotate carry

byte (eam)

With right-rotate carry

byte (ear)

With left-rotate carry

byte (eam)

With left-rotate carry

byte (A)

Arithmetic right barrel shift (A, R0)

byte (A)

Logical right barrel shift (A, R0)

byte (A)

Logical left barrel shift (A, R0)

byte (A)

Arithmetic right barrel shift (A, imm8)

byte (A)

Logical right barrel shift (A, imm8)

byte (A)

Logical left barrel shift (A, imm8)

*
*

*
*
*
*

*
*
*

*
*

*
*
*
*

*
*
*

*
*

*
*
*
*

*
*
*

*
*
*
*

ASRW A
LSRW

A/SHRW A

LSLW

A/SHLW A

ASRW A, R0
LSRW A, R0
LSLW A, R0

ASRW

A, #imm8

LSRW

A, #imm8

LSLW

A, #imm8

1
1
1

2
2
2

3
3
3

2
2
2

*1
*1
*1

*3
*3
*3

0
0
0

word (A)

Arithmetic right shift (A, 1 bit)

word (A)

Logical right shift (A, 1 bit)

word (A)

Logical left shift (A, 1 bit)

word (A)

Arithmetic right barrel shift (A, R0)

word (A)

Logical right barrel shift (A, R0)

word (A)

Logical left barrel shift (A, R0)

word (A)

Arithmetic right barrel shift (A, imm8)

word (A)

Logical right barrel shift (A, imm8)

word (A)

Logical left barrel shift (A, imm8)

*
*

*
*
*

ASRL A, R0
LSRL A, R0
LSLL

A, R0

ASRL

A, #imm8

LSRL

A, #imm8

LSLL

A, #imm8

2
2
2

3
3
3

*2
*2
*2

*4
*4
*4

0
0
0

long (A)

Arithmetic right barrel shift (A, R0)

long (A)

Logical right barrel shift (A, R0)

long (A)

Logical left barrel shift (A, R0)

long (A)

Arithmetic right barrel shift (A, imm8)

long (A)

Logical right barrel shift (A, imm8)

long (A)

Logical left barrel shift (A, imm8)

*
*

*
*
*

MB90210 Series

Table 20 Branch 1 [31 Instructions]

Note: For (a), (c) and (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

*1: Set to 3 when branch is executed, and 2 when branch is not executed.
*2: 3

*3: Reads (word) of the branch destination address.
*4: W pushes to stack (word), and R reads (word) of the branch destination address.
*5: Pushes to stack (word).
*6: W pushes to stack (long), and R reads (long) of the branch destination address.
*7: Pushes to stack (long).

Mnemonic

Operation

LH AH

V C RMW

BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN

rel

BNV

rel

BNT

rel

BLT

rel

BGE

rel

BLE

rel

BGT

rel

BLS

rel

BHI

rel

BRA

rel

JMP

addr16

JMP

@ear

JMP

@eam

JMPP

@ear *

JMPP

@eam *

JMPP

addr24

CALL

@ear *

CALL

@eam *

CALL

addr16 *

CALLV

#vct4 *

CALLP

@ear *

CALLP

@eam *

CALLP

addr24 *

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1
3
2

2 +

3
1
2

2 +

*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1

2
2
3

4 + (a)

5 + (a)

5
5
7

8 + (a)

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0

(c)

(d)

(c)

Branch if (Z) = 1
Branch if (Z) = 0
Branch if (C) = 1
Branch if (C) = 0
Branch if (N) = 1
Branch if (N) = 0
Branch if (V) = 1
Branch if (V) = 0
Branch if (T) = 1
Branch if (T) = 0
Branch if (V) xor (N) = 1
Branch if (V) xor (N) = 0

Branch if ((V) xor (N)) or (Z) = 1
Branch if ((V) xor (N)) or (Z) = 0

Branch if (C) or (Z) = 1
Branch if (C) or (Z) = 0
Branch unconditionally

word (PC)

(A)

word (PC)

addr16

word (PC)

(ear)

word (PC)

(eam)

word (PC)

(ear), (PCB)

(ear + 2)

word (PC)

(eam), (PCB)

(eam + 2)

word (PC)

ad24 0 15,

(PCB)

ad24 16 23

word (PC)

(ear)

word (PC)

(eam)

word (PC)

addr16

Vector call instruction
word (PC)

(ear) 0 15

(PCB)

(ear) 16 23

word (PC)

(eam) 0 15

(PCB)

(eam) 16 23

word (PC)

addr0 15,

(PCB)

addr16 23

MB90210 Series

Table 21 Branch 2 [20 Instructions]

Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

*1: Set to 4 when branch is executed, and 3 when branch is not executed.
*2: Set to 5 when branch is executed, and 4 when branch is not executed.
*3: Set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed.
*4: Set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed.
*5: Set to 3

(b) + 2

*6: This is a high-speed interrupt return instruction. In the instruction, an interrupt request is detected. When an

interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector.

*7: Return from stack (word).
*8: Return from stack (long).

Mnemonic

Operation

LH AH

C RMW

CBNE

A, #imm8, rel

CWBNE A, #imm16, rel

CBNE

ear, #imm8, rel

CBNE

eam, #imm8, rel

CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel

DBNZ

ear, rel

DBNZ

eam, rel

DWBNZ ear, rel

DWBNZ eam, rel

INT

#vct8

INT

addr16

INTP

addr24

INT9
RETI
RETIQ *

LINK

#imm8

UNLINK

RET *

RETP *

3
4

4 +

5 +

3 +

2
3
4
1
1
2

1
1

*1
*1

*1
*3
*1
*3

14
12
13
14

4
5

0
0

(b)

(c)

(b)

(c)

Branch if byte (A)

imm8

Branch if word (A)

imm16

Branch if byte (ear)

imm8

Branch if byte (eam)

imm8

Branch if word (ear)

imm16

Branch if word (eam)

imm16

byte (ear) = (ear) 1,
Branch if (ear)

byte (eam) = (eam) 1,
Branch if (eam)

word (ear) = (ear) 1,
Branch if (ear)

word (eam) = (eam) 1,
Branch if (eam)

Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
Return from interrupt

Stores old frame pointer in
the beginning of the
function, set new frame
pointer, and reserves local
pointer area
Restore old frame pointer
from stack in the end of
the function

Return from subroutine
Return from subroutine

R
R
R
R

*
*

S
S
S
S

*
*

*
*
*
*

*
*

*
*
*
*

*
*

*
*
*
*

*
*

*
*
*
*

*
*

MB90210 Series

Table 22 Miscellaneous Control Types (Byte, Word, Long) [36 Instructions]

Note: For (a) and (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles."

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB

: 2 states

DPR

: 3 states

*2: 3 + 4

(number of POPs)

*3: 3 + 4

(number of PUSHes)

*4: (Number of POPs)

(c), or (number of PUSHes)

(c)

*5: Set to 3 when AL is 0, 5 when AL is not 0.
*6: Set to 4 when AL is 0, 6 when AL is not 0.
*7: Set to 5 when AL is 0, 7 when AL is not 0.

Mnemonic

Operation

LH AH

V C RMW

PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst

POPW

rlst

JCTX

AND

CCR, #imm8

MOV

RP, #imm8

MOV

ILM, #imm8

MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam

ADDSP #imm8
ADDSP #imm16

MOV

A, brgl

MOV

brg2, A

MOV

brg2, #imm8

NOP
ADB
DTB
PCB
SPB
NCC
CMR

MOVW SPCU, #imm16
MOVW SPCL, #imm16

SETSPC
CLRSPC

BTSCN A

BTSCNS

BTSCND

1
1
1
2

2
2

2 +

2
3

2
2
3

1
1
1
1
1
1
1

4
4
2
2

2
2
2

3
3
3

3
3

2
2

2 + (a)

1 + (a)

3
3

1
2

1
1
1
1
1
1
1

2
2
2
2

*5
*6
*7

(c)

0
0

0
0
0
0

0
0

0
0
0

0
0
0
0
0
0
0

0
0
0
0

0
0
0

word (SP)

(SP) 2, ((SP))

(A)

word (SP)

(SP) 2, ((SP))

(AH)

word (SP)

(SP) 2, ((SP))

(PS)

(PS) 2n, ((SP))

(rlst)

word (A)

((SP)), (SP)

(

SP) + 2

word (AH)

((SP)), (SP)

(

SP) + 2

word (PS)

((SP)), (SP)

(

SP) + 2

(rlst)

((SP)), (SP)

(SP) + 2n

Context switch instruction

byte (CCR)

(CCR) and imm8

byte (CCR)

(CCR) or imm8

byte (RP)

imm8

byte (ILM)

imm8

word (RWi)

ear

word (RWi)

eam

word(A)

ear

word (A)

eam

word (SP)

(SP) + ext (imm8)

word (SP)

(SP) + imm16

byte (A)

(brgl)

byte (brg2)

(A)

byte (brg2)

imm8

No operation

Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no change in flag
Prefix for common register bank

word (SPCU)

(imm16)

word (SPCL)

(imm16)

Enables stack check operation.
Disables stack check operation.

Bit position of 1 in byte (A) from word (A)

Bit position (

2) of 1 in byte (A) from word (A)

Bit position (

4) of 1 in byte (A) from word (A)

Z
Z
Z

*
*

*
*
*

*
*

*
*
*

*
*

MB90210 Series

Table 23 Bit Manipulation Instruction [21 Instructions]

Note: For (b), refer to "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."

*1: Set to 5 when branch is executed, and 4 when branch is not executed.
*2: 7 if conditions are met, 6 when conditions are not met.
*3: Indeterminate times
*4: Until conditions are met

Mnemonic

Operation

LH AH

V C RMW

MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp

MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A

SETB dir:bp
SETB addr16:bp
SETB io:bp

CLRB dir:bp
CLRB addr16:bp
CLRB io:bp

BBC

dir:bp, rel

BBC

addr16:bp, rel

BBC

io:bp, rel

BBS

dir:bp, rel

BBS

addr16:bp, rel

BBS

io:bp, rel

SBBS

addr16:bp, rel

WBTS io:bp

WBTC io:bp

3
4
3

4
5
4

3
3
3

4
4
4

*1
*1
*1

(b)
(b)
(b)

(b)

(b)
(b)
(b)

(b)

byte (A)

(dir:bp) b

byte (A)

(addr16:bp) b

byte (A)

(io:bp) b

bit (dir:bp) b

(A)

bit (addr16:bp) b

(A)

bit (io:bp) b

(A)

bit (dir:bp) b

bit (addr16:bp) b

bit (io:bp) b

bit (dir:bp) b

bit (addr16:bp) b

bit (io:bp) b

Branch if (dir:bp) b = 0
Branch if (addr16:bp) b = 0
Branch if (io:bp) b = 0

Branch if (dir:bp) b = 1
Branch if (addr16:bp) b = 1
Branch if (io:bp) b = 1

Branch if (addr16:bp) b = 1, bit = 1

Wait until (io:bp) b = 1

Wait until (io:bp) b = 0

Z
Z
Z

*
*
*

MB90210 Series

Table 24 Accumulator Manipulation Instruction (Byte, Word) [6 Instructions]

Table 25 String Instruction [10 Instructions]

m: RW0 value (counter value)

*1: 3 when RW0 is 0, 2 + 6

(RW0) when count out, and 6n + 4 when matched

*2: 4 when RW0 is 0, otherwise 2 + 6

(RW0)

*3: (b)

(RW0)

*4: (b)

*5: (b)

(RW0)

*6: (c)

(RW0)

*7: (c)

*8: (c)

(RW0)

Mnemonic

Operation

LH AH

C RMW

SWAP
SWAPW/XCHW AL, AH
EXT
EXTW
ZEXT
ZEXTW

1
1
1
1
1
1

3
2
1
2
1
1

0
0
0
0
0
0

byte (A) 0 7

(A) 8 15

word (AH)

(AL)

byte sign-extension
word sign-extension
byte zero-extension
word zero-extension

*
*

R
R

*
*
*
*

Mnemonic

Operation

LH AH

C RMW

MOVS/MOVSI

MOVSD

SCEQ/SCEQI

SCEQD

FISL/FILSI

5m + 6

byte transfer @AH +

@AL +,

Counter = RW0
byte transfer @AH

@AL ,

Counter = RW0

byte search (@AH +) AL,
Counter = RW0
byte search (@AH ) AL,
Counter = RW0

byte fill @AH +

AL,

Counter = RW0

MOVSW/MOVSWI

MOVSWD

SCWEQ/SCWEQI

SCWEQD

FILSW/FILSWI

5m + 6

word transfer @AH +

@AL +,

Counter = RW0
word transfer @AH

@AL ,

Counter = RW0

word search (@AH +) AL,
Counter = RW0
word search (@AH ) AL,
Counter = RW0

word fill @AH +

AL,

Counter = RW0

MB90210 Series

Table 26 Multiple Data Transfer Instructions [18 Instruction]

*1: 256 when 5 + imm8

5, imm8 is 0.

*2: 256 when 5 + imm8

5 + (a), imm8 is 0.

*3: (Number of transfer cycles)

(b)

*4: (Number of transfer cycles)

(c)

*5: The bank register specified by bnk is the same as that for the MOVS instruction.

Mnemonic

Operation

LH AH

C RMW

MOVM @A, @RLi, #imm8

*3 Multiple data transfer

byte ((A))

((RLi))

MOVM @A, eam, #imm8

3 +

*3 Multiple data transfer

byte ((A))

(eam)

MOVM

addr16, @RLi, #imm8

*3 Multiple data transfer

byte (addr16)

((RLi))

MOVM

addr16, @eam, #imm8

5 +

*3 Multiple data transfer

byte (addr16)

(eam)

MOVMW

@A, @RLi, #imm8

*4 Multiple data transfer

word ((A))

((RLi))

MOVMW

@A, eam, #imm8

3 +

*4 Multiple data transfer

word ((A))

(eam)

MOVMWaddr16, @RLi, #imm8

*4 Multiple data transfer

word (addr16)

((RLi))

MOVMWaddr16, @eam, #imm8

5 +

*4 Multiple data transfer

word (addr16)

(eam)

MOVM @RLi, @A, #imm8

*3 Multiple data transfer

byte ((RLi))

((A))

MOVM @eam, A, #imm8

3 +

*3 Multiple data transfer

byte (eam)

((A))

MOVM

@RLi, addr16, #imm8

*3 Multiple data transfer

byte ((RLi))

(addr16)

MOVM

@eam, addr16, #imm8

5 +

*3 Multiple data transfer

byte (eam)

(addr16)

MOVMW

@RLi, @A, #imm8

*4 Multiple data transfer

word ((RLi))

((A))

MOVMW

@eam, A, #imm8

3 +

*4 Multiple data transfer

word (eam)

((A))

MOVMW@RLi, addr16, #imm8

*4 Multiple data transfer

word ((RLi))

(addr16)

MOVMW@eam, addr16, #imm8

5 +

*4 Multiple data transfer

word (eam)

(addr16)

MOVM bnk: addr16,

bnk: addr16, #imm8

*3 Multiple data transfer

byte (bnk: addr16)

(bnk: addr16)

MOVMW

bnk: addr16,
bnk: addr16, #imm8

*4 Multiple data transfer

word (bnk: addr16)

(bnk: addr16)

MB90210 Series

PACKAGE DIMENSIONS

"A"

LEAD No.

(.031±.008)

0.80±0.20

0.30(.012)

0.25(.010)

22.30±0.40(.878±.016)

18.40(.724)REF

0.16(.006)

(.014±.004)

0.35±0.10

0.80(.0315)TYP

(.705±.016)

(.551±.008)

14.00±0.20

17.90±0.40

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

INDEX

0.15±0.05(.006±.002)

(STAND OFF)

0.05(.002)MIN

3.35(.132)MAX

(.642±.016)

16.30±0.40

REF

12.00(.472)

Details of "B" part

0 10°

Details of "A" part

0.18(.007)MAX

0.58(.023)MAX

0.10(.004)

"B"

1994 FUJITSU LIMITED F80010S-3C-2

(Mounting height)

0.20

+0.50

+.020
.008

.006

+.018

+0.45
0.15

(.0315±.008)

(.878±.010)

(STAND OFF)

(.057±.008)

0.35±0.10

(.941±.012)

20.00

.787

.551

14.00

Ø8.89(.350)TYP

0.80±0.20

22.30±0.25

1.45±0.20

(.014±.004)

0.80(.0315)TYP

18.40(.724) REF

23.90±0.30

(.006±.002)

0.15±0.05

3.30(.130)MAX

0.05(.002)MIN

REF

12.00(.472)

(.642±.010)

16.30±0.25

(.705±.012)

17.90±0.30

INDEX AREA

1994 FUJITSU LIMITED F80018SC-1-2

(Mounting height)

80-pin Plastic QFP

(FPT-80P-M06)

Dimensions in mm (inches)

80-pin Ceramic QFP

(FPT-80C-C02)

MB90210 Series

FUJITSU LIMITED

For further information please contact:

Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329

http://www.fujitsu.co.jp/

North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608
Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220

http://www.fmap.com.sg/

F9710

FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.

Part Number MB90210

Document Outline