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DS07-12551-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

8-bit Proprietary Microcontrollers

CMOS

MC-8L MB89051 Series

MB89F051/MB89051

DESCRIPTION

The MB89051 series is a general-purpose, single-chip microcontroller that features a compact instruction set and
contains a range of peripheral function set and timers, serial interface, a PWM timer, the USB hub function and
the USB function. The USB hub function, in particular, supports five down ports (one of them is dedicated to an
internal function) allowing them to interface with other USB devices. The microcontrollers also contain one USB
function channel to support full speed.

FEATURES

· Package type

64-pin LQFP Package (0.65 mm pitch)

· High-speed operations at low voltage

Minimum execution time : 0.33

s (Automatically generates a 12 MHz main clock and a 48 MHz USB interface

synchronization clock with an externally supplied 6 MHz clock and the internal PLL circuit.)

(Continued)

Package

64-pin plastic LQFP

(FPT-64P-M09)

MB89051 Series

· F

MC-8L CPU core

Instruction set that is optimum to the controllers
-Multiplication and division instructions
-16-bit arithmetic operations
-branch instructions by bit testing
-bit manipulation instructions, etc.

· PLL clock control

The internal PLL clock circuit allows the use of low-speed clocks which are advantageous to noise character-
istics.
(6 MHz externally-supplied clock

12 MHz internal system clock)

· Various timers

8-bit PWM timer (can be used as either 8-bit PWM timer 2 channels or PPG timer 1 channel)
Internal 21-bit timebase timer

· Internal USB transceiver circuit (Compatible with full and low speeds)
· USB hub

USB function Compliant to USB Protocol Revision 1.0
Five downstream port channels (One of these channels is dedicated to a function.)
Automatically responds to all USB protocols by hardware.
Descriptor configuration is provided as ROM data for automatic responding by hardware (Vender ID and product
ID) .
String data is not supported.
Allows switching between BUS power supply and own power supply mode.
Power supply to the USB down port is controlled port by port.

· USB function

USB function Compliant to USB Protocol Revision 1.0
Support for full speed when using hub
Support for both low and full speeds when using function
Allows four endpoints to be specified at maximum.
Types of transfer supported: control/interrupt/bulk/isochronous
Built-in DMAC (Maps the buffer for each endpoint on to the internal RAM to directly access the memory for
function's send and receive data.)

· UART/SIO, SIO Serial Interface

Built-in UART/SIO function (selectable by switching)

1 channel

Built-in SIO (3.3 V)

2 channels

· I

C interface*

Supports Philips I

C bus standards

Uses a two-wire data transfer protocol
Master/slave send/receive

· External interrupt

External interrupt (level detection

7 channels)

Seven inputs are independent of one another and can also be used for resetting from low-power consumption
mode (the L-level detection feature available) .

· Clock output functions

Able for 12 MHz*

and 6 MHz*

clocks to output. (dedicated pins, 3 V)

· Low power consumption (standby mode supported)

Stop mode (There is almost no current consumption since oscillation stops.)
Sleep mode (This mode stops the running CPU.)

(Continued)

MB89051 Series

(Continued)

· A maximum of 41 general-purpose I/O ports

General-purpose I/O ports (CMOS) : 37 (7 of 3 V ports)
General-purpose I/O ports (Nch open drain) : 4

· Power supply

Supply voltage: 3.3 V

0.3 V or 5.0 V

0.5 V

· Operating temperature

C (When the USB function is not in use.)

C to

C (When the USB function is in use.)

*1 : I

C license

The customer is licensed to use Philips I

C patent when using this product in an I

C system that complies with

the Philips I

C standard specifications.

*2 : When an external supply clock is at 6 MHz.

MB89051 Series

PRODUCT LINEUP

* : When external supply clock is at 6 MHz.

Part number

MB89051

MB89F051

Parameter

ROM size

32 KB

32 KB (FLASH)

RAM size

2 KB

Package

LQFP-64 (FPT-64P-M09)

Others

MASK product

FLASH product/EVA product

CPU functions

Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Interrupt processing time

: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 0.33

s (6 MHz)

: 3

s (6 MHz)

General-
purpose ports

General purpose I/O ports (37 : CMOS (7 of 3 V ports ) , 4 : Nch open drain)

USB hub

Upstream port : 1 channel
Downstream port : 5 channels (One is dedicated to an internal function.)
Port power supply control method : By individual port
Allows selection between own power supply and bus power supply

USB function

Supports full speed : when using hub
Supports full and low speeds : when using function
End point max 4
Built-in DMAC (Can be set to DMA transfer to the internal RAM)

PWM timer

8-bit PWM timer operation 2 channels (can also be used as a PPG 1 channel timer)

UART

SIO

Allows switching between UART (clock-synchronous/asynchronous data transfer allowed)
and SIO (simple serial transfer).

SIO

SIO (simple serial)

2 channels (3 V)

C interface

One channel. Supports Phillips I

C bus standards. Uses a 2-wire protocol for communications

with other devices.

Timebase
timer

21-bit timebase timer

Clock output

Allows clock output of 12 MHz* and 6 MHz* (3 V)

Standby mode

Sleep mode and Stop mode

Peripheral functions

MB89051 Series

DIFFERENCES AMONG PRODUCTS

Memory Size

· Before evaluating using the FLASH product, it is necessary to confirm its differences from the product that will

actually be used.

Current Consumption

· When operating at low speed, FLASH products will consume more current than mask ROM products. However,

in sleep/stop mode the current consumption is the same.

· For detailed information on each package, see "

PACKAGE DIMENSIONS"

USB Pull-up Resistor control

· Remains in high impedance state until USB connection take place. Before the USB connection, use USBP

pin output to control pull-up resistance by software.

The example of connection

1.5 k

3.3 V

Host PC

MB89051 series

RPVP pin

RPVM pin

USBP pin

MB89051 Series

PIN ASSIGNMENT

(TOP VIEW)

(FPT-64P-M09)

P34/INT4/SCK1

P35/INT5/SCK2

P36/INT6/SO2

P37/INT7/SI2

CLK1

CLK2

P40/POW5

P41/POW2

P42/POW3

P43/POW4

P44/UCK

P45/UO

P46/UI/PWM1

P47/PWM2

MOD2

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P53/SDA

P54/SCL

RST

MOD0

MOD1

P27

P26

P25

P24

P23

P22

P21

P20

P33/INT3/SO1

P32/INT2/SI1

P31/INT1

D4VM

D4VP

D3VM

D3VP

D2VM

D2VP

D5VM

D5VP

USBP

RPVM

RPVP

MB89051 Series

PIN DESCRIPTION

(Continued)

Pin No.

Pin name

Circuit

type

Function

P34/INT4/

SCK1

General-purpose CMOS I/O pin
The external interrupt input is a hysteresis input. (Level detection)
SIO1 clock I/O

P35/INT5/

SCK2

General-purpose CMOS I/O pin
The external interrupt input is a hysteresis input. (Level detection)
SIO2 clock I/O

P36/INT6/

SO2

General-purpose CMOS I/O pin
The external interrupt input is a hysteresis input. (Level detection)
SIO2 serial data output

P37/INT7/SI2

General-purpose CMOS I/O pin
The external interrupt input is a hysteresis input. (Level detection)
SIO2 serial data input

CLK1

6 MHz clock output pin (When external supply clock is at 6 MHz.)

CLK2

12 MHz clock output pin (When external supply clock is at 6 MHz.)

P40/POW5

General-purpose CMOS I/O pin
This pin also serves as USB Down Port power control signal.

P41/POW2

General-purpose CMOS I/O pin
This pin also serves as USB Down Port power control signal.

P42/POW3

General-purpose CMOS I/O pin
This pin also serves as USB Down Port power control signal.

P43/POW4

General-purpose CMOS I/O pin
This pin also serves as USB Down Port power control signal.

P44/UCK

General-purpose CMOS I/O pin
UART/S10 clock I/O

P45/UO

General-purpose CMOS I/O pin
UART/S10 serial data output

P46/UI/

PWM1

Nch open drain general-purpose I/O pin
UART/S10 serial data input
PWM timer

Power supply pin (GND)

P47/PWM2

Nch open drain general-purpose I/O pin
PWM timer

MOD2

An operating mode designation pin. Connect directly to Vss.

P53/SDA

Nch open drain general-purpose I/O pin
Also serve as I

C interface data input/output pin.

P54/SCL

Nch open drain general-purpose I/O pin
Also serve as I

C interface clock input/output pin.

RST

Reset pin (Reset on the negative logic low level.)

MOD0

An operating mode designation pin. Connect directly to Vss.

MOD1

An operating mode designation pin. Connect directly to Vss.

MB89051 Series

* : For output only on the emulator.

(Continued)

Pin No.

Pin name

Circuit

type

Function

Pins for the connection of crystal oscillation circuit.(6 MHz)

Power supply pin (GND)

P27

General-purpose CMOS I/O pin*

P26

General-purpose CMOS I/O pin*

P25

General-purpose CMOS I/O pin*

P24

General-purpose CMOS I/O pin*

P23

General-purpose CMOS I/O pin*

P22

General-purpose CMOS I/O pin*

P21

General-purpose CMOS I/O pin*

P20

General-purpose CMOS I/O pin*

P17

General-purpose CMOS I/O pin

P16

General-purpose CMOS I/O pin

P15

General-purpose CMOS I/O pin

P14

General-purpose CMOS I/O pin

P13

General-purpose CMOS I/O pin

P12

General-purpose CMOS I/O pin

P11

General-purpose CMOS I/O pin

P10

General-purpose CMOS I/O pin

P07

General-purpose CMOS I/O pin

P06

General-purpose CMOS I/O pin

P05

General-purpose CMOS I/O pin

P04

General-purpose CMOS I/O pin

P03

General-purpose CMOS I/O pin

P02

General-purpose CMOS I/O pin

P01

General-purpose CMOS I/O pin

P00

General-purpose CMOS I/O pin

Power supply pin.

Connect an external capacitor of 0.1

F. When using with 3.3 V power

supply, connect this pin with the Vcc pin to set to 3.3 V input.

RPVP

USBDRV USB route port

RPVM

USBDRV USB router port

USBP

USB pull-up resistance connection pin.

D5VP

USBDRV USB down port 5

D5VM

USBDRV USB down port 5

MB89051 Series

(Continued)

Pin No.

Pin name

Circuit

type

Function

D2VP

USBDRV USB down port 2

D2VM

USBDRV USB down port 2

D3VP

USBDRV USB down port 3

D3VM

USBDRV USB down port 3

D4VP

USBDRV USB down port 4

D4VM

USBDRV USB down port 4

P31/INT1

General-purpose CMOS I/O pin
External interrupt input (Hysteresis input (level detection) )

P32/INT2/SI1

General-purpose CMOS I/O pin
External interrupt input (Hysteresis input (level detection) )
SIO1 serial data input

P33/INT3/

SO1

General-purpose CMOS I/O pin
External interrupt input (Hysteresis input (level detection) )
SIO1 serial data output

MB89051 Series

HANDLING DEVICES

Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to input or output pins
other than the medium- and high-voltage pins or if voltage higher than the rating is applied between Vcc and Vss.

When latchup occurs, power supply current increases rapidly and might thermally damage elements.When
using, take great care not to exceed the absolute maximum ratings.

Also take care to prevent the analog input from exceeding the digital power supply (Vcc) when the power supply
to the analog power system is turned on and off.

Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions and latchup leading to permanent damage to the
pins.These unused pins should be connected to a pullup or pulldown resistance of at least 2 k

between the

pin and the power supply.

Unused I/O pins should be placed in output state to leave it open or pins that are in input state should be handled
the same as unused input pins.

Note to noise in the External Reset Pin (RST)

If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunc-
tions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).

Power Supply Voltage Fluctuations

Although Vcc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that Vcc ripple fluctuations (P-P
value) will be less than 10% of the standard V

value at the commercial frequency (50 Hz to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.

Note on the clock during operation

This microcontroller uses a PLL for generating the main clock signal. If the oscillator is removed or the clock
input stops during operation, therefor, the microcontroller may keep on operating at the free-running frequency
of the self-oscillation circuit in the PLL. The operation is not however guaranteed.

About port 2 (P20 to P27)

Port 2 serves as an output-only terminal on the emulator.

MB89051 Series

PROGRAMMING AND ERASING FLSH MEMORY

Flash Memory

The flash memory is located between 8000

and FFFF

in the CPU memory map and incorporates a flash

memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mark ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the CPU, providing an efficient method of updating program and data.

Flash Memory Features

· 32 Kbyte

8-bit configuration (16 K

8 K

8 K sectors)

· Automatic programming algorithm (Embedded Algorithm* : Equivalent to MBM29LV200)
· Includes an erase pause and restart function
· Data polling and toggle bit for detection of program/erase completion
· Detection of program/erase completion via CPU interrupt
· Compatible with JEDEC-standard command
· Sector Protection (sectors can be combined in any combination)
· No. of program/erase cycles : 10,000 (Min)

* : Embedded Algorithm is a trademark of Advanced Micro Devices.

Procedure for Programming and Erasing Flash Memory

Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flash memory, the program must first be copied from flash memory to RAM so that programming can be
performed without program access from flash memory.

Flash Memory Register

Control status register (FMCS)

Sector Configuration

The table below shows the sector configuration of flash memory and lists the addresses of each sector for both
during CPU access and a flash memory programming.

Sector configuration of flash memory

* : Programmer address

The programmer address is the address to be used instead of the CPU address when programming data from
a parallel flash memory programmer. Use the programmer address on programming or erasing using a general-
purpose parallel programmer.

Flash Memory

CPU Address

Programmer Address*

16 Kbytes

FFFF

to C000

1FFFF

to 1C000

8 Kbytes

BFFF

to A000

1BFFF

to 1A000

8 Kbytes

9FFF

to 8000

19FFF

to 18000

R/W

RDY

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

002E

000X00X0

R/W

INTE

RDYINT

Re-

served

Re-

served

Re-

served

Initial value

Address

MB89051 Series

BLOCK DIAGRAM

RPVP

RPVM

D2VP

D5VP

D2VM

D5VM

USB DRV

Dp2-5

Dp1

CMOS I/O Port

3 V CMOS I/O Port

CMOS out Port

CMOS I/O Port

Nch I/O Port

P40/POW5

P41/POW2

P42/POW3

P43/POW4

DMAC

P53/SDA, P54/SCL

MOD0 MOD1

RAM 2 KByte

MC - 8L CPU

ROM 32 K / FLASH 32 KByte

P20

P27*

P45/UO

P44/UCK

P47/PWM2

P46/UI/PWM1

P00

P07, P10

P17

SIO

RST

X0
X1

CLK2

3 V CLK Port

CLK1

I2C

SIO1

SIO2

P31/INT1

P32/INT2/SI1
P33/INT3/SO1
P34/INT4/SCK1
P35/INT5/SCK2
P36/INT6/SO2
P37/INT7/SI2

MOD2 USBP

UART

Nch I/O Port

Main clock oscillator

Clock control circuit

PLL circuit

Internal Bus

USB

Function

Circuit

Clock output

External interrupt (level)

Reset output

Power on

reset circuit

(watchdog

timer)

21-bit timebase timer

8 bit PWM

timer

Other pins

USB HUB

Circuit

* : Port 2 serves as an output-only terminal on the emulator.

MB89051 Series

CPU CORE

Memory Size

The MB89051 microcontroller offers a memory space of 64 Kbytes consisting of the I/O, RAM and ROM areas.
The memory space contains areas that are used for specific purposes, such as a general-purpose register and
a vector table.

· I/O area (addresses: 0000

through 007F

)

This area is assigned with the control and data registers, for example, of peripheral functions to be built in.
The I/O area is as accessible as the memory since the area is assigned to a part of the memory space.Direct
addressing also allows the area to be accessed faster.

· RAM area

As an internal data area, a static RAM is built in.
The internal RAM capacity varies with the product type.
The area 80

to FF

can be accessed at high speed with direct addressing.

The area 100H to 1FFH can be used a general-purpose register area. (The usable area is limited depending
on the product.)
When reset, RAM data becomes undefined.

· ROM area

As an internal program area, a ROM is built in.
The internal RAM capacity varies with the product type.
The area FFC0

to FFFF

should be used for a vector table, for example.

·
·
·
·

Memory map

MB89051

0000

0080

0100

0200

0880

8000

FFC0

FFFF

ROM

I/O

RAM

MB89F051

0000

0080

0100

0200

0880

8000

FFC0

FFFF

ROM

I/O

RAM

Access

prohibited

Vector table
(reset, interrupt and vector call instructions)

* : FLASH ROM

Access

prohibited

MB89051 Series

Registers

The MB89051 series has two types of registers; the registers dedicated to specific purposes in the CPU and
the general-purpose registers.
The dedicated registers are as follows:

The PS register can further be divided into the register bank pointer in the higher 8 bits (RP) and the condition
code register in the lower 8 bits (CCR). (See the diagram below.)

Program counter (PC)

: A 16-bit register to indicate locations where instructions are stored.

Accumulator (A)

A 16-bit register for temporary storage of operations. In the case of an 8-bit
data processing instruction, the lower one byte is used.

Temporary accumulator (T)

A 16-bit register which performs operations with the accumulator.In the case of
an 8-bit data processing instruction, the lower one byte is used.

Index register (IX)

: A 16-bit register for index modification.

Extra pointer (EP)

: A 16-bit register to point to a memory address.

Stack pointer (SP)

: A 16-bit register to indicate a stack area.

Program status (PS)

: A 16-bit register to store a register pointer or a condition code.

CCR

16 bits

: Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

FFFD

Initial value

Indeterminate

I-flag = 0, IL1, 0 = 11

Initial values for other bits are

indeterminate.

CCR

X011XXXX

bit15 bit14 bit13 bit12 bit11 bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

IL1

IL0

CCR initial value

H-flag

IL 1,0

I-flag

N-flag

Z-flag

V-flag

C-flag

X: Undefined

MB89051 Series

The RP points to the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule shown next.

The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at the time of an interrupt.

H flag

: The flag is set to "1" when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow

from bit 4 to bit 3. The bit is cleared to "0" in other instances.The flag is for decimal adjustment
instructions; do not use for other than additions and subtractions.

I flag

: Interrupt is enabled when this flag is set to "1." Interrupt is disabled when this flag is set to "0." The

flag is set to "0" when reset.

IL1, 0

Indicates the level of the interrupt currently enabled.An interrupt is processed only if its level is
higher than the value this bit indicates.

IL1

IL0

Interrupt level

High-low

Higher

Lower = no interruption

N flag

: The flag is set to "1" when an arithmetic operation results in setting of the MSB to "1" or is cleared

to "0" when the MSB is set to "1."

Z flag

: The flag is set to "1" when an arithmetic operation results in "0" or is set to "0" in other instances.

V flag

: The flag is set to "1" when an arithmetic operation results in two's complement overflow or is

cleared to "0" if no overflow occurs.

C flag

: The flag is set to "1" when an arithmetic operation results in a carry from bit 7 or in a borrow to bit

7. The flag is cleared to "0" if neither of them occurs. In the case of a shift instruction, the flag is
set to the shift-out value.

Rule for Conversion of Actual Addresses in the General-purpose Register Area

"0"

"1"

A15 A14 A13 A12 A11 A10

Generated address

RP higher bits

OP code lower bits

MB89051 Series

I/O MAP

(Continued)

Address

Register

name

Register description

Read/write

Initial value

PDR0

Port 0 data register

R/W

XXXXXXXX

DDR0

Port 0 direction register

0 0 0 0 0 0 0 0

PDR1

Port 1 data register

R/W

XXXXXXXX

DDR1

Port 1 direction register

0 0 0 0 0 0 0 0

PDR2

Port 2 data register

R/W

0 0 0 0 0 0 0 0

Reserved area

DDR2

Port 2 direction register

R/W

0 0 0 0 0 0 0 0

SYCC

System clock control register

R/W

XXX

STBC

Standby control register

R/W

0 0 0 1 XXXX

WDTC

Watchdog timer control register

R/W

XXXXXXXX

TBTC

Timebase timer control register

R/W

0 0 XXX 0 0 0

Vacancy

PDR3/USBP

Port 3 data register/Pull-up register for USB

R/W

XXXXXXXX

DDR3/USBPC

Port 3 data direction register/
Pull-up control register for USB

R/W

0 0 0 0 0 0 0 0

Reserved area

Vacancy

PDR4

Port 4 data register

R/W

XXXXXXXX

DDR4

Port 4 direction register

R/W

0 0 0 0 0 0 0 0

PDR5

Port 5 data register

R/W

XXX 1 1 XXX

to 15

Reserved area

to 20

Vacancy

PURR0

Port 0 pullup option setting register

R/W

1 1 1 1 1 1 1 1

PURR1

Port 1 pullup option setting register

R/W

1 1 1 1 1 1 1 1

PURR2

Port 2 pullup option setting register

R/W

1 1 1 1 1 1 1 1

PURR3

Port 3 pullup option setting register

R/W

1 1 1 1 1 1 1 X

PURR4

Port 4 pullup option setting register

R/W

1 1 1 1 1 1 1 1

Reserved area

CTR1

PWM control register 1

R/W

0 0 0 0 0 0 0 0

CTR2

PWM control register 2

R/W

0 0 0 X 0 0 0 0

CTR3

PWM control register 3

R/W

X 0 0 0 XXXX

CMR1

PWM compare register 1

XXXXXXXX

CMR2

PWM compare register 2

XXXXXXXX

CKR

Clock output control register

R/W

XXXXXXX 0 0

SCS

Serial clock switching register

R/W

XXXXXXX 0

MB89051 Series

(Continued)

Address

Register

name

Register description

Read/write

Initial value

FMCS

Flash memory control status register
(Only built-in Flash Memory products)

R, R/W

0 0 0 X 0 0 X 0

SMC1

Serial mode control register 1

R/W

0 0 0 0 0 0 0 0

SMC2

Serial mode control register 2

R/W

0 0 0 0 0 0 0 0

SSD

Serial status and control register

0 0 0 0 1 XXX

SIDR/SODR

Serial input/serial output data register

R/W

XXXXXXXX

SRC

Serial rate control register

R/W

XXXXXXXX

IBSR

C bus status register

0 0 0 0 0 0 0 0

IBCR

C bus control register

R/W

0 0 0 1 1 0 0 0

ICCR

C clock regeister

R/W

0 X 0 XXXXX

IADR

C address register

R/W

XXXXXXXX

IDAR

C data register

R/W

XXXXXXXX

Vacancy

SMR1

Serial mode register 1

R/W

0 0 0 0 0 0 0 0

SDR1

Serial data register 1

R/W

XXXXXXXX

EIE

External interrupt control register

R/W

0 0 0 0 0 0 0 0

EIF

External interrupt flag register

R/W

XXXXXXX 0

, 3F

Vacancy

HMDR

HUB mode register

R/W

1 0 XXXXX 0

HDSR1

Hub descriptor register 1

R/W

XXXXXXXX

HDSR2

Hub descriptor register 2

R/W

XXXXXXXX

HDSR3

Hub descriptor register 3

R/W

XXXXXXXX

HSTR

Hub status register

R/W

0 0 0 0 0 0 0 0

OCCR

Over current register

R/W

0 XXX 0 0 0 0

DADR

Descriptor ROM address register

R/W

XXXXXXXX

Reserved area

, 49

Vacancy

SMR2

Serial mode register 2

R/W

0 0 0 0 0 0 0 0

SDR2

Serial data register 2

R/W

XXXXXXXX

, 4D

Vacancy

HDSR4

Hub descriptor register 4

R/W

0 0 0 0 0 1 01

Vacancy

UMDR

USB reset mode register

R/W

1 0 0 0 XX 0 0

DBAR

DMA base address register

R/W

XXXXXXXX

TDCR0

Transfer data count register 0

R/W

X 0 0 0 0 0 0 0

TDCR1

Transfer data count register 1

R/W

X 0 0 0 0 0 0 0

Reserved area

TDCR21

Transfer data count register 2

R/W

X 0 0 0 0 0 0 0

MB89051 Series

(Continued)

· Information about read/write

R/W

Read/write enabled, R

Read only, W

Write only

· Information about initial values

0: The initial value of this bit is "0".
1: The initial bit of this bit is "1".
X: The initial value of this bit is undefined.

Note : Vacancies and reserved spaces are not for use.

Address

Register

name

Register description

Read/write

Initial value

Reserved area

TDCR3

Transfer data count register 3

R/W

X 0 0 0 0 0 0 0

UCTR

USB control register

R/W

0 0 0 0 0 0 0 0

USTR1

USB status register 1

R/W

0 0 0 0 0 0 0 0

USTR2

USB status register 2

XXXXXX 0 0

UMSKR

USB interrupt mask register

R/W

0 0 0 0 0 0 0 0

UFRMR1

USB frame status register 1

XXXXXXXX

UFRMR2

USB frame status register 2

XXXXXXXX

EPER

USB endpoint enable register

R/W

XXXX 0 0 0 1

EPBR0

End point setup register 0

R/W

X 0 0 0 0 0 0 0

EPBR11

Endpoint setup register 11

R/W

XX 0 0 0 0 XX

EPBR12

Endpoint setup register 12

R/W

X 0 0 0 0 0 0 0

EPBR21

Endpoint setup register 21

R/W

XX 0 0 0 0 XX

EPBR22

Endpoint setup register 22

R/W

X 0 0 0 0 0 0 0

EPBR31

Endpoint setup register 31

R/W

XX 0 0 0 0 XX

EPBR32

Endpoint setup register 32

R/W

X 0 0 0 0 0 0 0

Reserved area

to 78

Vacancy

Reserved area

Vacancy

ILR1

Interrupt level setting register 1

1 1 1 1 1 1 1 1

ILR2

Interrupt level setting register 2

1 1 1 1 1 1 1 1

ILR3

level setting register 3

1 1 1 1 1 1 1 1

ILR4

Interrupt level setting register 4

1 1 1 1 1 1 1 1

Reserved area

MB89051 Series

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

0 V)

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

*1 : V

should not exceed the specified ratings. However, if the maximum current to /from an input is limited by some

means with external components, the I

CLAMP

rating supersedes the V

rating.

*2 : Maximum output current is defined as the peak value at one curresponding pin.

*3 : Average output current is defined as the average current flowing through one corresponding pin in an internal

of 100 ms. (Average value : operating current

operating duty)

Parameter

Symbol

Rating

Unit

Remarks

Min

Max

Power supply voltage

0.3

6.0

Input voltage

0.3

Other than P31 to P37, P46,
P47, P53, P54*

0.3

3.3

P31 to P37

0.3

6.0

P46,P47,P53, P54*

Output voltage

0.3

Other than P31 to P37, P46,
P47, P53, P54,
CLK1, CLK2, USBP

0.3

3.6

P31 to P37, CLK1, CLK2,
USBP

0.3

6.0

P46, P47, P53, 54

Maximum clamp current

CLAMP

2.0

Total maximum clamp cuurent

CLAMP

"L" level maximum output current

Normal output*

"L" level average output current

OLAV

Normal output*

"L" level total maximum output current

100

Total normal output

"L" level total average output current

OLAV

Total normal output*

"H" level maximum outputcurrent

Normal output*

"H" level average outputcurrent

OHAV

Normal output*

"H" level total maximum output current

Total normal output

"H" level maximum outputcurrent

Total output of P31 to P37,
CLK1, CLK2, USBP.

"H" level average total output currnt

OHAV

Total normal output*

Total output of P31 to P37,
CLK1, CLK2 and USBP.*

Power consumption

300

Operating temperature

Storage temperature

Tstg

150

MB89051 Series

*4 : Average total output current is defined as the average current flowing through all corresponding pins in an

internal of 100 ms.

*5 :

Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P40 to P45

Use within recommended operating conditions.

Use at DC voltage (current)

The

B signal should always be applied with a limiting resistance placed between the

B signal and the

microcontroller.

The value of the limiting resistance should be set so that when the

B signal is applied the input current

to the microcontroller pin does not exceed rated values, either instaneously or for prolonged periods.

Note that when the microcontroller drive current is low, such as in the power saving modes, the

B input

potentional may pass through the protective diode and increase the potentional at the V

pin, and this may

affect other devices.

Note that if a

B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply

is provided from the pins, so that incomplete operation may result.

Note that if the

B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on result.

Care must be taken not to leave the

B input pin open.

Note that analog system input pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.)

cannot accept

B signl input.

Sample recommended circuits :

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

Input/Output Equivalent circuits

Protective diode

Limiting

resistance

+B input (0 V to 16 V)

MB89051 Series

Recommended Operating Conditions

0 V)

*: Use either a ceramic capacitor or a capacitor with similar frequency characteristics.The capacity of the smoothing

capacitor for the Vcc pin should be greater than that of the Cs.When using with a supply voltage of 3.3 V, connect
pin C with Vcc to input 3.3 V.

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

Power supply voltage

4.5

5.5

At V

5.0 V

3.0

3.6

At V

3.3 V*

Operating temperature

When the USB function is not
in use.

When the USB function is in
use

Smoothing capacitor

0.1

1.0

At V

5.0 V*

Series resistance

When the USB function is in
use

RPVM

RPVP

D2VM

D2VP

D3VM

D3VP

D4VM

D4VP

D5VM

D5VP

C and USB Port Connection Diagram

MB89051 Series

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

5.5

5.0

4.0

3.0

2.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0 11.0 12.0 13.0

4.0

2.0

0.8

0.4

0.33

4.5

3.6

Guaranteed operation range

Operating voltage V

(V)

CPU operating frequency (F

MHz)

(At instruction cycle 4/ F

)

Minimum execution time (instruction cycle) (

However, F

= clock frequency (Fc)

Operating voltage vs. Operating frequency

MB89051 Series

DC Characteristics (Power supply votage : 5.0 V)

5.0 V, V

0 V, T

C to

(Continued)

Parameter

Sym

bol

Pin

Condition

Value

Unit

Remarks

Min

Typ

Max

"H" level
Input voltage

P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P53, P54,
MOD0,
MOD1,
MOD2

0.7 V

0.3

P31 to P37

2.5

3.3

3 V

IHS

RST,
UCK, UI

0.8 V

0.3

INT1 to INT7,
SCK1, SCK2,
SI1, SI2

2.9

3.3

3 V

IHI2C

SCL, SDA

0.8 V

5.5

"L" level
Input voltage

P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P53, P54,
MOD0,
MOD1,
MOD2

0.3

0.3 V

P31 to P37

0.3

0.9

3 V

ILS

RST,
INT1 to INT7,
UCK, UI

0.3

0.2 V

INT1 to INT7,
SCK1, SCK2,
SI1, SI2

0.3

0.6

3 V

ILI2C

SCL, SDA

0.3

0.3 V

Open-drain out-
put application
voltage

P53, P54

0.3

"H" level
Output voltage

P00 to P07,
P10 to P17,
P20 to P24,
P40 to P47

2.0 mA

4.0

P31 to P37,
CLK1, CLK2

1.0 mA

2.6

3.6 V

3 V

USBP

2.4 mA

3.0

3.6 V

USB Pull up

MB89051 Series

(Continued)

5.0 V, V

0 V, T

C to

Parameter

Sym

bol

Pin

Condition

Value

Unit

Remarks

Min

Typ

Max

"L" level
Output voltage

P00 to P07,
P10 to P17,
P20 to P24,
P40 to P47,
P53, P54,
RST

4.0 mA

0.4

P31 to P37,
CLK1, CLK2

1.0 mA

0.4

3 V

Input leakage
current
(Hi-Z output
leakage current)

P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,

0.0 V

When no pullup
re sistance is
speci fied

CLK1, CLK2

USBP

Open-drain out-
put leakage cur-
rent

LIOD

P53, P54

0.0 V

5.5 V

Pullup
resistance

PULL

P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
P53, P54,
RST

0.0 V

100

RST is excluded
when pullup
resistance
available is
specified.

Power supply
current

12.0 MHz,

5.0 V,

inst

0.333

MB89F051

MB89051

CCS1

12.0 MHz,

5.0 V,

inst

0.333

Sleep mode

CCH

Stop

Input
capacitance

Other than
V

, V

and

1 MHz

MB89051 Series

DC Characteristics (Power supply votage : 3.3 V)

3.3 V, V

0 V, T

C to

(Continued)

Parameter

Sym

bol

Pin

Condition

Value

Unit

Remarks

Min

Typ

Max

"H" level
Input voltage

P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
P53, P54,
MOD0, MOD1,
MOD2

0.7 V

0.3

IHS

RST,
UCK, UI,
INT1 to INT7,
SCK1, SCK2,
SI1, SI2

0.8 V

0.3

IHI2C

SCL, SDA

0.8 V

5.5

"L" level
Input voltage

P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
P53, P54,
MOD0, MOD1,
MOD2

0.3

0.3 V

ILS

RST,
INT1 to INT7,
UCK, UI,
INT1 to INT7,
SCK1, SCK2,
SI1, SI2

0.3

0.2 V

ILI2C

SCL, SDA

0.3

0.3 V

Open-drain
output application
voltage

P53, P54

0.3

"H" level
Output voltage

P00 to P07,
P10 to P17,
P20 to P24,
P40 to P47

2.0 mA

2.6

P31 to P37,
CLK1, CLK2

1.0 mA

2.6

USBP

2.4 mA

3.0

USB Pull up,
Vcc

3.1 V to

3.6 V

MB89051 Series

(Continued)

3.3 V, V

0 V, T

C to

Parameter

Sym

bol

Pin

Condition

Value

Unit

Remarks

Min

Typ

Max

"L" level
Output voltage

P00 to P07,
P10 to P17,
P20 to P24,
P40 to P47,
P53, P54,
RST

4.0 mA

0.4

P31 to P37,
CLK1, CLK2

1.0 mA

0.4

Input leakage
current
(Hi-Z output
leakage current)

P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,

0.0 V

When no pullup
resistance is
specified

CLK1, CLK2

USBP

Open-drain
output leakage
current

LIOD

P53, P54

0.0 V

5.5 V

Pullup
resistance

PULL

P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
P53, P54,
RST

0.0 V

100

RST is excluded
when pullup
resistance
available is
specified.

Power supply
current

12.0 MHz,

3.3 V,

inst

0.333

MB89F051

MB89051

CCS1

12.0 MHz,

3.3 V,

inst

0.333

Sleep mode

CCH

Stop

Input
capacitance

Other than
Vcc and Vss

1 MHz

MB89051 Series

AC Characteristics

(1) Reset Timing

5.0 V, V

0 V, T

C to

Notes :

HCYL

is the oscillation cycle for the internal main clock.

If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause
malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external
reset pin (RST).

(2) Power-on reset

0 V, T

C to

Note : The power supply must be up within the selected oscillation stabilization time.

When the supply voltage needs to be varied while operating, it is recommended to smoothly start up the
voltage.

Parameter

Symbol

Condition

Value

Unit

Remarks

Min

Max

RST "L" pulse width

ZLZH

48 t

HCYL

Parameter

Symbol

Condition

Value

Unit

Remarks

Min

Max

Power supply rising time

0.066

Power supply cutoff time

OFF

Due to repeated
operations

RST

0.2 V

ZLZH

3.5 V

0.2 V

OFF

MB89051 Series

(3) Clock Timing

0 V, T

C to

(4) Instruction Cycle

0 V, T

C to

Parameter

Symbol Pin name Condition

Value

Unit

Remarks

Min

Typ

Max

Clock frequency

X0, X1

MHz

Clock cycle time

XCYL

X0, X1

166.6

Internal main clock
frequency

MHz

Twice the
Fc

Internal clock cycle

HCYL

83.3

XCYL

Parameter

Symbol

Value

Unit

Remarks

Instruction cycle
(Min execution time)

inst

, 8

, 64

When operating at F

= 12 MHz

inst

= 0.33

s (4

)

X0 and X1 Timing and Conditions

Clock Conditions

XCYL

0.2 V

When a crystal resonator is used

MB89051 Series

(5) UART Serial I/O Timing

5.0 V, V

0 V, T

C to

* : For information on t

inst

, see " (4) Instruction Cycle".

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Serial clock cycle time

SCYC

UCK

Internal shift

clock mode

2 t

inst

UCK

SLOV

UCK, UO

200

Valid UI

UCK

IVSH

UI, UCK

200

UCK

valid UI hold time

SHIX

UCK, UI

200

Serial clock "H" pulse width

SHSL

UCK

External

shift clock

mode

1 t

inst

Serial clock "L" pulse width

SLSH

1 t

inst

UCK

UO time

SLOV

UCK, UO

200

Valid UI

UCK

IVSH

UI, UCK

200

UCK

valid UI hold time

SHIX

UCK, UI

200

Internal shift clock mode

External shift clock mode

UCK

SCYC

IVSH

SLOV

SHIX

0.2 Vcc

0.8 Vcc

0.8 V

0.2 V

0.8 V

0.2 V

0.2 Vcc

0.8 Vcc

UCK

SLSH

SHSL

IVSH

SLOV

SHIX

0.2 V

0.2 Vcc

0.8 Vcc

0.8 V

0.2 V

0.8 V

0.2 V

0.8 V

MB89051 Series

(6) Serial I/O Timing

5.0 V, Vss

0V, T

C to

* : For information on t

inst

, see " (4) Instruction Cycle".

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Serial clock cycle time

SCYC

SCK1, SCK2

Internal

shift clock

mode

2 t

inst

SCK

SO time

SLOV

SCK1, SO1,

SCK2, SO2

200

Valid SI

SCK

IVSH

SCK1, SI1,

SCK2, SI2

200

SCK

Valid SI hold time

SHIX

SCK1, SI1,

SCK2, SI2

200

Serial clock "H" pulse width

SHSL

SCK1, SCK2

External

shift clock

mode

inst

Serial clock "L" pulse width

SLSH

SCK1, SCK2

inst

SCK

SO time

SLOV

SCK1, SO1,

SCK2, SO2

200

Valid SI

SCK

IVSH

SCK1, SI1,

SCK2, SI2

200

SCK

Valid SI hold time

SHIX

SCK1, SI1,

SCK2, SI2

200

Internal shift clock mode

External shift clock mode

0.6

2.9

0.6

SCYC

SLOV

IVSH

SHIX

SCK1
SCK2

SO1
SO2

SI1
SI2

0.6

2.9

0.6

2.9

0.6

SLSH

SHSL

SLOV

IVSH

SHIX

SCK1
SCK2

SO1
SO2

SI1
SI2

0.6

2.9

0.6

MB89051 Series

(8) I

C Timing

5.0 V, V

0 V, T

C to

*1 : For information on t

inst

, see " (4) Instruction Cycle".

*2 : m is defined in the ICCR CS 4 to CS 3 (bit 4 to bit 3) .
*3 : n is defined in the ICCR CS 2 to CS 0 (bit 2 to bit 0) .

Parameter

Sym

bol

Pin

Value

Unit

Remarks

Min

Max

Start condition output

STA

SCL,

SDA

inst

Master
mode

Stop condition output

STO

SCL,

SDA

inst

Master
mode

Start condition detect

STA

SCL,

SDA

inst

Stop condition detect

STO

SCL,

SDA

inst

Restart condition output t

STASU

SCL,

SDA

inst

Master
mode

Restart condition detect t

STASU

SCL,

SDA

inst

SCL output Low width

LOW

SCL

inst

Master
mode

SCL output High width

HIGH

SCL

inst

Master
mode

SDA output delay

SDA

inst

SDA output setup time
after interrupt

DOSU

SDA

inst

SCL input Low pulse
width

LOW

SCL

inst

SCL input High pulse
width

HIGH

SCL

inst

SDA input setup time

SDA

SDA hold time

SDA

Data transmit (master/slave)

Data receive (master/slave)

ACK

DOSU

LOW

STA

SDA

SCL

STASU

SDA

SCL

HIGH

LOW

DOSU

STO

ACK

MB89051 Series

PACKAGE DIMENSIONS

64-pin plastic LQFP

(FPT-64P-M09)

Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.

Dimensions in mm (inches)
Note : The values in parentheses are reference values.

2003 FUJITSU LIMITED F64018S-c-3-5

0.65(.026)

0.10(.004)

12.00±0.10(.472±.004)SQ

14.00±0.20(.551±.008)SQ

INDEX

0.32±0.05

(.013±.002)

0.13(.005)

0.145±0.055

(.0057±.0022)

"A"

.059

.004

+.008

0.10

+0.20

1.50

0~8°

0.25(.010)

(Mounting height)

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

Details of "A" part

(Stand off)

0.10(.004)

MB89051 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party's
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0303

FUJITSU LIMITED Printed in Japan

Part Number MB89F051

Document Outline