DS04-28220-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP For Video Applications
CMOS
3ch 8-bit 100 MSPS A/D Converter
MB40C348V
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DESCRIPTION
MB40C348V is a high-speed 3ch A/D converter using a fast CMOS technology.
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FEATURES
· Resolution
: 8 bit
· No. of AD channels
: 3 ch
· Linearity error
:
±
0.40
%
(typical)
· Maximum conversion rate
: 100 MSPS (minimum)
· Power supply voltage
: 3.3 V (typical : internal circuit)
· Digital input voltage range
: TTL level
· Digital output voltage range
: 3.3 V CMOS level
· Video Amp. input voltage range : 0.7 V
P
-
P
(typical)
· Video Amp. gain
: 1.9 double fixed
· A/D input capacity
: 15 pF (typical)
· Power dissipation
: 880 mW (typical)
· Additional features
: PLL circuit
Video Amp. circuit (1.9 double fixed gain, OFF operation is possible)
CLAMP circuit
V
RT
Amp. circuit (RGB 3 ch separate)
V
RB
Amp. circuit (RGB 3 ch common)
Overflow output
High impedance output, power down function
· Package
: LQFP120 (16 mm
×
16 mm, lead pitch : 0.5 mm)
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PACKAGE
120-pin plastic LQFP
(FPT-120P-M21)
MB40C348V
2
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PIN ASSIGNMENT
(TOP VIEW)
(FPT-120P-M21)
RV
IN
V
RB
GV
IN
GV
M
BV
IN
BV
M
V
REF
PCLP
AV
DD
AV
SS
RADIN
V
RBM
GADIN
V
ESD
BADIN
RV
RTM
GV
RTM
BV
RTM
RV
CLP
GV
CLP
BV
CLP
AV
SS
AV
DD
CS
CK
DATA
DV
SS
DV
DD
(MSB) BD
B7
BD
B6
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
PV
SS
PV
DD
HSYNC
HHOLD
PV
DD
LPF
PV
SS
R
REF
RV
RT
GV
RT
BV
RT
RV
M
AV
SS
AV
DD
DV
DD
DV
SS
OF
DSYNC
DSYNCB
COUT
EXPCLK
EXPCLKB
EXCLK
ADCLKA
ADCLKB
CLK
CLKB
DV
DD
DV
SS
AV
SS
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
BD
B5
BD
B4
BD
B3
BD
B2
BD
B1
(LSB) BD
B0
DV
SS
DV
DD
(MSB) BD
A7
BD
A6
BD
A5
BD
A4
BD
A3
BD
A2
BD
A1
(LSB) BD
A0
AV
DD
AV
SS
DV
SS
DV
DD
(MSB) GD
B7
GD
B6
GD
B5
GD
B4
GD
B3
GD
B2
GD
B1
(LSB) GD
B0
DV
DD
DV
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RD
A0
(LSB)
RD
A1
RD
A2
RD
A3
RD
A4
RD
A5
RD
A6
RD
A7
(MSB)
DV
DD
DV
SS
AV
SS
AV
DD
RD
B0
(LSB)
RD
B1
RD
B2
RD
B3
RD
B4
RD
B5
RD
B6
RD
B7
(MSB)
DV
DD
DV
SS
GD
A0
(LSB)
GD
A1
GD
A2
GD
A3
GD
A4
GD
A5
GD
A6
GD
A7
(MSB)
MB40C348V
3
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PIN DESCRIPTION
Note: The values in parentheses are standard.
(Continued)
Pin No.
Symbol
Description
9, 23, 47,
79, 107
AV
DD
Analog power supply (+3.3 V)
28, 38, 50,
59, 70, 82,
93, 106
DV
DD
Digital power supply (+3.3 V)
116, 119
PV
DD
PLL power supply pin (
+
3.3 V)
14
V
ESD
Digital input power supply for protect device (
+
3.3 V or
+
5 V)
10, 22, 48,
80, 91, 108
AV
SS
Analog power supply ground pin (0 V)
27, 37, 49,
60, 69, 81,
92, 105
DV
SS
Digital power supply ground pin (0 V)
114, 120
PV
SS
PLL power supply ground pin (0 V)
1
3
5
RV
IN
GV
IN
BV
IN
1.9 double Amp. input pin
11
13
15
RADIN
GADIN
BADIN
A/D converter input pin
This pin inputs directly is possible when 1.9 double Amp. OFF.
19
20
21
RV
CLP
GV
CLP
BV
CLP
Clamp voltage setting input pin
16
17
18
RV
RTM
GV
RTM
BV
RTM
Reference voltage output pin on top side
112
111
110
RV
RT
GV
RT
BV
RT
Reference voltage input pin on top side
12
V
RBM
Reference voltage output pin on bottom side (RGB 3 ch common)
2
V
RB
Reference voltage input pin on bottom side (RGB 3 ch common)
109
4
6
RV
M
GV
M
BV
M
Reference 1/2 voltage output pin (Add 0.1
µ
F for AV
SS
)
25
CK
Serial data transfer clock input pin
26
DATA
Serial data input pin
24
CS
Chip select signal input pin
It is possible to input to the shift register at CS falling
The content of the shift register is executed at CS rising
98
EXCLK
Clock input pin for A/D converter (CMOS level)
Fix to "L" level when unused.
MB40C348V
4
(Continued)
Note: The values in parentheses are standard.
Pin No.
Symbol
Description
99
EXPCLKB
Differential clock (negative-phase) input pin for A/D converter
Fix to "H" level when unused.
PECL level
100
EXPCLK
Differential clock (positive-phase) input pin for A/D converter
Fix to "L" level when unused.
8
PCLP
Clamp pulse input pin
113
R
REF
Internal current setting pin (Add 12 k
for AVss)
103
DSYNC
Delay sync signal output pin
102
DSYNCB
Inverted delay sync signal output pin
95
CLK
Clock output pin (See "
s
TIMING DIAGRAM ".)
94
CLKB
97
ADCLKA
96
ADCLKB
83 to 90
61 to 68
39 to 46
RD
A7
to RD
A0
GD
A7
to GD
A0
BD
A7
to BD
A0
Digital output pin (Port A)
RD
A7
, GD
A7
, BD
A7
: MSB
RD
A0
, GD
A0
, BD
A0
: LSB
71 to 78
51 to 58
29 to 36
RD
B7
to RD
B0
GD
B7
to GD
B0
BD
B7
to BD
B0
Digital output pin (Port B)
RD
B7
, GD
B7
, BD
B7
: MSB
RD
B0
, GD
B0
, BD
B0
: LSB
101
COUT
PLL counter output pin
115
LPF
External capacitor / resistor connection pin
117
HHOLD
Phase detector operation is hold by input "H" level
118
HSYNC
Horizontal sync signal input pin
7
V
REF
Internal voltage output pin (Add 3.3 µF for AVss)
104
OF
Overflow output pin ("H" level output at overflow)
MB40C348V
5
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BLOCK DIAGRAM
PCLP
RADIN
RV
IN
RV
CLP
HSYNC
HHOLD
COUT
LPF
EXPCLK
EXPCLKB
EXCLK
PV
SS
PV
DD
CK
CS
CLKB
CLK
DSYNCB
DSYNC
DV
SS
AV
SS
ADCLKB
ADCLKA
OF
BV
M
GV
M
RV
M
V
RBM
V
RB
RV
RT
DV
DD
AV
DD
V
ESD
RD
B0
RD
B7
RD
A0
RD
A7
DATA
AMP
+
CLAMP
+
A/D
×
1.9
A ch
B ch
8 bit A/D
8 bit A/D
8
8
8
8
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
11 bit Shift Reg
Counter
(12 bit)
Filter
×
3 ch
(1 bit)
2 bit
(1
1/8)
DIV
MUX
VCO
Delay
RESET
CP
PD
POL
2 bit (0
3 CLK)
CLK Delay
1/2
RV
RTM
PLL
Block
6 bit
(32 divide, 2CLK)
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