© 2005 Fairchild Semiconductor Corporation
DS500398
www.fairchildsemi.com
March 2001
Revised January 2005
NC7WZ240 T
i
nyLogi
c
UHS
Dua
l
Inver
ti
ng B
u
ff
er w
i
th 3-
ST
A
T
E O
u
t
put
s
NC7WZ240
TinyLogic
UHS Dual Inverting Buffer
with 3-STATE Outputs
General Description
The NC7WZ240 is a Dual Inverting Buffer with indepen-
dent active LOW enables for the 3-STATE outputs. The
Ultra High Speed device is fabricated with advanced
CMOS technology to achieve superior switching perfor-
mance with high output drive while maintaining low static
power dissipation over a broad V
CC
operating range. The
device is specified to operate over the 1.65V to 5.5V V
CC
operating range. The inputs and outputs are high imped-
ance when V
CC
is 0V. Inputs tolerate voltages up to 5.5V
independent of V
CC
operating range. Outputs tolerate volt-
ages above V
CC
when in the 3-STATE condition.
Features
s
Space saving US8 surface mount package
s
MicroPak
Pb-Free leadless package
s
Ultra High Speed; t
PD
2.3 ns typ into 50 pF at 5V V
CC
s
High Output Drive;
±
24 mA at 3V V
CC
s
Broad V
CC
Operating Range: 1.65V to 5.5V
s
Matches the performance of LCX when operated at
3.3V V
CC
s
Power down high impedance inputs/outputs
s
Overvoltage tolerant inputs facilitate 5V to 3V translation
s
Outputs are overvoltage tolerant in 3-STATE mode
s
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
TinyLogic
is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak
is a trademark of Fairchild Semiconductor Corporation.
Product
Package Description
Supplied As
Order
Package
Code
Number
Number
Top Mark
NC7WZ240K8X
MAB08A
WZ40
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
NC7WZ240L8X
MAC08A
U7
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
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2
NC7W
Z240
Logic Symbol
IEEE/IEC
Pin Descriptions
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
Z
=
3-STATE
Connection Diagrams
Pin Assignments for US8
(Top View)
Pin One Orientation Diagram
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignment for MicroPak
(Top Through View)
Pin Names
Description
OE
n
Enable Inputs for 3-STATE Outputs
A
n
Inputs
Y
n
3-STATE Outputs
Inputs
Output
OE
A
n
Y
n
L
L
H
L
H
L
H
L
Z
H
H
Z
3
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NC7WZ240
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 3)
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
) (Note 2)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
@V
IN
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
@V
OUT
<
0V
-
50 mA
DC Output Source/Sink Current (I
OUT
)
±
50 mA
DC V
CC
/Ground Current (I
CC
/I
GND
)
±
100 mA
Storage Temperature Range (T
STG
)
-
65
°
C to
+
150
°
C
Junction Lead Temperature under Bias (T
J
)
+
150
°
C
Junction Lead Temperature (T
L
)
(Soldering, 10 seconds)
+
260
°
C
Power Dissipation (P
D
) @
+
85
°
C
250 mW
Supply Voltage Operating (V
CC
)
1.65V to 5.5V
Supply Voltage Data Retention (V
CC
)
1.5V to 5.5V
Input Voltage (V
IN
)
0V to 5.5V
Output Voltage (V
OUT
)
Active State
0V to V
CC
3-STATE
0V to 5.5V
Operating Temperature (T
A
)
-
40
°
C to
+
85
°
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
@ 1.8V, 0.15V, 2.5V
±
0.2V
0 ns/V to 20 ns/V
V
CC
@ 3.3V
±
0.3V
0 ns/V to 10 ns/V
V
CC
@ 5.0V
±
0.5V
0 ns/V to 5 ns/V
Thermal Resistance (
JA
)
250
°
C/W
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
T
A
=
-
40
°
C to
+
85
°
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
V
IH
HIGH Level Input Voltage
1.65 to 1.95 0.75 V
CC
0.75 V
CC
V
2.3 to 5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input Voltage
1.65 to 1.95
0.25 V
CC
0.25 V
CC
V
2.3 to 5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output Voltage
1.65
1.55
1.65
1.55
V
2.3
2.2
2.3
2.2
V
IN
=
V
IH
I
OH
=
-
100
µ
A
3.0
2.9
3.0
2.9
or V
IL
4.5
4.4
4.5
4.4
1.65
1.29
1.52
1.29
V
I
OH
=
-
4 mA
2.3
1.9
2.15
1.9
V
IN
=
V
IH
I
OH
=
-
8 mA
3.0
2.4
2.80
2.4
or V
IL
I
OH
=
-
16 mA
3.0
2.3
2.68
2.3
I
OH
=
-
24 mA
4.5
3.8
4.20
3.8
I
OH
=
-
32 mA
V
OL
LOW Level Output Voltage
1.65
0.0
0.10
0.10
V
2.3
0.0
0.10
0.10
V
IN
=
V
IH
I
OL
=
100
µ
A
3.0
0.0
0.10
0.10
or V
IL
4.5
0.0
0.10
0.10
1.65
0.08
0.24
0.24
V
I
OL
=
4 mA
2.3
0.10
0.3
0.3
I
OL
=
8 mA
3.0
0.15
0.4
0.4
I
OL
=
16 mA
3.0
0.22
0.55
0.55
I
OL
=
24 mA
4.5
0.22
0.55
0.55
I
OL
=
32 mA
I
IN
Input Leakage Current
0 to 5.5
±
0.1
±
1
µ
A
V
IN
=
5.5V, GND
I
OZ
3-STATE Output Leakage
1.65 to 5.5
±
0.5
±
5
µ
A
V
IN
=
V
IH
or V
IL
0
V
OUT
5.5V
I
OFF
Power Off Leakage Current
0.0
1
10
µ
A
V
IN
or V
OUT
=
5.5V
I
CC
Quiescent Supply Current
1.65 to 5.5
1
10
µ
A
V
IN
=
5.5V, GND
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4
NC7W
Z240
Noise Characteristics
Note 4: Parameter guaranteed by design.
AC Electrical Characteristics
Note 5: Parameter guaranteed by design. t
OSLH
=
|t
PLHmax
-
t
PLHmin
|; t
OSHL
=
|t
PHLmax
-
t
PHLmin
|.
Note 6: C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at no output
loading and operating at 50% duty cycle. (See Figure 2.) C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
=
(C
PD
)(V
CC
)(f
IN
)
+
(I
CC
static).
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
Units
Conditions
(V)
Typ
Max
V
OLP
(Note 4) Quiet Output Maximum Dynamic V
OL
5.0
1.0
V
C
L
=
50 pF
V
OLV
(Note 4) Quiet Output Minimum Dynamic V
OL
5.0
1.0
V
C
L
=
50 pF
V
OHV
(Note 4) Quiet Output Minimum Dynamic V
OH
5.0
4.0
V
C
L
=
50 pF
V
IHD
(Note 4)
Minimum HIGH Level Dynamic Input Voltage
5.0
3.5
V
C
L
=
50 pF
V
ILD
(Note 4)
Maximum LOW Level Dynamic Input Voltage
5.0
1.5
V
C
L
=
50 pF
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
T
A
=
-
40
°
C to
+
85
°
C
Units
Conditions
Figure
(V)
Min
Typ
Max
Min
Max
Number
t
PLH
,
Propagation Delay
1.8
±
0.15
2.0
12.0
2.0
13.0
ns
C
L
=
15 pF
Figures
1, 3
t
PHL
A
n
to Y
n
2.5
±
0.2
1.0
7.5
1.0
8.0
R
D
=
1 M
3.3
±
0.3
0.8
5.2
0.8
5.5
S1
=
Open
5.0
±
0.5
0.5
4.5
0.5
4.8
t
PLH,
Propagation Delay
3.3
±
0.3
1.2
5.7
1.2
6.0
ns
C
L
=
50 pF
Figures
1, 3
t
PHL
A
n
to Y
n
5.0
±
0.5
0.8
5.0
0.8
5.3
R
D
=
500
S1
=
Open
t
OSLH
,
Output to Output Skew
3.3
±
0.3
1.0
1.0
ns
C
L
=
50 pF
Figures
1, 3
t
OSHL
(Note 5)
5.0
±
0.5
0.8
0.8
R
D
=
500
S1
=
Open
t
PZL
,
Output Enable Time
1.8
±
0.15
3.0
14.0
3.0
15.0
ns
C
L
=
50 pF
Figures
1, 3
t
PZH
2.5
±
0.2
1.8
8.5
1.8
9.0
R
D
, R
U
=
500
3.3
±
0.3
1.2
6.2
1.2
6.5
S1
=
GND for t
PZH
5.5
±
0.5
0.8
5.5
0.8
5.8
S1
=
V
I
for t
PZL
V
I
=
2 x V
CC
t
PLZ
,
Output Disable Time
1.8
±
0.15
2.5
12.0
2.5
13.0
ns
C
L
=
50 pF
Figures
1, 3
t
PHZ
2.5
±
0.2
1.5
8.0
1.5
8.5
R
D
, R
U
=
500
3.3
±
0.3
0.8
5.7
0.8
6.0
S1
=
GND for t
PZH
5.0
±
0.5
0.3
4.7
0.3
5.0
S1
=
V
I
for t
PZL
V
I
=
2 x V
CC
C
IN
Input Capacitance
0
2.5
pF
C
OUT
Output Capacitance
5.0
4
C
PD
Power Dissipation Capacitance
3.3
10
pF
(Note 6)
Figure 2
5.0
12
5
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NC7WZ240
AC Loading and Waveforms
C
L
includes load and stray capacitance
Input PRR
=
1.0 MHz; t
w
=
500 ns
FIGURE 1. AC Test Circuit
Input
=
AC Waveform; t
r
=
t
f
=
1.8 ns;
PRR
=
10 MHz; Duty Cycle
=
50%
FIGURE 2. I
CCD
Test Circuit
FIGURE 3. AC Waveforms
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6
NC7W
Z240
Tape and Reel Specification
Tape Format for US8
TAPE DIMENSIONS inches (millimeters)
Tape Format for MicroPak
TAPE DIMENSIONS inches (millimeters)
Package
Tape
Number
Cavity
Cover Tape
Designator
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
K8X
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
Package
Tape
Number
Cavity
Cover Tape
Designator
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
L8X
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
7
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NC7WZ240
Tape and Reel Specification
(Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
A
B
C
D
N
W1
W2
W3
8 mm
7.0
0.059
0.512
0.795
2.165
0.331
+
0.059/
-
0.000
0.567
W1
+
0.078/
-
0.039
(177.8)
(1.50)
(13.00)
(20.20)
(55.00)
(8.40
+
1.50/
-
0.00)
(14.40)
(W1
+
2.00/
-
1.00)
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8
NC7W
Z240
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
9
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NC7WZ240 T
i
nyLogi
c
UHS
Dua
l
Inver
ti
ng B
u
ff
er w
i
th 3-
ST
A
T
E O
u
t
put
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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