Exar
Corporation 48720 Kato Road, Fremont CA, 94538
З
(510) 668-7000
З
FAX (510) 668-7017
З
www.exar.com
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XRT82D20
SINGLE CHANNEL E1 LINE INTERFACE UNIT
APRIL 2001
REV. 1.0.7
GENERAL DESCRIPTION
The XRT82D20 is a fully integrated, single channel,
Line Interface Unit (Transceiver) for 75
or 120
E1
(2.048 Mbps) applications. The LIU consists of a
receiver with adaptive data slicer for accurate data
and clock recovery and a transmitter which accepts
either single or dual-rail digital inputs for signal
transmission to the line using a low- impedance
differential line driver. The LIU also includes a crystal-
less jitter attenuator for clock and data smoothing
which, depending on system requirements, can be
selected in either the transmit or receive path.
Coupling the XRT82D20 to the line requires trans-
formers on both the Receiver and Transmitter sides,
and supports both 120
balanced and 75
unbal-
anced interfaces. The receiver can be capacitive
coupled to for cost reduction
FEATURES
З Complete E1 (CEPT) line interface unit
З Generates transmit output pulses that are compli-
ant with the ITU-T G.703 Pulse Template for
2.048Mbps (E1) rates
З On-Chip Pulse Shaping for both 75
and 120
Line Drivers
З Clock Recovery and Selectable Crystal-less Jitter
attenuator
З Compliant with ETS300166 Return Loss
З Compliant with the ITU-T G.823 Jitter Tolerance
Requirements
З Remote, Local and Digital Loop backs
З Declares and Clears LOS per ITU-T G.775
З Logic Inputs accept either 3.3V or 5.0V levels
З - 40
0
C to 85
0
C Temperature Range
З Low Power Dissipation; 145mW with 120
or
160mW with 75
typical
З +3.3V or +5V Supply Operation
З Pin Compatible with the XRT7288
APPLICATIONS
З PDH Multiplexers
З SDH Multiplexers
З Digital Cross-Connect Systems
З DECT (Digital European Cordless Telephone) Base
Stations
З CSU/DSU Equipment
З Test Equipment
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT82D20
HDB3
Encoder
Peak
Detector
Local
Loopback
LOS
Detect
Data
Slicer
Data &
Timing
Recovery
Remote
Loopback
HDB3
Decoder
Digital
Loopback
Tx Pulse
Shaper
MUX
MUX
Line
Driver
TClk
TPOS
TNEG
RClk
RPOS
RNEG
TTIP
TRing
RLOS
RTIP
RRing
MClk
Timing
Generator
Jitter Attenuator
XRT82D20
SINGLE CHANNEL E1 LINE INTERFACE UNIT
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REV. 1.0.7
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES ................................................................................................................................................ 1
APPLICATIONS ......................................................................................................................................... 1
Figure 1. Block Diagram of the XRT82D20 .................................................................................................. 1
Figure 2. Pinout of the XRT82D20 ................................................................................................................ 2
O
RDERING
I
NFORMATION
.............................................................................................................................. 2
PIN DESCRIPTIONS .......................................................................................................... 3
Figure 3. Interface Timing Diagram in Both Single-Rail and Dual-Rail Mode, with DIGI (Pin 17) = "0" . 5
Figure 4. Interface Timing Diagram in Dual-Rail Mode only, with DIGI (Pin 17) = "1" ............................. 6
ELECTRICAL CHARACTERISTICS .................................................................................. 7
T
ABLE
1: R
ECEIVER
C
HARACTERISTICS
.............................................................................................................. 7
T
ABLE
2: T
RANSMITTER
C
HARACTERISTICS
........................................................................................................ 7
T
ABLE
3: 3.3V P
OWER
C
ONSUMPTION
INCLUDING
L
INE
P
OWER
D
ISSIPATION
, T
RANSMISSION
AND
R
ECEIVE
P
ATHS
ALL
A
CTIVE
........................................................................................................................................................ 7
T
ABLE
4: 5V P
OWER
C
ONSUMPTION
INCLUDING
L
INE
P
OWER
D
ISSIPATION
, T
RANSMISSION
AND
R
ECEIVE
P
ATHS
ALL
A
CTIVE
............................................................................................................................................................... 8
T
ABLE
5: AC E
LECTRICAL
C
HARACTERISTICS
................................................................................................... 8
T
ABLE
6: DC E
LECTRICAL
C
HARACTERISTICS
.................................................................................................... 9
A
BSOLUTE
MAXIMUM
R
ATINGS
.......................................................................................................... 9
Figure 5. Receiver Maximum Jitter Tolerance, Test Conditions: Test Pattern 2
15
-1, (-6dB) Cable Loss ..
10
Figure 6. Receiver Jitter Transfer Function (Jitter Attenuator Disabled), Test Conditions: Test Pattern
2
15
-1, Input Jitter 0.5UIp-p ............................................................................................................................ 11
Figure 7. Receiver Jitter Transfer Function (Jitter Attenuator enabled) Test Conditions: Test Pattern 2
15
-
1, Input Jitter 75% of Maximum Jitter Tolerance ........................................................................................ 11
SYSTEM DESCRIPTION .................................................................................................. 12
1.0 THE Receive Section ........................................................................................................................ 12
1.1 JITTER ATTENUATOR .................................................................................................................................. 12
1.2 THE TRANSMIT SECTION ............................................................................................................................ 12
Figure 8. Illustration on how the XRT82D20 Samples the data on the TPOS and TNEG input pins .... 12
1.3 T
HE
P
ULSE
S
HAPING
C
IRCUIT
........................................................................................................................... 12
Figure 9. Illustration of the ITU-T G.703 Pulse Template for E1 Application .......................................... 13
1.4 I
NTERFACING
THE
T
RANSMIT
S
ECTION
OF
THE
XRT82D20
TO
THE
L
INE
............................................................. 14
Figure 10. Illustration of how to interface the XRT82D20 to the Line for 75
Applications and 3.3V op-
eration only .................................................................................................................................................... 14
Figure 11. Illustration of how to interface the XRT82D20 to the Line for 120
Applications and 3.3V op-
eration only .................................................................................................................................................... 15
1.5 I
NTERFACING
THE
R
ECEIVE
S
ECTION
TO
THE
L
INE
............................................................................................. 15
Figure 12. Recommended Schematic for Transformer-Coupling the XRT82D20 to the Line for 75
Ap-
plications and 5 V operation only ................................................................................................................ 16
Figure 13. Recommended Schematic for Transformer-Coupling the XRT82D20 to the Line for 120
Ap-
plications and 5 V operation only ................................................................................................................ 17
1.6 C
APACITIVELY
-
COUPLING
THE
R
ECEIVE
S
ECTION
(
S
)
OF
THE
XRT82D20
TO
THE
LINE
......................................... 18
Figure 14. Capacitively-coupling the Receive Section for 75
Application and 3.3V supply ............. 18
Figure 15. Capacitively-coupling the Receive Section for 120
Application and 3.3V supply ........... 19
Figure 16. Capacitively-coupling the Receive Section for 75
Application and 5V supply ................ 20
Figure 17. Capacitively-coupling the Receive Section for 120
Application and 5V supply .............. 21
2.0 Diagnostic Features ......................................................................................................................... 22
2.1 T
HE
L
OCAL
L
OOP
-B
ACK
M
ODE
......................................................................................................................... 22
Figure 18. Illustration of the Analog Local Loop-Back within the XRT82D20 ........................................ 22
2.2 T
HE
R
EMOTE
L
OOP
B
ACK
M
ODE
....................................................................................................................... 23
Figure 19. Illustration of the Remote Loop-Back path, within the XRT82D20 ........................................ 23
XRT82D20
SINGLE CHANNEL E1 LINE INTERFACE UNIT
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REV. 1.0.7
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PIN DESCRIPTIONS
P
IN
#
S
YMBOL
T
YPE
D
ESCRIPTION
1
RLOS
O
Receiver Loss of Signal: This pin toggles Low to indicate the loss of
signal at the receive inputs.
2
ClkLOS
O
Receiver Loss of Clock: With MuteRx=1, this pin will toggle low to indi-
cate a loss of clock has occurred when the receive signal is lost
(RLOS=0). When RLOS=0, no transitions occur on RClk, RPOS/RData
and RNEG outputs.
3
TNEG/CODE
I
Transmitter Negative Data Input/Coding Select: With Jitter Attenuator
enabled (pin 18=1), input activity on this pin determines whether the
device is configured to operate in single-rail or dual-rail mode. With n-rail
transmit data applied to this pin, the device is automatically configured to
operate in dual-rail mode for both transmit input and receive output.
If this pin is tied high for more than 16 clock cycles, the device is config-
ured to operate in single-rail mode with HDB3 encoding and decoding
functions enabled.
If this pin is tied low for more than 16 clock cycles, the device is config-
ured to operate in single-rail mode with AMI encoding and decoding
functions enabled. (internal pull-down).
4
RNEG/LCV
O
Receive Negative Data/Line Code Violation Output:
If the device is configured in Dual-rail mode with n-rail data applied to pin
3, then the receive negative data will be output through this pin.
If the device is configured in Single-rail mode and operate with HDB3
coding enabled, HDB3 code violation will be detected and cause this pin
to go high.
If the device is configured in Single-rail mode and with AMI coding
selected, every bipolar violation will be reported at this pin.
5
RClk
O
Receive Clock:
Output receive clock signal to the terminal equipment.
6
RPOS/RData
O
Receive Positive/ Data Output:
In Dual-rail mode, this signal is the p-rail receive output data. In Single-
rail mode, this signal is the receive output data.
7
TClk
I
Transmitter Clock Input:
Input clock signal (2.048 MHz Б 50ppm)
8
TPOS/TData
I
Transmit Positive / Data Input:
In Dual-rail mode, this signal is the p-rail transmit input data. In Single-rail
mode, this signal is the transmit input data.
9
LLoop
I
Local Loop back enable (active low):
Tie this pin low to enable analog Local Loop-back.In local loop-back
mode, transmit output data is looped back to the input of the
receiver.Input signal at RTIP and RRing are ignored. Local Loop-back
has priority over Remote and Digital Loop-back mode. See Section 2.2
for more details. (internal pull-down).
10
RLoop
I
Remote Loop Back Enable (active low):
Connect this pin to ground to enable Remote Loop-back. In Remote
Loop-back mode, transmit data at TPOS/TData and TNEG are ignored.
See Section 2.2 for more details. (internal pull-down).
11
DLoop
I
Digital Loop Back enable (active low):
Connect this pin to ground to enable Digital Local Loop-back.In Digital
loop-back mode, transmit input data after the encoder is looped back to
the jitter attenuator (if selected) and to the receive decoder. Input data at
RTIP and RRing are ignored in this mode. (internal pull-up). In this
mode, the XRT82D20 can operate only as a jitter attenuator.
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