EM65160

160 COM/SEG Dot Matrix LCD Driver

* This specification are subject to be changed without notice. 6/27/2002 (V1.1)

GENERAL DESCRIPTION

The EM65160 is a 160-channel output common and segment driver LSI for driving large scale STN dot matrix LCD (liquid

crystal display) panel using as PDA, computers and workstation. Since this product can be used as segment or common

driver, a LCD panel can be configured only with this product. Through the use of SST (super slim TCP) technology, it is deal

for substantially decreasing the size of LCD module frame.

In common driver mode, it can be selected in single mode and dual mode by a mode pin (MD), data input/output pins are

bi-directional, four data shift direction are pin selectable.

In segment driver mode, it can be selected 4-bit parallel input mode or 8-bit parallel input mode by a mode pin (MD).

FEATURES

Both common mode and segment mode

Display duty application: up to 1/480 duty

Supply voltage for the logic system: +2.5 to +5.5V

Supply voltage for LCD driver: +15 to +42V

Number of LCD driver outputs: 160

Low output impedance

Low power consumption

CMOS silicon process (P-type Silicon substrate)

186 pin TCP (tape carrier package) package

Built-in display-off function: when /DSPOF is "L", all LCD drive output remain at the V

level.

Common Mode

Shift clock frequency: 4.0MHz (Max.)

Built-in 160 bits bi-directional shift register (divisible into 80bits*2)

Available in a single mode or in a dual mode

Data input/output pins are bi-directional, four data shift direction are pin selectable.

Shift register circuit reset function when /DSPOF active

Segment mode

Shift clock frequency: 14MHz(Max.) (V

=+5V

10%)

8MHz(Max.) (V

=+2.5V to +4.5V)

Adopts a data bus system

4-bits/8-bits parallel input mode are selected by mode pin (MD)

Automatic transfer function of an enable signal

Automatic counting function which, in the chip select, causes the internal clock to be stopped by automatically counting

160 of input data

Line latch circuit reset function when /DSPOF active

EM65160

160 COM/SEG Dot Matrix LCD Driver

* This specification are subject to be changed without notice. 6/27/2002 (V1.1)

PIN ARRANGEMENT

12L

43L

XCK

43R

12R

160

159

C hip Surface

161 -------------------------------------------------------------------------------------------186

160---------------------------------------------------------------------------------------------------------------------1

Figure-1 Pin Arrangement

BLOCK DIAGRAM

Liquid crystal display driver circuit

160 bits line latch

/shift register

data latch control

Active

Control

Level

Shifter

8bits*2

data

latch

data conversion & control

(4 to 8 or 8 to 8)

Clock

Control

160

Y1,Y2.............................Y159,Y160

, V

12R

, V

43R

, V

12L

, V

43L

, V

/DSPOF

EIO

XCK

DIR

S/C

- DI

160 bits level shifter

160

Figure-2 Block Diagram

EM65160

160 COM/SEG Dot Matrix LCD Driver

* This specification are subject to be changed without notice. 6/27/2002 (V1.1)

PIN DESCRIPTION

Table-1 Pin Arrangement

Pin NO.

Symbol

I/O

Description

1 to 160

-Y

160

LCD driver output

161,186 V

, V

Power supply for LCD driver

162,185 V

12L

, V

12R

Power supply for LCD driver

163,184 V

43L

, V

43R

Power supply for LCD driver

165

DIR

Display data shift direction selection

166 V

Power supply for logic system

167

S/C

Segment/common mode selection

168
180

EIO

I/O

Input /output for chip select or data of shift register

169 to 176

Display data input for segment mode
Dual mode data input for common mode

177

XCK

Display data shift clock input for segment mode

178

/DSPOF

Control input for deselect output level

179

Latch pulse input/shift clock input for shift register

181

AC-converting signal input for LCD driver waveform

182

Mode selection input

164,183 V

Ground (0 V)

Segment Mode

Table-2 Pin Functions Of Segment Mode

Symbol

I/O

Connected to

Functions

Power Supply Power supply for internal logic connects to +2.5 to +5.5V

GND

Connect to Ground

12R

12L

43R

43L

I Power

Supply

Power supply for LCD driver level

Normallythe bias voltage used is set by resistor divider

Ensure that the voltage are set such that

To further reduce the difference between the output waveforms of LCD driver output pin
Y

and Y

160

externally connect V

and V

(i=0,12,43)

I Controller

Input for display data

In 4-bit parallel input modeinput data into DI

, connect DI

to V

or V

In 8-bit parallel input modeinput data into DI

XCK I

Controller

Clock signal for taking display data
Data is read on the falling of the clock pulse

LP I

Controller

Latch signal for display data

Data is latched on the falling edge of the clock pulse

Selection of segment mode/common mode

S/C

Mode selection

H Segment

mode

L Common

mode

S/C I

Directional selection for reading display data

DIR

Data read direction

L Y

160

to Y

H Y

to Y

160

DIR I

EM65160

160 COM/SEG Dot Matrix LCD Driver

* This specification are subject to be changed without notice. 6/27/2002 (V1.1)

Segment mode (continuous)

Symbol

I/O

Connected to

Functions

/DSPOF I Controller

Control signal for output deselect level

The input signal is level-shifted from logic voltage level to LCD driver voltage level and
controls LCD drive circuit

When the signal is lowthe output (Y

160

) of LCD drive be set to level V

the

contents of line latch are resetbut read the display data in the data latch regardless of
condition of /DSPOF

When this signal is high, the operation returns to the normal status.

FR I

Controller

AC signal for LCD drive

Input a frame inversion signal

The LCD driver output voltage level can be set by line latch output signal and FR signal

Mode selection

Mode selection

8-bit parallel input

4-bit parallel input

MD I

Input/output for chip selection

In output stateafter 160-bit of data have been readset to "L" then set to "H"

In input state the chip is selected when EI is set to "L"then 160-bit of data have been
readthe chip is deselected

DIR

EIO

H Input Output

L Output Input

EIO

-Y

160

LCD

Panel

LCD driver output.
One of four levels is output according to the combination of the FR signal and display data

Common Mode

Table-3 Pin Functions Of Common Mode

Symbol

I/O

Connected to

Functions

Power supply

Power supply for internal logic connects to +2.5 to +5.5V

GND

Connect to Ground

, V

12R

, V

12L

34R

, V

34L

I Power

supply

Power supply for LCD driver level

Normallythe bias voltage used is set by resistor divider

Ensure that the voltage are set such that

To further reduce the difference between the output waveforms of LCD driver output pin
Y

and Y

160

,externally connect V

and V

(i=0,12,34)

EIO

Data input/output shift for bi-directional shift register

When EIO

(EIO

) is inputit will be pull-down

When EIO

(EIO

) is outputit will not be pull-down

DIR

EIO

H Input Output

L Output Input

LP I

Controller

Shift clock for bi-directional shift register

Data is shifted on the falling edge of the clock

EM65160

160 COM/SEG Dot Matrix LCD Driver

* This specification are subject to be changed without notice. 6/27/2002 (V1.1)

Common Mode (Continuous)

Symbol

I/O

Connected to

Functions

DIR I

Controller

Directional selection of bi-directional shift register

DIR

Data read direction

L Y

160

to Y

H Y

to Y

160

/DSPOF I Controller

Control signal for output deselect level

The input signal is level-shifted from logic voltage level to LCD driver voltage leveland
controls LCD drive circuit

When the signal is lowthe output (Y

160

) of LCD drive be set to level V

the

contents of shift register are reset not read

When this signal return to high, the operation returns to the normal status.

FR I

Controller

AC signal for LCD drive

Input a frame inversion signal

The LCD driver output voltage level can be set by line latch output signal and FR signal

MD I

Mode selection

Mode selection

H Dual

mode

L Single

mode

S/C I

Selection of segment mode/common mode

S/C

Mode selection

H Segment

mode

L Common

mode

Controller

Dual mode data input

In dual modedata can input from 81

bit

-DI

or V

Not used, avoiding floating.

XCK I

or open

Not used

-Y

160

LCD

Panel

LCD driver output.

One of four voltage levels is output according to FR signal and the data of shift register

FUNCTIONAL DESCRIPTIONS

Active Control

In case of segment mode, controls the selection or de-selection of the chip. Following a LP signal, and after the chip select

signal is input, a select signal is generated internally until 160bits of data have been read in. Once data input has been

completed, a select signal for cascade connection is output, and the chip is deselected. In case of common mode, controls the

input/output data of bi-directional pins.

SP Conversion & Data Control

In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keep input

data which are 1 clock of XCK at 8-bits parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at

a time.

Data Latch Control

In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled

by the control logic, for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit.

Part Number EM65160