PIN NAMES
A0-A12
Row Address:
A0-A12
Column Address: A0-A9, A11, A12
BA0,BA1
Bank Select Address
A10/AP
Auto Precharge
DQ0-DQ7
Data In/Data Out
CAS
Column Address Strobe
CS0,CS1
Chip Selects
RAS
Row Address Strobe
WE
Data Write Enable
CK, CK
Differential Clock Inputs
CKE0, CKE1
Clock Enables
DQS
Data Strobe
DM
Data Masks
QFC
DQ FET Switch Control
V
DD
Power Supply (+2.5V)
V
SS
Ground
V
DDQ
DQ Power Supply (+2.5V)
V
SSQ
DQ Ground
V
REF
Reference Voltage for inputs
N.C.
No Connect
NU*
Not used, Electrical Connect is Present
DESCRIPTION:
The Memory StackTM series is a family of interchangeable memory modules. The 1 Gigabit Double Data Rate Synchronous
DRAM module is a member of this family which utilizes the space saving LP-StackTM TSOP stacking technology. The devices
are constructed with two 64 Meg x 8 DDR SDRAMs.
This 512 Megabit based LP-StackTM module, DPDD128MX8XSBY5, has been designed to fit in the same footprint as the 64
Meg x 8 DDR SDRAM TSOP monolithic. This allows system upgrade without electrical or mechanical redesign, providing an
immediate and low cost memory solution.
FEATURES:
· Configuration:
128 Meg x 8 (2 Banks of 16 Meg x 8 Bits x 4 Banks)
· JEDEC Approved Footprint and Pinout
· IPC-A-610 Manufacturing Standards
· Package: 66-Pin Leadless TSOP Stack
The Following Features are not affected by LP-StackTM and
are provided as reference only. Refer to memory OEM
device specification for details:
· Clock Frequency is determined by OEM memory
device used.
· 2.5 Volt DQ Supply
· JEDEC Standard SSTL_2 Interface for all
Inputs/Outputs
· Four Bank Operation
· Programmable Burst Length and Read Latency
· Refresh: 8192 Cycles/64ms
· Refresh Types: Auto and Self
1
(TOP VIEW)
60
N.C.
VDD
1
2
54
N.C.
VDDQ
3
53
N.C.
4
52
VSSQ
DQ1
5
51
DQS
VSSQ
6
50
N.C.
N.C.
7
49
VREF
8
48
VSS
VDDQ
9
47
N.C.
10
46
CK
DQ3
11
45
CK
VSSQ
12
44
CKE0
N.C.
13
43
CKE1
N.C.
14
42
A12
VDDQ
15
41
A11
N.C.
16
40
A9
A13
17
39
A8
VDD
18
38
A7
*NU/QFC
19
37
A6
N.C.
20
36
A5
WE
21
35
A4
CAS
22
34
VSS
RAS
23
59
DQ5
CS0
24
58
VSSQ
CS1
25
57
N.C.
BA0
26
56
DQ4
BA1
27
55
VDDQ
DQ2
DQ0
DM
N.C.
33
VDD
32
A3
31
A2
30
A1
29
A0
28
A10/AP
VDDQ
61
DQ6
62
N.C.
63
VSSQ
64
DQ7
65
VSS
66
This document contains information on a product presently under development at DPAC Technologies Corp.
DPAC reserves the right to change products or specifications herein without prior notice.
30A254-00
REV. A 6/02
1 Gigabit CMOS DDR SDRAM
DPDD128MX8XSBY5
DM
CAS
WE
DQ0-DQ7
CS0
(16 Meg x 8 Bits x 4 Banks)
RAS
CK
DQS
CS1
CK
A0-A12
VREF
CKE1
CKE0
(16 Meg x 8 Bits x 4 Banks)
BA0-BA1
512 Mb DDR SDRAM
QFC
1
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
ADVAN C E D C O M P O N E NTS PAC K AG I N G
P
R
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L
I
M
I
NAR
Y
* This pin is a No Connect for Some Manufacturers.
20
DP
XX
-
CAS
DOUBLE DATA RATE SYNCHRONOUS DRAM
PREFIX
CAS LATENCY 2.0
DD
128M
X
8
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
X
512 MEGABIT BASED
STACKABLE TSOP
MANUFACTURER CODE *
XX
-
MFR ID
SUPPLIER
DP
SUPPLIER CODE *
I/O TYPE
S
SSTL INPUTS/OUTPUTS
WIDTH
DEVICE
B
x8 MEMORY BASED
CAS LATENCY 2.5
25
10
10ns (100MHz)
8ns (125MHz)
7.5ns (133MHz)
75
08
CYCLE
XX
TIME
LATENCY
7ns (143MHz)
70
6ns (166MHz)
60
ORDERING INFORMATION
2
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
©2002 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, CS StackTM are trademarks of DPAC Technologies Corp.
DPDD128MX8XSBY5
1 Gigabit CMOS DDR SDRAM
1
.015 [.18]
.0256 [.65]
.102 MAX
PIN 1
INDEX
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
.502±.008
.885±.010
.427 [10.85]
.417 [10.59]
.527 [13.39]
.517 [13.13]
.0256 [.65] BSC
.016 [.41]
Standard TSOP pad layout is acceptable, however, when possible, the
following pad layout is recommended for optimal manufacture and
inspection. See Application Note 53A001-00 for further information.
[12.75±.20]
[22.48±.25]
[2.59 MAX]
.819 [20.80] BSC
.020 [.51]
TYP
TYP
MECHANICAL DRAWING
* Contact your sales representative for supplier and manufacturer codes.
NOTE:
1. AC Parameters of base memory are unchanged from device manufacturers' specifications.
2. DC Parameters may be affected by stacking. Please refer to Application Note 53A004-00 for further information.
30A254-01
REV. A 6/02
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