MediaClockTM
PDP Clock Generator
CY24207
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
,
CA 95134
·
408-943-2600
Document #: 38-07553 Rev. *A
Revised July 31, 2003
Features
· Integrated phase-locked loop (PLL)
· Low-jitter, high-accuracy outputs
· VCXO with Analog Adjust
· 3.3V operation
Benefits
· Internal PLL with up to 400-MHz internal operation
· Meets critical timing requirements in complex system
designs
· Large ±200-ppm range, better linearity
· Enables application compatibility
Part Number
Outputs
Input Frequency
Output Frequency Range
CY24207-1
4
27-MHz Crystal Input
Two copies of 27-MHz reference clock output, two copies of
54/53.946053/67.425/67.357642 MHz (frequency selectable)
CY24207-2
4
27-MHz Crystal Input
Two copies of 27-MHz reference clock output, two copies of
54/53.946053/67.425/68.400599 MHz (frequency selectable)
Frequency Select Options
OE
FS1
FS0
CLK1/CLK2 (-1)
[1]
CLK1/CLK2 (-2)
[1]
REFCLK 1/2
Unit
0
0
0
off
off
27
MHz
0
0
1
off
off
27
MHz
0
1
0
off
off
27
MHz
0
1
1
off
off
27
MHz
1
0
0
54
54
27
MHz
1
0
1
53.946053 (1 ppm)
53.946053 (1 ppm)
27
MHz
1
1
0
67.425
67.425
27
MHz
1
1
1
67.357642 (3.8 ppm)
68.400599(8.8 ppm)
27
MHz
Note:
1.
"off" = output is driven high.
Block Diagram
XIN
XOUT
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
CLK1
Q
P
VCO
VDDL
AVSS
AVDD
VSS
FS0
FS1
CLK2
REFCLK1
VSSL
VDD
16-pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
FS0
XIN
XOUT
VDD
VCXO
AVSS
REFCLK1
OE
FS1
AVDD
VDDL
Pin Configuration
CLK2
OE
VCXO
CLK1
24
20
7-
1
,
-
2
REFCLK2
REFCLK2
CY24207
Document #: 38-07553 Rev. *A
Page 2 of 6
Pin Description
Pin No.
Name
Description
1
XIN
Reference crystal input
2
V
DD
Voltage supply
3
AV
DD
Analog voltage supply
4
VCXO
Input analog control for VCXO
5
AV
SS
Analog ground
6
V
SSL
CLK ground
7
REFCLK2
Reference clock output
8
REFCLK1
Reference clock output
9
CLK1 (1)
54/53.946053/67.425/67.357642 MHz clock output (frequency selectable)
9
CLK1 (2)
54/53.946053/67.425/68.400599 MHz clock output (frequency selectable)
10
FS0
Frequency Select 0, weak internal pull-up
11
V
DDL
CLK voltage supply
12
CLK2 (1)
54/53.946053/67.425/67.357642 MHz clock output (frequency selectable)
12
CLK2 (2)
54/53.946053/67.425/68.400599 MHz clock output (frequency selectable)
13
V
SS
Ground
14
FS1
Frequency Select 1, weak internal pull-up
15
OE
Output Enable, weak internal pull-up
16
XOUT
Reference crystal output
CY24207
Document #: 38-07553 Rev. *A
Page 3 of 6
Absolute Maximum Conditions
Supply Voltage (V
DD
, AV
DDL
, V
DDL
)..................0.5 to +7.0V
DC Input Voltage ........................................ 0.5V to V
DD
+0.5
Storage Temperature (Non-condensing)..... 55
°
C to +125
°
C
Junction Temperature ................................ 40
°
C to +125
°
C
Data Retention @ Tj = 125
°
C................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883.................... 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Pullable Crystal Specifications
Parameter
Description
Conditions
Min.
Typ.
Max. Units
F
NOM
Nominal crystal frequency
Parallel resonance, fundamental mode, AT
cut
27.0
MHz
C
LNOM
Nominal load capacitance
14
pF
R
1
Equivalent series resistance (ESR)
Fundamental mode
25
R
3
/R
1
Ratio of third overtone mode ESR to
fundamental mode ESR
Ratio used because typical R
1
values are
much less than the maximum spec
3
DL
Crystal drive level
No external series resistor assumed
0.5
2
mW
F
3SEPHI
Third overtone separation from 3*F
NOM
High side
300
ppm
F
3SEPLO
Third overtone separation from 3*F
NOM
Low side
150
ppm
C
0
Crystal shunt capacitance
7
pF
C
0
/C
1
Ratio of shunt to motional capacitance
180
250
C
1
Crystal motional capacitance
14.4
18
21.6
fF
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
/AV
DDL
/V
DDL
Operating Voltage
3.135
3.3
3.465
V
T
A
Ambient Temperature
0
70
°C
C
LOAD
Max. Load Capacitance
15
pF
t
PU
Power-up time for all V
DD
s to reach minimum specified
voltage (power ramps must be monotonic)
0.05
500
ms
DC Electrical Specifications
Parameter
2
Name
Description
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
/V
DDL
= 3.3V
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
/V
DDL
= 3.3V
12
24
mA
V
IH
Input High Voltage
CMOS levels, 70% of V
DD
0.7
V
DD
V
IL
Input Low Voltage
CMOS levels, 30% of V
DD
0.3
V
DD
I
VDD
Supply Current
AV
DD
/V
DD
Current
25
mA
I
VDDL
Supply Current
V
DDL
Current (V
DDL
= 3.47V)
20
mA
C
IN
Input Capacitance
excluding XIN and XOUT
7
pF
f
XO
V
CXO
pullability range
±200
ppm
V
VCXO
V
CXO
input range
0
V
DD
V
R
UP
Pull-up resistor on inputs V
DD
= 3.14 to 3.47V, measured at V
IN
= 0V
100
150
k
CY24207
Document #: 38-07553 Rev. *A
Page 4 of 6
Test and Measurement Set-up
Voltage and Timing Definitions
Note:
2.
Not 100% tested.
AC Electrical Specifications
Parameter
[2]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1; t1/t2, 50% of V
DD
45
50
55
%
ER
Rising Edge Rate
Output Clock Edge Rate, Measured from 20% to
80% of V
DD
, C
LOAD
= 15 pF. See Figure 2.
0.8
1.4
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80% to
20% of V
DD
, C
LOAD
= 15 pF. See Figure 2.
0.8
1.4
V/ns
t
9
Clock Jitter
CLK1, CLK2 Peak-Peak period jitter
120
ps
t
10
PLL Lock Time
3
ms
0.1
µ
F
V
DDs
Outputs
C
LOAD
GND
DUT
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Figure 1. Duty Cycle Definition
Clock
Output
t
3
t
4
V
DD
80% of V
DD
20% of V
DD
0V
Figure 2. ER = (0.6 x V
DD
) /t3, EF = (0.6 x V
DD
) /t4
CY24207
Document #: 38-07553 Rev. *A
Page 5 of 6
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the
trademarks of their respective holders
Ordering Information
Ordering Code
Package Type
Operating Range
Operating Voltage
CY24207ZC-1
16-pin TSSOP
Commercial
3.3V
CY24207ZC-1T
16-pin TSSOP
Commercial
3.3V
CY24207ZC-2
16-pin TSSOP
Commercial
3.3V
CY24207ZC-2T
16-pin TSSOP
Commercial
3.3V
16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091-**
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