PRELIMINARY
MPEG Clock Generator with VCXO
CY241V08-01,-04,-05,-06
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
,
CA 95134
·
408-943-2600
Document #: 38-07520 Rev. *A
Revised July 28, 2003
Features
· Integrated phase-locked loop (PLL)
· Low-jitter, high-accuracy outputs
· VCXO with analog adjust
· 3.3V operation
Benefits
· Highest-performance PLL tailored for multimedia applica-
tions
· Meets critical timing requirements in complex system
designs
· Application compatibility for a wide variety of designs
Advance Features
· Lower drive strength settings (CY241V08-04, -06)
Benefits
· Electromagnetic interference (EMI) reduction for standards
compliance
Frequency Table
Part
Number
Outputs
Input Frequency Range
Output
Frequencies
VCXO Control
Curve
Other Features
CY241V08-01
1
13.5-MHz pullable crystal input
per Cypress specification
One copy of 27 MHz linear
Pinout compatible with MK3727
CY241V08-04
1
13.5-MHz pullable crystal input
per Cypress specification
One copy of 27 MHz linear
Same as CY241V08-01 except
lower drive strength settings
CY241V08-05
1
13.5-MHz pullable crystal input
per Cypress specification
One copy of 27 MHz nonlinear
Mimics MK3727 nonlinear
VCXO Control Curve
CY241V08-06
1
13.5-MHz pullable crystal input
per Cypress specification
One copy of 27 MHz nonlinear
Same as CY241V08-05 except
lower drive strength settings
13.5 XIN
XOUT
OSC
VCXO
VDD
VSS
Block Diagram
8-pin SOIC
CY241V08-01,-04,-05,-06
1
2
3
4
XOUT
XIN
VCXO
27 MHz
VSS
NC or VSS
NC or VDD
5
6
7
8
VDD
Pin Configuration
OUTPUT
DIVIDER
PLL
27 MHz
PRELIMINARY
CY241V08-01,-04,-05,-06
Document #: 38-07520 Rev. *A
Page 2 of 6
Absolute Maximum Conditions
Supply Voltage (V
DD
) ........................................0.5 to +7.0V
DC Input Voltage ...................................... 0.5V to V
DD
+ 0.5
Storage Temperature (Non-condensing)..... 55
°
C to +125
°
C
Junction Temperature ................................ 40
°
C to +125
°
C
Data Retention @ Tj = 125
°
C................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883................. > 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Pin Descriptions for CY241V08 01, 04, 05, 06
Name
Pin Number
Description
XIN
1
Reference crystal input
VDD
2
Voltage supply
VCXO
3
Input analog control for VCXO
VSS
4
Ground
27 MHz
5
27-MHz clock output
NC/VDD
6
No connect or voltage supply
NC/VSS
7
No connect or ground
XOUT
8
Reference crystal output
Pullable Crystal Specifications
[1]
Parameter
Description
Comments
Min.
Typ.
Max.
Unit
F
NOM
Nominal crystal frequency
Parallel resonance, fundamental mode,
AT cut
13.5
MHz
C
LNOM
Nominal load capacitance
14
pF
R
1
Equivalent series resistance (ESR) Fundamental mode
25
R
3
/R
1
Ratio of third overtone mode ESR
to fundamental mode ESR
Ratio used because typical R
1
values
are much less than the maximum spec
3
DL
Crystal drive level
No external series resistor assumed
150
µ
W
F
3SEPHI
Third overtone separation from
3*F
NOM
High side
400
ppm
F
3SEPLO
Third overtone separation from
3*F
NOM
Low side
-200
ppm
C
0
Crystal shunt capacitance
7
pF
C
0
/C
1
Ratio of shunt to motional capaci-
tance
180
250
C
1
Crystal motional capacitance
14.4
18
21.6
fF
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
3.135
3.3
3.465
V
T
A
Ambient Temperature
0
70
°C
C
LOAD
Max. Load Capacitance
15
pF
t
PU
Power-up time for all VDD pins to
reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
Note:
1.
Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI
HA13500XFSA14XC.
PRELIMINARY
CY241V08-01,-04,-05,-06
Document #: 38-07520 Rev. *A
Page 3 of 6
DC Electrical Specifications
Parameter
Name
Description
Min.
Typ.
Max.
Unit
I
OH
Output HIGH Current 001,
005
V
OH
= V
DD
0.5V, V
DD
= 3.3V
12
24
mA
I
OL
Output LOW Current 001,
005
V
OL
= 0.5V, V
DD
= 3.3V
12
24
mA
I
OH
Output HIGH Current 004,
006
V
OH
= V
DD
0.5V, V
DD
= 3.3V
6
18
mA
I
OL
Output LOW Current 004,
006
V
OL
= 0.5V, V
DD
= 3.3V
6
18
mA
C
IN
Input Capacitance
Except XIN, XOUT pins
7
pF
V
VCXO
VCXO Input Range
0
V
DD
V
f
XO
VCXO Pullability Range
±150
ppm
I
VDD
Supply Current
30
35
mA
AC Electrical Specifications (V
DD
= 3.3V)
[2]
Parameter
[2]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of V
DD
45
50
55
%
ER
Rising Edge Rate 001, 005
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, CLOAD = 15 pF. See Figure 2.
0.8
1.4
V/ns
EF
Falling Edge Rate 001, 005
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF. See Figure 2.
0.8
1.4
V/ns
ER
Rising Edge Rate 004, 006
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, CLOAD = 15 pF. See Figure 2.
0.7
1.1
V/ns
EF
Falling Edge Rate 004, 006
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF. See Figure 2.
0.7
1.1
V/ns
t
9
Clock Jitter 001, 005
Peak-to-peak period jitter
140
ps
t
9
Clock Jitter 004, 006
Peak-to-peak period jitter
150
ps
t
10
PLL Lock Time
3
ms
Test and Measurement Setup
Note:
2.
Not 100% tested.
0.1
µ
F
VDD
Outputs
C
LOAD
GND
DUT
PRELIMINARY
CY241V08-01,-04,-05,-06
Document #: 38-07520 Rev. *A
Page 4 of 6
Voltage and Timing Definitions
Ordering Information
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Figure 1. Duty Cycle Definition
Clock
Output
t
3
t
4
V
DD
80% of V
DD
20% of V
DD
0V
Figure 2. ER = (0.6 x V
DD
) /t3, EF = (0.6 x V
DD
) /t4
Ordering Code
Package
Name
Package Type
Operating Range
Operating
Voltage
Features
CY241V08SC-01
S8
8-pin SOIC
Commercial
3.3V
Linear VCXO control curve
CY241V08SC-01T
S8
8-pin SOIC Tape and Reel Commercial
3.3V
Linear VCXO control curve
CY241V08SC-04
S8
8-pin SOIC
Commercial
3.3V
Lower drive strength version
of CY241V08-01
CY241V08SC-04T
S8
8-pin SOIC Tape and Reel Commercial
3.3V
Lower drive strength version
of CY241V08-01
CY241V08SC-05
S8
8-pin SOIC
Commercial
3.3V
Mimics nonlinear MK3727
VCXO control curve
CY241V08SC-05T
S8
8-pin SOIC Tape and Reel Commercial
3.3V
Mimics nonlinear MK3727
VCXO control curve
CY241V08SC-06
S8
8-pin SOIC
Commercial
3.3V
Lower drive strength version
of CY241V08-05
CY241V08SC-06T
S8
8-pin SOIC Tape and Reel Commercial
3.3V
Lower drive strength version
of CY241V08-05
PRELIMINARY
CY241V08-01,-04,-05,-06
Document #: 38-07520 Rev. *A
Page 5 of 6
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
All product or company names mentioned in this document may be the trademarks of their respective holders.
SEATING PLANE
PIN 1 ID
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.189[4.800]
0.196[4.978]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
0°~8°
0.016[0.406]
0.010[0.254]
X 45°
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.004[0.102]
1
4
5
8
8-lead (150-Mil) SOIC S8
51-85066-*B
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