SERIAL

DATA

OUTPUT

REGISTER

V L1

REF

V H1

REF

V 1

OUT

V 3

V 4

OUT

V 2

OUT

PROG

RDY/

BSY

PROGRAM

CONTROL

H.V.

CHARGE

PUMP

DATA
CONTROLLER

CLK

V H2

REF

V H3

REF

V H4

REF

(ea)

V L2

REF

V L3

REF

V L4

REF

NVRAM

GND

CLK

DVD

PROG

RDY/BSY

VREF H1

VREF H2

VREF H4

VREF H3

VREF L1

REF

VREF L4

REF L3

VOUT1

OUT

GND

CLK

DVD

PROG

RDY/BSY

VREF H1

VREF H2

VREF H4

VREF H3

VREF L1

REF

VREF L4

REF L3

VOUT1

OUT

CAT525

Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications

FEATURES

Four 8-bit DPPs configured as programmable

voltage sources in DAC-like applications

Independent reference inputs

Buffered wiper outputs

Non-volatile NVRAM memory wiper storage

Output voltage range includes both supply rails

4 independently addressable buffered
output wipers

1 LSB accuracy, high resolution

Serial

P interface

Single supply operation: 2.7V-5.5V

Setting read-back without effecting outputs

APPLICATIONS

Automated product calibration

Remote control adjustment of equipment

Offset, gain and zero adjustments in
self-calibrating and adaptive control systems

Tamper-proof calibrations

DAC (with memory) substitute

DESCRIPTION

The CAT525 is a quad 8-Bit digitally programmable
potentiometer (DPPTM) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax ma-
chines and cellular telephones on automated high vol-
ume production lines and systems capable of self cali-
bration, it is also well suited for applications were equip-
ment requiring periodic adjustment is either difficult to
access or located in a hazardous environment.

The CAT525 offers four independently programmable
DPPs each having its own reference inputs and each
capable of rail to rail output swing. The wipers are
buffered by rail to rail op amps. Wiper settings, stored in
non-volatile NVRAM memory, are not lost when the
device is powered down and are automatically rein-

PIN CONFIGURATION

stated when power is returned. Each wiper can be
dithered to test new output values without effecting the
stored settings and stored settings can be read back
without disturbing the DPP's output.

Control of the CAT525 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT525's to share a common serial interface and
communications back to the host controller is via a single
serial data line thanks to the CAT525's Tri-Stated Data
Output pin. A RDY/

BSY

output working in concert with

an internal low voltage detector signals proper operation
of non-volatile NVRAM Memory Erase/Write cycle.

The CAT525 is available in the 0

C to 70

C commercial

and 40

C to 85

C industrial operating temperature

ranges and offered in 20-pin plastic DIP and Surface
mount packages.

DIP Package (P)

SOIC Package (J)

CAT525

Doc. No. 25078-00 4/01-A M-1

FUNCTIONAL DIAGRAM

CAT525

CAT525

Doc. No. 25078-00 4/01 - A M-1

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Resolution

Bits

Accuracy

INL

Integral Linearity Error

LOAD

= 10

A T

= C

0.6

LSB

LOAD

= 10

A T

= I

0.6

LSB

LOAD

= 40

A T

= C

1.2

LSB

LOAD

= 40

A T

= I

1.2

LSB

DNL

Differential Linearity Error

LOAD

= 10

A T

= C

0.25

0.5

LSB

LOAD

= 10

A T

= I

0.25

0.5

LSB

LOAD

= 40

A T

= C

0.5

LSB

LOAD

= 40

A T

= I

0.5

LSB

Logic Inputs

Input Leakage Current

= V

Input Leakage Current

= 0V

High Level Input Voltage

Low Level Input Voltage

0.8

References

REF

H Input Voltage Range

2.7

REF

L Input Voltage Range

GND

-2.7

REF

L Resistance

/ R

Input Resistance Match

0.5

Logic Outputs

High Level Output Voltage

= 40

0.3

Low Level Output Voltage

= 1 mA, V

= +5V

0.4

= 0.4 mA, V

= +3V

0.4

ABSOLUTE MAXIMUM RATINGS

Supply Voltage*

to GND ...................................... 0.5V to +7V

Inputs

CLK to GND ............................ 0.5V to V

+0.5V

CS to GND .............................. 0.5V to V

+0.5V

DI to GND ............................... 0.5V to V

+0.5V

RDY/BSY to GND ................... 0.5V to V

+0.5V

PROG to GND ........................ 0.5V to V

+0.5V

REF

H to GND ........................ 0.5V to V

+0.5V

REF

L to GND ......................... 0.5V to V

+0.5V

Outputs

to GND ............................... 0.5V to V

+0.5V

OUT

1 4 to GND ................... 0.5V to V

+0.5V

Operating Ambient Temperature

Commercial (`C' or Blank suffix) ...... 0

C to +70

Industrial (`I' suffix) ...................... 40

C to +85

Junction Temperature ..................................... +150

Storage Temperature ....................... 65

C to +150

Lead Soldering (10 sec max) .......................... +300

* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.

DC ELECTRICAL CHARACTERISTICS:

= +2.7V to +5.5V, V

REF

H = V

, V

REF

L = 0V, unless otherwise specified

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min

Max

Units

Test Method

ZAP

(1)

ESD Susceptibility

2000

Volts

MIL-STD-883, Test Method 3015

LTH

(1)(2)

Latch-Up

100

JEDEC Standard 17

NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to V

+ 1V.

CAT525

Doc. No. 25078-00 4/01 - A M-1

DC ELECTRICAL CHARACTERISTICS (Cont.):
V

= +2.7V to +5.5V, V

REF

H = V

, V

REF

L = 0V

, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Digital

CSMIN

Minimum CS Low Time

150

CSS

CS Setup Time

100

CSH

CS Hold Time

DIS

DI Setup Time

DIH

DI Hold Time

DO1

Output Delay to 1

150

DO0

Output Delay to 0

150

Output Delay to High-Z

400

Output Delay to Low-Z

400

BUSY

Erase/Write Cycle Time

PROG Setup Time

150

PROG

Minimum Pulse Width

700

CLK

Minimum CLK High Time

500

CLK

Minimum CLK Low Time

300

Clock Frequency

MHz

Analog

DAC Settling Time to 1 LSB

LOAD

= 10 pF, V

= +5V

LOAD

= 10 pF, V

= +3V

Pin Capacitance

Input Capacitance

= 0V, f = 1 MHz

(2)

OUT

Output Capacitance

OUT

= 0V, f = 1 MHz

(2)

NOTES: 1. All timing measurements are defined at the point of signal crossing V

/ 2.

2. These parameters are periodically sampled and are not 100% tested.

= 100 pF,

see note 1

AC ELECTRICAL CHARACTERISTICS:
V

= +2.7V to +5.5V, V

REF

H = V

, V

REF

L = 0V

, unless otherwise specified

Analog Output

FSO

Full-Scale Output Voltage

= V

REF

H V

REF

0.99 V

0.995 V

ZSO

Zero-Scale Output Voltage

= V

REF

H V

REF

0.005 V

0.01 V

DAC Output Load Current

OUT

DAC Output Impedance

= V

REF

H = +5V

= V

REF

H = +3V

PSSR

Power Supply Rejection

LOAD

= 1

LSB / V

Temperature

OUT

Temperature Coefficient

= +5V, I

LOAD

= 250nA

200

REF

H= +5V, V

REF

L = 0V

REF

Temperature Coefficient of

REF

H to V

REF

700

ppm /

REF

Resistance

Power Supply

DD1

Supply Current (Read)

Normal Operating

400

600

DD2

Supply Current (Write)

Programming, V

= 5V

1600

2500

= 3V

1000

1600

Operating Voltage Range

2.7

5.5

CAT525

Doc. No. 25078-00 4/01 - A M-1

A. C. TIMING DIAGRAM

1 2 3 4 5

CLK

t H CLK

Rising CLK edge to f

alling CLK edge

t L CLK

alling CLK edge to CLK r

ising edge

t CSH

alling CLK edge f

or last data bit (DI)

to f

alling CS edge

t CSS

Rising CS edge to ne

xt r

ising CLK edge

t CSMIN

alling CS edge to r

ising CS edge

t DIS

Data v

alid to first r

ising CLK

edge after CS = high

t DIH

Rising CLK edge to end of data v

alid

t DO0

Rising CLK edge to D0 = lo

t LZ

Rising CS edge to D0 becoming high

w impedance (activ

e output)

t DO1

Rising CLK edge to D0 = high

t HZ

alling CS edge to D0 becoming high

impedance (T

r
i-State)

Rising PR

OG edge to ne

xt r

ising

CLK edge

alling CLK edge after PR

OG=H

r
ising RD

BSY

edge

t H CLK

t L CLK

t CSH

t CSS

t CSMIN

t DIS

t DIH

t DO0

t LZ

t DO1

t HZ

TIMING

MIN/MAX

Min

Max

(Max)

Max

(Max)

Min

ARAM

NAME

Y/BSY

t B

USY

Rising PR

OG edge to f

alling

OG edge

t PS

t PR

Max

t PS

1 2 3 4 5

t B

USY

CAT525

Doc. No. 25078-00 4/01 - A M-1

PIN DESCRIPTION

Pin

Name

Function

REF

Maximum DAC 2 output voltage

REF

Maximum DAC 1 output voltage

Power supply positive

CLK

Clock input pin

RDY/

BSY

Ready/Busy output

Chip select

Serial data input pin

Serial data output pin

PROG

EEPROM Programming Enable
Input

GND

Power supply ground

REF

Minimum DAC 1 output voltage

REF

Minimum DAC 2 output voltage

REF

Minimum DAC 3 output voltage

REF

Minimum DAC 4 output voltage

OUT

DAC 4 output

OUT

DAC 3 output

OUT

DAC 2 output

OUT

DAC 1 output

REF

Maximum DAC 4 output voltage

REF

Maximum DAC 3 output voltage

DEVICE OPERATION

The CAT525 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be adjusted without altering the stored
output setting, which is useful for testing new output
settings before storing them in memory.

DIGITAL INTERFACE

The CAT525 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic "1" as a start bit. The DAC
address and data are clocked into the DI pin on the
clock's rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.

Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.

CHIP SELECT

Chip Select (CS) enables and disables the CAT525's
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.

Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.

CLOCK

The CAT525's clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock's rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.

No clock is necessary upon system power-up. The
CAT525's internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.

DAC addressing is as follows:

DAC OUTPUT

OUT

CAT525

Doc. No. 25078-00 4/01 - A M-1

As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.

REF

REF

, the voltage applied between pins V

REF

sets the DAC's Zero to Full Scale output range where
V

REF

L = Zero and V

REF

= Full Scale. V

REF

can span the

full power supply range or just a fraction of it. In typical
applications V

REF

L are connected across the

power supply rails. When using less than the full supply
voltage be mindfull of the limits placed on V

REF

H and

REF

L as specified in the References section of DC

Electrical Characteristics.

READY/

BUSY

When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/

BSY

) signals the start and

duration of the EEPROM erase/write cycle. Upon receiv-
ing a command to store data (PROG goes high) RDY/

BSY

goes low and remains low until the programming

cycle is complete. During this time the CAT525 will
ignore any data appearing at DI and no data will be
output on DO.

RDY/

BSY

is internally ANDed with a low voltage detec-

tor circuit monitoring V

DD.

If V

is below the minimum

value required for EEPROM programming, RDY/

BSY

will remain high following the program command indicat-
ing a failure to record the desired data in non-volatile
memory.

DATA OUTPUT

Data is output serially by the CAT525, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes

its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 525s to share a
single serial data line and simplifies interfacing multiple
525s to a microprocessor.

WRITING TO MEMORY

Programming the CAT525's EEPROM memory is ac-
complished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock's rising edge. The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.

Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of generating and ramping up the program-
ming voltage for data transfer to the EEPROM cells. The
CAT525's EEPROM memory cells will endure over
100,000 write cycles and will retain data for a minimum
of 20 years without being refreshed.

READING DATA

Each time data is transferred into a DAC control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC's output. This feature allows

Ps to

poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13

clock cycle completes. In doing so the EEPROM's

Figure 1. Writing to Memory

Figure 2. Reading from Memory

PROG

DAC

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12

CURRENT

DAC VALUE

NON-VOLATILE

CURRENT DAC DATA

RDY/BSY

NEW DAC DATA

CURRENT DAC DATA

CURRENT

DAC VALUE

NON-VOLATILE

DAC

OUTPUT

PROG

NEW

DAC VALUE

VOLATILE

NEW

DAC VALUE

NON-VOLATILE

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

RDY/BSY

CAT525

Doc. No. 25078-00 4/01 - A M-1

MSB LSB

1111 1111 ---- (.98 V ) + .01 V = .990 V V = +4.90V

1000 0000 ---- (.98 V ) + .01 V = .502 V V = +0.02V

0111 1111 ---- (.98 V ) + .01 V = .498 V V = -0.02V

0000 0001 ---- (.98 V ) + .01 V = .014 V V = -4.86V

0000 0000 ---- (.98 V ) + .01 V = .010 V V = -4.90V

REF REF REF

V = 5V

REF

255

OUT

DAC INPUT DAC OUTPUT ANALOG

R = R

OUTPUT

REF REF REF

OUT

128
255
127
255

REF REF REF

OUT

1
255

REF REF REF

OUT

REF REF REF

OUT

0
255

V = 0.99 V

FS REF

V = 0.01 V

ZERO

REF

V = ------ (V - V ) + V

DAC

CODE

255

ZERO ZERO

Figure 3. Temporary Change in Output

NEW DAC DATA

CURRENT DAC DATA

PROG

DAC

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

CURRENT

DAC VALUE

NON-VOLATILE

NEW

DAC VALUE

VOLATILE

CURRENT

DAC VALUE

NON-VOLATILE

RDY/BSY

setting is reloaded into the DAC control register. Since
this value is the same as that which had been there
previously no change in the DAC's output is noticed.
Had the value held in the control register been different
from that stored in EEPROM then

a change would occur

at the read cycle's conclusion.

TEMPORARILY CHANGE OUTPUT

The CAT525 allows temporary changes in DAC's output
to be made without disturbing the settings retained in
EEPROM memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.

Figure 3 shows the control and data signals needed to
effect a temporary output change. DAC settings may be
changed as many times as required and can be made to
any of the four DACs in any order or sequence. The
temporary setting(s) remain in effect long as CS remains
high. When CS returns low all four DACs will return to the
output values stored in EEPROM memory.

When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DAC control register prior to programming. This is be-
cause the CAT525's internal control circuitry discards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.

Amplified DAC Output

APPLICATION CIRCUITS

Bipolar DAC Output

OPT 505

GND

VDD

V H

REF

V L

REF

CONTROL
& DATA

OP 07

V = ( ) -V

OUT

R +

-15V

+15V

+5V

VDAC

For R =

V = 2V -V

OUT

DAC

OUT

CAT525

OPT 505

GND

VDD

V H

REF

V L

REF

CONTROL
& DATA

OP 07

OUT

-15V

+15V

+5V

V = (1 + ) V

OUT DAC

RF
RI

CAT525

CAT525

Doc. No. 25078-00 4/01 - A M-1

APPLICATION CIRCUITS (Cont.)

Coarse-Fine Offset Control by Averaging DPP Outputs

for Single Power Supply Systems

Coarse-Fine Offset Control by Averaging DPP Outputs

for Dual Power Supply Systems

OPT 505

LT 1029

I > 2 mA

V+

GND

VDD

V = 5.000V

REF

V H

REF

V L

REF

CONTROL
& DATA

OPT 505

GND

VDD

V H

REF

V L

REF

CONTROL
& DATA

15K

10 µF

5.1V

10K

4.02 K

1.00K

10 µF
35V

LM 324

1N5231B

MPT3055EL

28 - 32V

OUTPUT

0 - 25V
@ 1A

Digitally Trimmed Voltage Reference

Digitally Controlled Voltage Reference

CAT525

FINE ADJUST

DPP

COARSE ADJUST

DPP

GND

V L

REF

V H

REF

VDD

127RC

+5V

VREF

R = ----------

256 1

VREF

Fine adjust gives

1 LSB change in V

when V = ------

OFFSET

VREF

OFFSET

V OFFSET

FINE ADJUST

DPP

COARSE ADJUST

DPP

GND

V L

REF

V H

REF

VDD

127RC

+5V

REF

-V

REF

R = ----------------------

OFFSET

VOFFSET

REF

(+V ) - (V )

R = ----------------------

OFFSET

REF

(-V ) + (V )

CAT525

Doc. No. 25078-00 4/01 - A M-1

APPLICATION CIRCUITS (Cont.)

Staircase Window Comparator

Overlapping Window Comparator

CAT525

10K

+5V

WINDOW 2

10K

+5V

WINDOW 3

10K

+5V

WINDOW 4

10K

+5V

WINDOW 5

10K

+5V

WINDOW 1

GND

V L

REF

PROG

CLK

VPP

VDD

V H

REF

+5V

1.0

LM 339

DPP 1

DPP 2

DPP 3

DPP 4

WINDOW 1

WINDOW 2

WINDOW 3

WINDOW 4

WINDOW 5

REF

V 1

OUT

V 2

OUT

V 3

OUT

V 4

OUT

GND

WINDOW STRUCTURE

OPT 505

CAT525

10K

+5V

WINDOW 2

10K

+5V

WINDOW 3

10K

+5V

WINDOW 1

GND

V L

REF

PROG

CLK

VPP

VDD

V H

REF

+5V

1.0

LM 339

DPP 1

DPP 2

DPP 3

DPP 4

WINDOW 1

WINDOW 2

V 1

OUT

V 2

OUT

V 3

OUT

V 4

OUT

GND

WINDOW STRUCTURE

WINDOW 3

V H

REF

Part Number CAT525