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Part Number SD8901

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Wideband, Ring
Demodulator
SD8901
FEATURES
·
·
High Frequency Operation
·
·
Wide Dynamic Range
·
·
Low Capacitance
APPLICATIONS
·
·
Communications
·
·
RF Mixers
DESCRIPTION
The SD8901 is a ring demodulator/balanced mixer. Designed
to utilize Calogic's ultra high speed and low capacitance
lateral DMOS process. The SD8901 offers significant
performance improvements over JFET and diode balanced
mixers when low third order harmonic distortion has been a
problem.
PACKAGE INFORMATION
Part
Package
Temperature Range
SD8901HD Hermetic TO-78
-55
o
C to 125
o
C
SD8901CY Plastic Surface Mount
-55
o
C to 125
o
C
XSD8901
Sorted Chips in Carriers
-55
o
C to 125
o
C
CORPORATION
Functional block diagram
SO-14
TOP VIEW
1
LO
2
IF
2
LO
NC
SUB
SUB
SUB
NC
SUB
SUB
SUB
1
RF
2
RF
1
IF
PIN CONFIGURATIONS
LO
1
LO
2
IF
2
RF
2
RF
1
IF
1
SUBSTRATE
5
7
3
6
2
1
4
C
TO-78
LO
RF
LO
RF
IF
IF
1
2
2
1
1
2
1
2
3
4 5
BOTTOM VIEW
1
2
3
4
5
6
7
7
6
IF
RF
RF
CASE
LO
LO
IF
1
2
1
1
2
2
CD4
SD8901
CORPORATION
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
o
C unless otherwise noted)
V
DS
Drain to Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
V
DB
Drain to Substrate . . . . . . . . . . . . . . . . . . . . . . . . 22.5 V
V
SB
Source to Substrate . . . . . . . . . . . . . . . . . . . . . . . 22.5 V
V
GS
Gate to Source. . . . . . . . . . . . . . . . . . . . -22.5 V to 30 V
V
GB
Gate to Substrate. . . . . . . . . . . . . . . . . . . . -0.3V to 30 V
V
GD
Gate to Drain . . . . . . . . . . . . . . . . . . . . . . -22.5V to 30 V
I
D
Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . -55 to 125
o
C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150
o
C
Power Dissipation (A Package)* . . . . . . . . . . . . . . . . 640 mW
* Derate 5 mW/
o
C above 25
o
C
ELECTRICAL CHARACTERISTCIS (T
A
= +25
o
C unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN
TYP
MAX
UNIT
TEST CONDITIONS
STATIC
V
(BR)DS
Drain-Source
Breakdown Voltage
15
25
V
V
GS
= V
SB
= -5 V
Is = 10 nA
V
(BR)SD
Source-Drain
Breakdown Voltage
15
V
GD
= V
DB
= - 5 V
I
D
= 10 nA
V
(BR)DB
Drain-Substrate
Breakdown Voltage
22.5
Source Open
V
GB
= 0 V, I
D
= 10 nA
V
(BR)SB
Source-Substrate
Breakdown Voltage
22.5
Drain Open
V
GB
= 0 V, I
D
= 10 nA
V
T
Threshold Voltage
0.1
1
2.0
V
DS
= V
GS
= V
T
I
S
= 1
µ
A, V
SB
= 0V
r
DS(ON)
Drain-Source
"ON" Resistance
50
75
I
D
= 1 mA
V
SB
= 0 V
V
GS
= 5 V
30
V
GS
= 10 V
23
V
GS
= 15 V
19
V
GS
= 20 V
r
DS(ON)
Resistance Matching
3
7
V
GS
= 5 V
DYNAMIC
C
gg
LO
1
- LO
2
Capacitance
4.4
pF
V
DS
= 0 V, V
BS
= -5.5 V
V
GS
= 4 V
L
c
Conversion Loss
8
dB
See Figure 1, PLO = +17 dBm
IMD
3
Third Order Intercept
+35
f
MAX
Maximum Operation Frequency
250
MHz
Note: Guaranteed by design, not subject to production test
PERFORMANCE COMPARISON
3rd ORDER INPUT
INTERCEPT POINT
(+dBM)
40
30
20
10
0
0
5
10
15
20
25
30
35
POWER LOCAL OSC. (+dBm)
U350
DIODE RING
SD8901
SD8901
CORPORATION
FIGURE 2. First and third Quadrand I-E Characteristic Showing Effect of Gate Voltage Leading to Large-Signal
Overload Distortion.
FIGURE 1.
SIGNAL
T4-1
+VGG
T4-1
L O
680 pF
-Vu
T1-1T
OR
T4-1
i-f
u
LOW-PASS
IMAGE TERMINATING
FILTER
(OPTIONAL)
680 pF
SD8901
u
u
u
ID (ma)
50.00
10.00
/DIV
-50.00
-5.000
VDS
0
(V)
5.000
0
1.000/DIV
16 V
12 V
8 V
4 V
0 V