B C M 8 1 1 8 F E A T U R E S
10 Gbps CDR
10 Gbps
Optical Receiver
BCM8118
Application Block Diagram
·
Delivers superior 10.7-Gbps performance for OC-
192/STM-64 and 802.3ae applications.
·
Features a small footprint for high-density
applications.
·
Includes low-power operation for increased system
reliability.
·
Uses the most effective silicon economy of scale for
CMOS-based devices.
·
Exceeds SONET jitter requirements.
·
Target applications:
· Optical transceiver modules
· SONET and Ethernet optical interfaces
S U M M A R Y O F B E N E F I T S
D I F F E R E N T I A L 1 0 . 7 G b p s L I M I T I N G A M P L I F I E R
PRODUCT
Brief
B C M 8 1 1 8
·
30 dB gain
·
550 mVpp output swing
·
6 x 6 mm BGA package
·
1.8V power supply
·
Standard CMOS fabrication process
·
Power dissipation: 150 mW typical at 1.8V
The BCM8118 differential 10.7 Gbps limiting amplifier provides
post-amplification of low-level signals between an optical
receiver and the CDR inputs. It provides a typical differential
output voltage of 550 mVpp for input signals between 20 and
2000 mVpp, differential.
The differential input stage of the device contains internal DC
biasing, which allows AC coupling of the input signals. The
BCM8118 is packaged in a 6 x 6 mm, 36-pin BGA.
B C M 8 1 1 8 O V E R V I E W
VDD1
Ferrite
VDD2
OUTP
OUTN
INP
INN
1.0
1.0
µ
F
µ
F
10
100
µ
F
pF
1.0
1.0
µ
F
µ
F
50
50
Application Schematic
Phone: 949-450-8700
FAX: 949-450-8710
Email: info@broadcom.com
Web: www.broadcom.com
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Irvine, California 92619-7013
© 2002 by BROADCOM CORPORATION. All rights reserved.
8118-PB02-R-3.5.02
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