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Part Number ATAR862-4

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1
Features
·
Single Package Fully-integrated ROM Mask 4-bit Microcontroller with RF Transmitter
·
Low Power Consumption in Sleep Mode (< 1 µA Typically)
·
Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)
·
2.0 V to 4.0 V Operation Voltage for Single Li-cell Power Supply
·
-40
°
C to +125
°
C Operation Temperature
·
SSO24 Package
·
About Seven External Components
·
Flash Controller for Application Program Available
Description
The ATAR862-4 is a single package triple-chip circuit. It combines a UHF ASK/FSK
transmitter with a 4-bit microcontroller and a 512-bit EEPROM. It supports highly inte-
grated solutions in car access and tire pressure monitoring applications, as well as
manifold applications in the industrial and consumer segment. It is available for the
frequency range of 429 MHz to 439 MHz with data rates up to 32 kbaud.
For further frequency ranges such as 310 MHz to 330 MHz and 868 MHz to 928 MHz
separate data sheets are available.
The device contains a ROM mask version microcontroller and an additional data
EEPROM.
Figure 1. Application Diagram
Antenna
Micro-
controller
PLL-
Transmitter
ATAR862-4
Keys
UHF ASK/FSK
Receiver
Micro-
controller
Microcontroller
with UHF
ASK/FSK
Transmitter
ATAR862-4
Preliminary
Rev. 4552B­4BMCU­02/03
2
ATAR862-4
4552B­4BMCU­02/03
Pin Configuration
Figure 2. Pinning SSO24
XTAL
VS
GND
ENABLE
NRESET
BP63/T3I
BP20/NTE
BP23
BP41/T2I/VMI
BP42/T2O
BP43/SD/INT3
VSS
ANT1
ANT2
PA_ENABLE
CLK
BP60/T3O
OSC2
OSC1
BP50/INT6
BP52/INT1
BP53/INT1
BP40/SC/INT3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Pin Description: RF Part
Pin
Symbol
Function
Configuration
1
XTAL
Connection for crystal
2
VS
Supply voltage
ESD protection circuitry (see Figure 8)
3
GND
Ground
ESD protection circuitry (see Figure 8)
4
ENABLE
Enable input
XTAL
1.2k
VS
1.5k
VS
182 mA
ENABLE
200k
3
ATAR862-4
4552B­4BMCU­02/03
21
CLK
Clock output signal for microcontroller
The clock output frequency is set by the
crystal to f
XTAL
/4
22
PA_ENABLE
Switches on power amplifier, used for
ASK modulation
23
24
ANT2
ANT1
Emitter of antenna output stage
Open collector antenna output
Pin Description: RF Part (Continued)
Pin
Symbol
Function
Configuration
CLK
VS
100
100
PA_ENABLE
50k
Uref=1.1V
20 mA
ANT1
ANT2
Pin Description: Microcontroller Part
Name
Type
Function
Alternate Function
Pin-No.
Reset State
V
DD
­
Supply voltage
­
13
NA
V
SS
­
Circuit ground
­
12
NA
BP20
I/O
Bi-directional I/O line of Port 2.0
NTE-test mode enable, see also section "Master Reset"
7
Input
BP40
I/O
Bi-directional I/O line of Port 4.0
SC-serial clock or INT3 external interrupt input
14
Input
BP41
I/O
Bi-directional I/O line of Port 4.1
VMI voltage monitor input or T2I external clock input
Timer 2
9
Input
BP42
I/O
Bi-directional I/O line of Port 4.2
T2O Timer 2 output
10
Input
BP43
I/O
Bi-directional I/O line of Port 4.3
SD serial data I/O or INT3-external interrupt input
11
Input
BP50
I/O
Bi-directional I/O line of Port 5.0
INT6 external interrupt input
17
Input
BP52
I/O
Bi-directional I/O line of Port 5.2
INT1 external interrupt input
16
Input
BP53
I/O
Bi-directional I/O line of Port 5.3
INT1 external interrupt input
15
Input
BP60
I/O
Bi-directional I/O line of Port 6.0
T3O Timer 3 output
20
Input
BP63
I/O
Bi-directional I/O line of Port 6.3
T3I Timer 3 input
6
Input
OSC1
I
Oscillator input
4-MHz crystal input or 32-kHz crystal input or external
clock input or external trimming resistor input
18
Input
OSC2
O
Oscillator output
4-MHz crystal output or 32-kHz crystal output or external
clock input
19
Input
NRESET
I/O
Bi-directional reset pin
­
5
I/O
4
ATAR862-4
4552B­4BMCU­02/03
UHF ASK/FSK Transmitter Block
Features
·
Integrated PLL Loop Filter
·
ESD Protection (4 kV HBM/200 V MM, Except Pin 2: 4 kV HBM/100 V MM) also at ANT1/ANT2
·
Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)
·
Modulation Scheme ASK/FSK
­ FSK Modulation is Achieved by Connecting an Additional Capacitor between the XTAL Load Capacitor and the Open-
drain Output of the Modulating Microcontroller
·
Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
·
Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40
°
C to +125
°
C
·
Single-ended Antenna Output with High Efficient Power Amplifier
·
External CLK Output for Clocking the Microcontroller
·
125
°
C Operation for Tire Pressure Systems
Description
The PLL transmitter block has been developed for the demands of RF low-cost transmission systems, at data rates up to
32 kbaud. The transmitting frequency range is 429 MHz to 439 MHz. It can be used in both FSK and ASK systems.
5
ATAR862-4
4552B­4BMCU­02/03
Figure 3. Block Diagram
CLK
PA_ENABLE
ANT2
ANT1
ENABLE
GND
VS
XTAL
VCO
LF
CP
PFD
f
32
XTO
PLL
PA
f
4
Power up /
down
Voltage monitor
External input
UTCM
OSC1
OSC2
I/O bus
ROM
RAM
4-bit CPU core
256 x 4 bit
Data direction +
alternate function
Data direction +
interrupt control
Port 4
Port 5
Data direction +
alternate function
Port 6
Timer 3
Brown-out protect.
RESET
Clock management
Timer 1
watchdog timer
Timer 2
Serial interface
Port 1
P
o
r
t

2
D
a
t
a

d
i
r
e
c
t
i
o
n
T2O
SD
SC
T3O
T3I
BP10
BP13
BP20/NTE
BP21
BP22
BP23
RC
oscillators
Crystal
oscillators
4 K x 8 bit
VMI
with modulator
SSI
External
clock input
interval- and
8/12-bit timer
8-bit
timer / counter
with modulator
and demodulator
T2I
EEPROM
32 x 16 bit
BP40
INT3
SC
T2I
BP41
VMI
SD
BP43
INT3
BP42
T2O
BP53
INT1
BP52
INT1
BP50
INT6
BP51
INT6
BP60
T3O
BP63
T3I
V SS
V DD
NRESET
µC
ATAR862-4