Features
·
SPI for Microcontroller Connection with Up to 1 Mbit/s
·
Internal Data Buffer for Timing-independent Data Transmission
·
Programmable Driver Current Regulation
·
One-chip Antenna Driver Stage for 1 A Peak Current
·
LF Baud Rates Between 1 kbaud and 4 kbaud
·
Quick Start Control (QSC) for Fast Oscillation Build-up and Decay Timing
·
Integrated Oscillator for Ceramic Resonators
·
Power Supply Range from 7.5 V to 16 V Direct Battery Input
(Up to 28 V With Limited Function Range)
·
Amplitude Shift Keying (ASK) Modulation
·
Phase Shift Keying (PSK) Modulation
·
Carrier Frequency Range from 100 kHz to 150 kHz
·
Operational Temperature -40°C to +105°C
·
EMI and ESD According to Automotive Requirements
·
Highly Integrated -- Less External Components Required
Applications
·
Hands-free Car Access (Passive Entry/Go)
·
Tire Pressure Measurement
·
Home Access Control
·
Care Watch Systems
Benefits
·
Diagnosis Function and Overtemperature Protection
·
Load Dump Protection Up to 45 V for 12 V Boards
·
Power-down Mode for Minimum Power Consumption
Electrostatic sensitive device.
Observe precautions for handling.
Description
The ATA5278 device is an integrated BCDMOS antenna driver IC dedicated as a
transmitter for Passive Entry/Go (PEG) car applications and for other hands-free
access control applications.
It includes the full functionality of generating a magnetic LF field in conjunction with an
antenna coil to transmit data to a receiver in a key fob, card or transponder. A micro-
controller can access the chip via a bi-directional serial interface.
Stand-alone
Antenna Driver
ATA5278
Preliminary
Rev. 4832ARKE10/04
2
ATA5278 [Preliminary]
4832ARKE10/04
Figure 1. Block Diagram
Pin Configuration
Figure 2. Pinning QFN28
5-V
regulator
Oscillator
SPI
ATA5278
Boost
converter
control
Driver control
logic
Control
and
status
register
Current and
zero crossing
sensing
TEST
DGND
SCANE
AGND
VSHUNT
QSC
DRV1
CBOOST
PGND1
PGND2
VDS
VL1 VL2 VL3
VBATT
VDD
OSCI OSCO
CLKO
PGND3
CINT
S_CS
S_CLK
S_DI
S_DO
LF data buffer
LS driver
HS driver
MODACTIVE
NRES
Voltage
interface
VIF
PGND1
PGND2
PGND3
VDS
DRV1
CBOOST
QSC
S_CLK
S_CS
OSCI
OSCO
VIF
CLKO
TEST
VL
3
VL
2
VL
1
VBATT
VD
D
S_
D
O
S_
D
I
VSH
U
N
T
AG
N
D
DGN
D
CI
NT
M
O
DA
CT
I
V
E
NRES
SC
AN
E
8 9 10 11 12 13 14
28 27 26 25 24 23 22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
ATA5278
3
ATA5278 [Preliminary]
4832ARKE10/04
Pin Description
Pin
Symbol
Function
1
PGND1
Boost transistor ground
2
PGND2
Boost transistor ground
3
PGND3
Boost transistor ground
4
VDS
Driver voltage supply input
5
DRV1
Antenna driver stage output
6
CBOOST
External bootstrap capacitor connection
7
QSC
QSC transistor-gate driver-stage output
8
VSHUNT
Antenna current-shunt resistor connection
9
AGND
Analog ground (sensoric/antenna driver)
10
DGND
Digital ground (logic)
11
CINT
External integrator-capacitor connection
12
MODACTIVE
Modulator status pin output
13
NRES
Reset input (inverted)
14
SCANE
For factory test purposes only (connect to ground)
15
TEST
For factory test purposes only (connect to ground)
16
CLKO
Clock signal output
17
VIF
Logic interface voltage supply
18
OSCO
Oscillator output (for resonator/crystal connection)
19
OSCI
Oscillator input (for external clock source or resonator/crystal connection)
20
S_CS
Chip select for serial interface
21
S_CLK
Clock input for serial interface
22
S_DI
Data input for serial interface
23
S_DO
Data output of serial interface
24
VDD
Internal 5 V stabilizing capacitor connection
25
VBATT
Battery supply
26
VL1
Coil connection for the boost converter low-side switch
27
VL2
Coil connection for the boost converter low-side switch
28
VL3
Coil connection for the boost converter low-side switch
4
ATA5278 [Preliminary]
4832ARKE10/04
Functional Description
General Description
The IC contains a half-bridge coil driver stage with a special driver voltage regulator and
control logic with diagnosis circuitry. It is controllable by a serial programming interface
(SPI).
In combination with an LC antenna circuitry, the IC generates an electromagnetic LF
field. The carrier frequency for the antenna is generated by the oscillator and a pre-
scaler logic.
The LF field can be modulated to transmit data to a suitable receiver. Two modulation
modes are available: Amplitude Shift Keying (ASK) and 180° Phase Shift Keying (PSK).
The transmission data has to be stored in the internal data buffer.
The IC consists of two main functional blocks:
·
The SPI with the data buffer, the control registers and the oscillator
·
The driver stage with its control logic and the power supply stage
A boost converter is used to supply the driver half-bridge with a high voltage and a regu-
lated current even if the battery voltage is low. The antenna current is programmable in
16 steps to support a transmission with various field strengths.
The driver circuitry is protected against short-circuits and overload.
Operational States
After power-on-reset, the ATA5278 is in power-down mode. To achieve minimum power
consumption, only the internal 5-V supply and the control registers are active. The IC
can only be activated by the external control unit via the serial interface (i.e., the chip
select line is enabled).
Once activated, the chip keeps the oscillator active and waits for commands on the
serial bus. This state can be described as standby mode. Only upon an external reset or
on command followed by disabling the chip select line, the power-down mode is re-
invoked.
The modulator stage, together with the antenna driver and the power supply, is acti-
vated as soon as LF data is written into the buffer and remains in this state until all data
has been sent, a stop command has been given via the SPI or a fault occurred. The
data modulation is running independently of the SPI activity and can be monitored with
the MODACTIVE pin.
Power-down Mode
The ATA5278 should be kept in power-down mode as long as the LF channel is not
used, because not only is the current consumption minimal, but the internal logic is also
reset. The antenna driver stage is in high impedance mode. To power-up the chip, the
chip-select line (S_CS) has to be activated for an appropriate time. The SPI then starts
the internal oscillator which is necessary for proper operation. Only after a certain oscil-
lation build-up time, is full functionality available. The microcontroller can check out the
state of the IC with two state bits automatically returned by any SPI command.
5
ATA5278 [Preliminary]
4832ARKE10/04
Figure 3. Power-up Timing
The startup time, t
startup
, in Figure 3 depends on the clock source used in the application.
Typical oscillation build-up times are below 100 µs for ceramic and about 1 ms for crys-
tal resonators. When using an active clock source, the startup time can be neglected.
The internal logic debounces the first clock signals until it finally powers-up the IC for the
time t
deb
. Note that during this time, the chip select signal S_CS has to be permanently
active.
The normal way to bring the chip back into power-down mode is to use an SPI com-
mand. Deactivating the chip-select line right after the power-down command, an internal
standby timer is started and will run for t
timeout
= (2048/f
OSCI
). In this time, the antenna
driver stage is stopped to discharge any energies possibly remaining in the antenna
circuit. If the chip-select line is reactivated during this time, the sequence is interrupted
and the IC remains in standby mode. Otherwise, the power-down mode is engaged after
the timeout, the oscillator is stopped and the driver stages are switched to high imped-
ance. Figure 4 illustrates this behavior.
Figure 4. Power-down Timing
Note that if command 4 is omitted and only the chip-select line is disabled, the ATA5278
stays operational (i.e., the oscillator keeps running, an eventually running LF data mod-
ulation is not interrupted). Here, only the SPI itself is disabled and the serial bus can be
used for other devices connected to it.
Z
t
startup
Legend: Z = high impedance
S_CS
QSC
DRV1
OSCI/OSCO
Oscillation build-up
Steady oscillation
t
deb
S_CS
S_CLK
S_DI
DRV1
OSC
X
8 CLK
cmd 4
f = 8 MHz
Z
t
timeout
Legend: X = do not care
Z = high impedance
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