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Preliminary Information

Contents

iii

21896E/0--May 2000

Mobile AMD-K6

-2 Processor Data Sheet

Preliminary Information

Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

About This Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii

Part One

Mobile AMD-K6

-2 Processor

Mobile AMD-K6

-2 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1

Super7TM Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Super7 Platform Enhancements: . . . . . . . . . . . . . . . . . . . . . . . . 5

Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Mobile AMD-K6

-2 Processor Microarchitecture

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Enhanced RISC86

Microarchitecture . . . . . . . . . . . . . . . . . . . 8

2.3

Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . 11
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4

Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5

Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6

Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register X and Y Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.7

Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Branch History Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Branch Target Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Mobile AMD-K6-2 Processor Operation . . . . . . . . . . . . . . . . . 37

5.1

Process Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2

Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Contents

Mobile AMD-K6

-2 Processor Data Sheet

21896E/0--May 2000

Preliminary Information

Stop Grant Inquire State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3

System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . 42
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SMM Operating Mode and Default Register Values . . . . . . . 42
SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I/O Trap Dword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . . . 51

Signal Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 53

6.1

CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 53

6.2

Clock Switching Characteristics for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.3

Clock Switching Characteristics for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.4

Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . . 55

6.5

Output Delay Timings for 100-MHz Bus Operation . . . . . . . 56

6.6

Input Setup and Hold Timings for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.7

Output Delay Timings for 66-MHz Bus Operation . . . . . . . . 60

6.8

Input Setup and Hold Timings for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.9

RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . 64

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.1

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.2

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.3

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.4

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.5

Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . . 77
Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 77

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.1

Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . 79
Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 82

Contents

21896E/0--May 2000

Mobile AMD-K6

-2 Processor Data Sheet

Preliminary Information

Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.1

321-Pin Staggered CPGA Package Specification . . . . . . . . . 83

9.2

360-Pin Model 8 CBGA Package Specification . . . . . . . . . . . 85

9.3

360-Pin CBGA Mechanical Specification . . . . . . . . . . . . . . . . 87

Pin Description Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.1

360-Pin CBGA Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.2

321-Pin CPGA Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 91

10.3

Pin Designations by Functional Grouping . . . . . . . . . . . . . . . 93

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Part Two

Mobile AMD-K6-2-P Processor

Mobile AMD-K6-2-P Processor . . . . . . . . . . . . . . . . . . . . . . . . . 99

12.1

Super7 Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Super7 Platform Enhancements: . . . . . . . . . . . . . . . . . . . . . . 101

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.1

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.2

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.3

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.4

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

13.5

Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . 110
Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . . . 111

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

14.1

Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 113
Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Part Number AMD-K6-2

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