ADG3301 Low Voltage 1.15 V to 5.5 V, Single-Channel Bidirectional Logic Level Translator Preliminary Data Sheet (Rev. PrA)

Low Voltage 1.15 V to 5.5 V, Single-Channel

Bidirectional Logic Level Translator

Preliminary Technical Data

ADG3301

Rev.Pr.A 1 February 2005

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

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Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

FEATURES

Bidirectional level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 1 µA
No direction pin

APPLICATIONS

SPI®, MICROWIRE® level translation
Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communication devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
Portable POS systems
Low cost serial interfaces

FUNCTIONAL BLOCK DIAGRAM

GND

VCCY

VCCA

Figure 1.

GENERAL DESCRIPTION

The ADG3301 is a single channel bidirectional logic level
translator. It can be used in multivoltage digital system
applications such as data transfer between a low voltage
DSP/controller and a higher voltage device. The internal
architecture allows the device to perform bidirectional logic
level translation without an additional signal to set the direction
in which the translation takes place.

The voltage applied to V

CCA

sets the logic levels on the A side of

the device, while V

CCY

sets the levels on the Y side. For proper

operation, V

CCA

must always be less than V

CCY

. The V

CCA-

compatible logic signals applied to the A pin appear as V

CCY

compatible levels on the Y pin. Similarly, V

CCY

-compatible logic

levels applied to the Y pin appear as V

CCA

-compatible logic

levels on the A pin.

The enable pin (EN) provides three-state operation on both the
A-side and the Y-side pins. When the device enable pin is pulled
low, the terminals on both sides of the device are in the high
impedance state. The EN pin is referred to the V

CCA

supply

voltage and driven high for normal operation.

The ADG3301 is available in compact 6 lead SC70 package and
is guaranteed to operate over the 1.15 V to 5.5 V supply voltage
range and extended -40°C to +85°C temperature range.

PRODUCT HIGHLIGHTS

1. Bidirectional

level

translation.

2. Fully guaranteed over the 1.15 V to 5.5 V supply range.

3. No direction pin.

4. Compact 6 lead SC70 package.

ADG3301

Preliminary Technical Data

Rev. Pr.A | Page 2 of 18

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

Pin Configurations and Function Descriptions ....................... 6

ESD Caution.................................................................................. 6

Typical Performance Characteristics ............................................. 7

Test Circuits..................................................................................... 11

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

Level Translator Architecture ................................................... 15

Input Driving Requirements..................................................... 15

Output Load Requirements ...................................................... 15

Enable Operation ....................................................................... 15

Power Supplies ............................................................................ 15

Data Rate ..................................................................................... 16

Applications..................................................................................... 17

Layout Guidelines....................................................................... 17

Outline Dimensions ....................................................................... 18

Preliminary Technical Data

ADG3301

Rev. Pr.A| Page 3 of 18

SPECIFICATIONS

CCY

= 1.65 V to 5.5 V, V

CCA

= 1.15 V to V

CCY

, GND = 0 V. All specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 1.

Parameter Symbol

Conditions

Min

Typ

Max Unit

LOGIC INPUTS/OUTPUTS

A Side

Input High Voltage

IHA

CCA

= 1.15 V

CCA

- 0.3

IHA

CCA

= 1.2 V to 5.5 V

CCA

- 0.4

Input Low Voltage

ILA

0.4

Output High Voltage

OHA

= V

CCY

, I

= 20 µA, Figure 27

CCA

- 0.4

Output Low Voltage

OLA

= 0 V, I

= 20 µA, Figure 27

0.4

Capacitance

f = 1 MHz, EN = 0, Figure 32

Leakage Current

LA, HiZ

= 0 V/V

CCA

, EN = 0, Figure 29

±1

µA

Y Side

Input Low Voltage

IHY

CCY

- 0.4

Input High Voltage

ILY

0.4

Output High Voltage

OHY

= V

CCA

, I

= 20 µA, Figure 28

CCY

- 0.4

Output Low Voltage

OLY

= 0 V, I

= 20 µA, Figure 28

0.4

Capacitance

f = 1 MHz, EN = 0, Figure 33

Leakage Current

LY, HiZ

= 0 V/V

CCY

, EN = 0, Figure 30

±1

µA

Enable (EN)

Input High Voltage

IHEN

CCA

= 1.15 V

CCA

- 0.3

IHEN

CCA

= 1.2 V to 5.5 V

CCA

- 0.4

Input Low Voltage

ILEN

0.4

Leakage Current

LEN

= 0 V/V

CCA

, V

= 0 V, Figure 31

±1

µA

Capacitance

Enable Time

= R

= 50 , V

= 0 V/V

CCA

Y),

= 0 V/V

CCY

A), Figure 34

1.8

µs

SWITCHING CHARACTERISTICS

3.3 V ± 0.3V

CCA

CCY,

, V

CCY

= 5 V ± 0.5 V

Y Level Translation

= R

= 50 , C

= 50 pF, Figure 35

Propagation Delay

P, A-Y

Rise Time

R, A-Y

2 3.5 ns

Fall Time

F, A-Y

2 3.5 ns

Maximum Data Rate

MAX, A-Y

Mbps

Channel-to-Channel Skew

SKEW, A-Y

2 4

Part-to-Part Skew

PPSKEW, A-Y

A Level Translation

= R

= 50 , C

= 15 pF, Figure 36

Propagation Delay

P, Y-A

Rise Time

R, Y-A

1 3 ns

Fall Time

F, Y-A

3 7 ns

Maximum Data Rate

MAX, Y-A

Mbps

Channel-to-Channel Skew

SKEW, Y-A

2 3.5 ns

Part-to-Part Skew

PPSKEW, Y-A

1.8 V ± 0.15 V

CCA

CCY

, V

CCY

= 3.3 V ± 0.3 V

Y Translation

= R

= 50 , C

= 50 pF, Figure 35

Propagation Delay

P, A-Y

Rise Time

R, A-Y

2 5 ns

Fall Time

F, A-Y

2 5 ns

Maximum Data Rate

MAX, A-Y

Mbps

Channel-to-Channel Skew

SKEW, A-Y

2 4

Part-to-Part Skew

PPSKEW, A-Y

ADG3301

Preliminary Technical Data

Rev. Pr.A | Page 4 of 18

Parameter Symbol

Conditions

Min

Typ

Max Unit

A Translation

= R

= 50 , C

= 15 pF, Figure 36

Propagation Delay

P, Y-A

Rise Time

R, Y-A

2 3.5 ns

Fall Time

F, Y-A

2 3.5 ns

Maximum Data Rate

MAX, Y-A

Mbps

Channel-to-Channel Skew

SKEW, Y-A

2 3

Part-to-Part Skew

PPSKEW, Y-A

1.15 V to 1.3 V

CCA

CCY

, V

CCY

= 3.3 V ± 0.3 V

Y Translation

= R

= 50 , C

= 50 pF, Figure 35

Propagation Delay

P, A-Y

Rise Time

R, A-Y

3 5 ns

Fall Time

F, A-Y

2 5 ns

Maximum Data Rate

MAX, A-Y

Mbps

Channel-to-Channel Skew

SKEW, A-Y

2 5

Part-to-Part Skew

PPSKEW, A-Y

A Translation

= R

= 50 , C

= 15 pF, Figure 36

Propagation Delay

P, Y-A

Rise Time

R, Y-A

2 4 ns

Fall Time

F, Y-A

2 4 ns

Maximum Data Rate

MAX, Y-A

Mbps

Channel-to-Channel Skew

SKEW, Y-A

2 4

Part-to-Part Skew

PPSKEW, Y-A

1.15 V to 1.3 V

CCA

CCY

, V

CCY

= 1.8 V ± 0.3 V

Y Translation

= R

= 50 , C

= 50 pF, Figure 35

Propagation Delay

P, A-Y

Rise Time

R, A-Y

7 12 ns

Fall Time

F, A-Y

3 5 ns

Maximum Data Rate

MAX, A-Y

Mbps

Channel-to-Channel Skew

SKEW, A-Y

2 5

Part-to-Part Skew

PPSKEW, A-Y

A Translation

= R

= 50 , C

= 15 pF, Figure 36

Propagation Delay

P, Y-A

Rise Time

R, Y-A

5 16 ns

Fall Time

F, Y-A

2.5

6.5 ns

Maximum Data Rate

MAX, Y-A

Mbps

Channel-to-Channel Skew

SKEW, Y-A

3 6.5 ns

Part-to-Part Skew

PPSKEW, Y-A

23.5 ns

2.5 V ± 0.2 V

CCA

CCY

, V

CCY

= 3.3 V ± 0.3 V

Y Translation

= R

= 50 , C

= 50 pF, Figure 35

Propagation Delay

P, A-Y

Rise Time

R, A-Y

2.5

4 ns

Fall Time

F, A-Y

2 5 ns

Maximum Data Rate

MAX, A-Y

Mbps

Channel-to-Channel Skew

SKEW, A-Y

1.5 2

Part-to-Part Skew

PPSKEW, A-Y

A Translation

= R

= 50 , C

= 15 pF, Figure 36

Propagation Delay

P, Y-A

Rise Time

R, Y-A

1 4 ns

Fall Time

F, Y-A

3 5 ns

Maximum Data Rate

MAX, Y-A

Mbps

Channel-to-Channel Skew

SKEW, Y-A

2 3

Part-to-Part Skew

PPSKEW, Y-A

Preliminary Technical Data

ADG3301

Rev. Pr.A| Page 5 of 18

Parameter Symbol

Conditions

Min

Typ

Max Unit

POWER REQUIREMENTS

Power Supply Voltages

CCA

CCY

1.15 5.5

CCY

1.65 5.5

Quiescent Power Supply Current

CCA

= 0 V/V

CCA

= 0 V/V

CCY

CCA

= V

CCY

= 5.5 V, EN = 1

0.17

µA

CCY

= 0 V/V

CCA

, V

= 0 V/V

CCY

CCA

= V

CCY

= 5.5 V, EN = 1

0.27

µA

Three-State Mode Power Supply Current

HiZA

CCA

= V

CCY

= 5.5 V, EN = 0

0.1

µA

HiZY

CCA

= V

CCY

= 5.5 V, EN = 0

0.1

µA

Temperature range is a follows: B version: -40°C to +85°C.

All typical values are at T

= 25°C, unless otherwise noted.

Guaranteed by design; not subject to production test.

ADG3301

Preliminary Technical Data

Rev. Pr.A | Page 6 of 18

ABSOLUTE MAXIMUM RATINGS

= 25°C, unless otherwise noted.

Table 2.

Parameter Rating

CCA

to GND

-0.3 V to +7 V

CCY

to GND

CCA

to +7 V

Digtal Inputs (A)

-0.3 V to (V

CCA

+ 0.3 V)

Digtal Inputs (Y)

-0.3 V to (V

CCY

+ 0.3 V)

EN to GND

-0.3 V to +7 V

Operating Temperature Range

Industrial (B Version)

-40°C to +85°C

Storage Temperature Range

-65°C to +150°C

Junction Temperature

150°C

Thermal Impedance (4-Layer Board)

6 Lead SC70

332

C/W

Lead Temperature, Soldering (10 sec)

300°C

IR Reflow, Peak Temperature (< 20 sec)

260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

ADG3301

TOP VIEW

(Not to Scale)

VCCA

6 VCCY

5 Y1

Figure 2. 6-Lead SC70

Table 3 Pin Function Descriptions

Pin No.

Mnemonic

Description

1 V

CCA

Power Supply Voltage Input for the A I/O Pin (1.15 V V

CCA

CCY

2 A

Input/Output A. Referenced to V

CCA

3 GND

Ground.

Active High Enable input.

Input/Output A4. Referenced to V

CCA

6 V

CCY

Power Supply Voltage Input for the Y I/O Pin (1.65 V V

CCY

5.5V).

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADG3301

Preliminary Technical Data

Rev. Pr.A | Page 14 of 18

TERMINOLOGY

Table 4.

Symbol Description

IHA

Logic input high voltage at Pin A.

ILA

Logic input low voltage at Pin A.

OHA

Logic output high voltage at Pin A.

OLA

Logic output low voltage at Pin A.

Capacitance measured at Pin A (EN = 0).

LA, HiZ

Leakage current at Pin A when EN = 0 (Pin A three-stated).

IHY

Logic input high voltage at Pin Y.

ILY

Logic input low voltage at Pin Y.

OHY

Logic output high voltage at Pin Y.

OLY

Logic output low voltage at Pin Y.

Capacitance measured at Pin Y (EN = 0).

LY, HiZ

Leakage current at Pin Y when EN = 0 (Pin Y three-stated).

IHEN

Logic input high voltage at the EN pin.

ILEN

Logic input low voltage at the EN pin.

Capacitance measured at EN pin.

LEN

Enable (EN) pin leakage curent.

Three-state enable time for Pins A /Y.

P, A-Y

Propagation delay when translating logic levels in the A

Y direction.

R, A-Y

Rise time when translating logic levels in the A

Y direction.

F, A-Y

Fall time when translating logic levels in the A

Y direction.

MAX, A-Y

Guaranteed data rate when translating logic levels in the A

Y direction under the driving and loading conditions

specified in Table 1.

SKEW, A-Y

Difference between propagation delays on any two channels when translating logic levels in the A

Y direction.

PPSKEW, A-Y

Difference in propagation delay between any one channel and the same channel on a different part (under same
driving/loading conditions) when translating in the A

Y direction.

P, Y-A

Propagation delay when translating logic levels in the Y

A direction.

R, Y-A

Rise time when translating logic levels in the Y

A direction.

F, Y-A

Fall time when translating logic levels in the Y

A direction.

MAX, Y-A

Guaranteed data rate when translating logic levels in the Y

A direction under the driving and loading conditions

specified in Table 1.

SKEW, Y-A

Difference between propagation delays on any two channels when translating logic levels in the Y

A direction.

PPSKEW, Y-A

Difference in propagation delay between any one channel and the same channel on a different part (under same
driving/loading conditions) when translating in the Y

A direction.

CCA

Power supply voltage at the V

CCA

pin.

CCY

Power supply voltage at the V

CCY

pin.

CCA

supply current.

CCY

supply current.

HiZA

CCA

supply current during three-state mode (EN = 0).

HiZY

CCY

supply current during three-state mode (EN = 0).

Preliminary Technical Data

ADG3301

Rev. Pr.A| Page 15 of 18

THEORY OF OPERATION

The ADG3301 level translator allows the level shifting
necessary for data transfer in a system where multiple supply
voltages are used. The device requires two supplies, V

CCA

and

CCY

CCA

CCY

). These supplies set the logic levels on each

side of the device. When driving the A pin, the device translates
the V

CCA

compatible logic levels to V

CCY

compatible logic levels

available at the Y pin. Similarly, since the device is capable of
bidirectional translation, when driving the Y pin the V

CCY

compatible logic levels are translated to V

CCA

-compatible logic

levels available at the A pin. When EN = 0, the A and Y pins are
three-stated. When EN is driven high, the ADG3301 goes into
normal operation mode and performs level translation.

LEVEL TRANSLATOR ARCHITECTURE

The ADG3301 consists of a single bidirectional channel that can
translate logic levels in either the A

Y or the Y

A direction. It

uses a one-shot accelerator architecture, which ensures excellent
switching characteristics. Figure 37 shows a simplified block
diagram of the ADG3301 level translator.

ONE-SHOT GENERATOR

CCA

CCY

04860-053

Figure 37. Simplified Block Diagram of an ADG3301 Channel

The logic level translation in the A

Y direction is performed

using a level translator (U1) and an inverter (U2), while the
translation in the Y

A direction is performed using the

inverters U3 and U4. The one-shot generator detects a rising or
falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS
transistors (T1T2) for a rising edge, or the NMOS transistors
(T3T4) for a falling edge. This charges/discharges the capacitive
load faster, which results in fast rise and fall times.

INPUT DRIVING REQUIREMENTS

To ensure correct operation of the ADG3301, the circuit that
drives the input of an ADG3301 channels must have an output
impedance of less than or equal to 150 and a minimum peak
current driving capability of 36 mA.

OUTPUT LOAD REQUIREMENTS

The ADG3301 level translator is designed to drive CMOS-
compatible loads. If current driving capability is required, it is
recommended to use buffers between the ADG3301 outputs
and the load.

ENABLE OPERATION

The ADG3301 provides three-state operation at the A and Y
I/O pins by using the enable (EN) pin as shown in Table 5.

Table 5. Truth Table

Y I/O Pin

A I/O Pin

0 Hi-Z

Hi-Z

1 Normal

operation

Normal operation

High impedance state.

In normal operation, the ADG3301 performs level translation.

While EN = 0, the ADG3301 enters into tri-state mode. In this
mode, the current consumption from both the V

CCA

and V

CCY

supplies is reduced, allowing the user to save power, which is
critical, especially on battery-operated systems. The EN input
pin can be driven with either V

CCA

- or V

CCY

-compatible logic

levels.

POWER SUPPLIES

For proper operation of the ADG3301, the voltage applied to
the V

CCA

must be always less than or equal the voltage applied to

CCY

. To meet this condition, the recommended power-up

sequence is V

CCY

first and then V

CCA

. The ADG3301 operates

properly only after both supply voltages reach their nominal
values. It is not recommended to use the part in a system where,
during power-up, V

CCA

may be greater than V

CCY

due to

significant increase in the current taken from the V

CCA

supply

For optimum performance, the V

CCA

and V

CCY

pins should be

decoupled to GND, and placed as close as possible to the device.

ADG3301

Preliminary Technical Data

Rev. Pr.A | Page 16 of 18

DATA RATE

The maximum data rate at which the device is guaranteed to
operate is a function of the V

CCA

and V

CCY

supply voltage

combination and the load capacitance. It is given by the
maximum frequency of a square wave that can be applied to the
device, which meets the V

and V

levels at the output and

does not exceed the maximum junction temperature (see the
Absolute Maximum Ratings).Table 6 shows the guaranteed
data rates at which the ADG3301 can operate in both directions
(A

Y or Y

A level translation) for various V

CCA

and V

CCY

supply combinations.

Table 6. Guaranteed Data Rate (Mbps)

CCY

CCA

1.8 V

(1.65 V to 1.95 V)

2.5 V

(2.3 V to 2.7 V)

3.3 V

(3.0 V to 3.6 V)

5 V

(4.5 V to 5.5 V)

1.2 V (1.15 V to 1.3 V)

25 30

1.8 V (1.65 V to 1.95 V)

- 45

2.5 V (2.3 V to 2.7 V)

- -

3.3 V (3.0 V to 3.6 V)

- -

5 V (4.5 V to 5.5 V)

- -

The load capacitance used is 50 pF when translating in the A

Y direction and 15 pF when translating in the YA direction.

Preliminary Technical Data

ADG3301

Rev. Pr.A| Page 17 of 18

APPLICATIONS

The ADG3301 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the A
pin, and the higher voltage logic signals to the Y pin. The
ADG3301 can provide level translation in both directions from
A

Y or Y

A, eliminating the need for a level translator IC for

each direction. The internal architecture allows the ADG3301
to perform bidirectional level translation without an additional
signal to set the direction in which the translation is made. It
also allows simultaneous data flow in both directions on the
same part, for example, two channels translate in AY direction
while the other two translate in YA direction. This simplifies
the design by eliminating the timing requirements for the
direction signal and reduces the number of ICs used for level
translation.

Figure 38 shows an application where a 1.8V microprocessors
transfers data to or from a 3.3V peripheral device using the
ADG3301 level translator.

VCCA

GND

VCCY

ADG3301

Microprocessor
/Microcontroller
/DSP

I/OL

I/OH

GND

1.8V

3.3V

100nF

Peripheral
Device

100nF

Figure 39. 1.8V to 3.3V level translation circuit

LAYOUT GUIDELINES

As with any high speed digital IC, the printed circuit board
layout is important for the overall performance of the circuit.
Care should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each V

pin (V

CCA

and

CCY

) should be bypassed using low effective series resistance

(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the V

CCA

and V

CCY

pins. The parasitic

inductance of the high speed signal track might cause
significant overshoot. This effect can be reduced by keeping the
length of the tracks as short as possible. A solid copper plane for
the return path (GND) is also recommended.

Part Number ADG3301