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2 pF Off Capacitance, 1 pC Charge Injection,
±15 V/12 V
iCMOSTM Dual SPDT Switch
Preliminary Technical Data
ADG1236
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
FEATURES
2 pF off capacitance
1 pC charge injection
33 V supply range
120 on resistance
Fully specified at +12 V, ±15 V
No V
L
supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 12-lead LFCSP packages
Typical power consumption: <0.03 µW
APPLICATIONS
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
FUNCTIONAL BLOCK DIAGRAM
ADG1236
D1
D2
S2B
S2A
IN2
IN1
S1B
S1A
SWITCHES SHOWN FOR A LOGIC 1 INPUT
04776-0-001
Figure 1.
GENERAL DESCRIPTION
The ADG1236 is a monolithic CMOS device containing two
independently selectable SPDT switches. It is designed on an
iCMOS process. iCMOS (industrial-CMOS) is a modular
manufacturing process combining high voltage CMOS
(complementary metal-oxide semiconductor) and bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 30 V operation in a footprint
that no previous generation of high voltage parts has been able
to achieve. Unlike analog ICs using conventional CMOS proc-
esses, iCMOS components can tolerate high supply voltages,
while providing increased performance, dramatically lower
power consumption, and reduced package size.
The ultralow capacitance and charge injection of the part make
it an ideal solution for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make the
part suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the part ideally
suited for portable and battery-powered instruments.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.
PRODUCT HIGHLIGHTS
1. 2 pF off capacitance (±15 V supply).
2. 1 pC charge injection.
3. 3 V logic-compatible digital inputs: V
IH
= 2.0 V, V
IL
= 0.8 V.
4. No
V
L
logic power supply required.
5. Ultralow power dissipation: <0.03 µW.
6. 16-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP
packages.
ADG1236
Preliminary Technical Data
Rev. PrD | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings............................................................ 6
Truth Table For Switches ............................................................. 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ............................7
Terminology .......................................................................................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 12
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
11/04--Revision PrD: Preliminary Version
Preliminary Technical Data
ADG1236
Rev. PrD | Page 3 of 16
SPECIFICATIONS
DUAL SUPPLY
V
DD
= 15 V ± 10%, V
SS
= -15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameters
25°C 85°C Y
Version
1
Unit Test
Conditions/Comments
ANALOG
SWITCH
Analog Signal Range
V
DD
to V
SS
V
On Resistance (R
ON
)
typ
V
S
= ±10 V, I
S
= -10 mA; Figure 21
120 220 260
max
On Resistance Match between
Channels (R
ON
)
5
typ
V
S
= ±10 V, I
S
= -10 mA
max
On Resistance Flatness (R
FLAT(ON)
)
25
typ
V
S
= -5 V/0 V/+5 V; I
S
= -10 mA
50
max
LEAKAGE
CURRENTS
V
DD
= +10 V, V
SS
= -10 V
Source Off Leakage, I
S
(Off) ±0.01
nA
typ
V
S
= 0 V/10 V, V
D
= 10 V/0 V; Figure 22
±0.5
±1 ±5 nA
max
Drain Off Leakage, I
D
(Off) ±0.01
nA
typ
V
S
= 0 V/10 V, V
D
= 10 V/0 V; Figure 22
±0.5
±1 ±5 nA
max
Channel On Leakage, I
D
, I
S
(On)
±0.04
nA
typ
V
S
= V
D
= 0 V or 10 V; Figure 23
±1 ±2 ±5 nA
max
DIGITAL
INPUTS
Input High Voltage, V
INH
2.0
V
min
Input Low Voltage, V
INL
0.8
V
max
Input Current, I
INL
or I
INH
0.005
µA
typ
V
IN
= V
INL
or V
INH
±0.5
µA max
Digital Input Capacitance, C
IN
5
pF
typ
DYNAMIC CHARACTERISTICS
2
t
ON
50
ns typ
R
L
= 50 , C
L
= 35 pF
ns max
V
S
= ±10 V; Figure 24
t
OFF
20
100 ns
typ
R
L
= 50 , C
L
= 35 pF
ns max
V
S
= ±10 V; Figure 24
Break-before-Make Time Delay, t
D
15
40 ns
typ
R
L
= 50 , C
L
= 35 pF
1 ns
min
V
S1
= V
S2
= 10 V; Figure 25
Charge
Injection
1
pC
typ
V
S
= 0 V, R
S
= 0 , C
L
= 1 nF; Figure 26
Off
Isolation
75
dB
typ
R
L
= 50 , C
L
= 5 pF, f = 1 MHz; Figure 27
Channel-to-Channel
Crosstalk
85
dB
typ
R
L
= 50 , C
L
= 5 pF, f = 1 MHz; Figure 28
Total Harmonic Distortion + Noise
0.002
% typ
R
L
= 600 , 5 V rms, f = 20 Hz to 20 kHz
-3 dB Bandwidth
700
MHz typ
R
L
= 50 , C
L
= 5 pF; Figure 29
C
S
(Off)
2
pF
typ
C
D
(Off)
2
pF
typ
C
D
, C
S
(On)
5
pF
typ
POWER
REQUIREMENTS
V
DD
= +16.5 V, V
SS
= -16.5 V
I
DD
0.001
µA typ
Digital Inputs = 0 V or V
DD
5.0 µA
max
I
DD
150
µA typ
Digital Input = 5 V
300 µA
max
I
SS
0.001
µA typ
Digital Inputs = 0 V or V
DD
5.0 µA
max
ADG1236
Preliminary Technical Data
Rev. PrD | Page 4 of 16
Parameters
25°C 85°C Y
Version
1
Unit Test
Conditions/Comments
I
GND
0.001
µA typ
Digital Inputs = 0 V or V
DD
5.0 µA
max
I
GND
150
µA typ
Digital Input = 5 V
300
µA max
1
Temperature range for Y Version is -40°C to +125°C.
2
Guaranteed by design, not subject to production test.
SINGLE SUPPLY
V
DD
= 12 V ± 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameters
25°C 85°C Y
Version
1
Unit Test
Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to V
DD
V
On Resistance (R
ON
)
220
typ
V
S
= +10 V, I
S
= -10 mA; Figure 21
max
On Resistance Match between
Channels (R
ON
)
10
typ
V
S
= +10 V, I
S
= -10 mA
max
On Resistance Flatness (R
FLAT(ON)
) 40
typ
V
S
= +3 V/+6 V/+9 V, I
S
= -10 mA
LEAKAGE CURRENTS
V
DD
= 12 V
Source Off Leakage, I
S
(Off)
±0.01
nA typ
V
S
= 1 V/10 V, V
D
= 10 V/1 V; Figure 22
±0.5
±1 ±5 nA
max
Drain Off Leakage, I
D
(Off)
±0.01
nA typ
V
S
= 1 V/10 V, V
D
= 10 V/1 V; Figure 22
±0.5
±1 ±5 nA
max
Channel On Leakage, I
D
, I
S
(On)
±0.04
nA typ
V
S
= V
D
= 1 V or 10 V, Figure 23
±1 ±2 ±5 nA
max
DIGITAL INPUTS
Input High Voltage, V
INH
2.0
V min
Input Low Voltage, V
INL
0.8
V max
Input Current, I
INL
or I
INH
0.001
µA typ
V
IN
= V
INL
or V
INH
±0.5 µA
max
Digital Input Capacitance, C
IN
5
pF typ
DYNAMIC CHARACTERISTICS
2
t
ON
50
ns typ
R
L
= 50 , C
L
= 35 pF
ns max
V
S
= 8 V; Figure 24
t
OFF
15
ns typ
R
L
= 50 , C
L
= 35 pF
ns max
V
S
= 8 V; Figure 24
Break-before-Make Time Delay, t
D
15
ns typ
R
L
= 50 , C
L
= 35 pF
1 ns
min
V
S1
= V
S2
= 8 V; Figure 25
Charge Injection
5
pC typ
V
S
= 0 V, R
S
= 0 , C
L
= 1 nF; Figure 26
pC typ
Off Isolation
75
dB typ
R
L
= 50 , C
L
= 5 pF, f = 1 MHz; Figure 27;
Channel-to-Channel Crosstalk
85
dB typ
R
L
= 50 , C
L
= 5 pF, f = 1 MHz; Figure 28
-3 dB Bandwidth
700
MHz typ
R
L
= 50 , C
L
= 5 pF; Figure 29
C
S
(Off)
2
pF typ
C
D
(Off)
2
pF typ
C
D
, C
S
(On)
5
pF typ
Preliminary Technical Data
ADG1236
Rev. PrD | Page 5 of 16
Parameters
25°C 85°C Y
Version
1
Unit Test
Conditions/Comments
POWER REQUIREMENTS
V
DD
= 13.2 V
I
DD
0.001
µA typ
Digital Inputs = 0 V or V
DD
5.0 µA
max
I
DD
150
µA typ
Digital Inputs = 5 V
300 µA
max
1
Temperature range for Y Version is -40°C to +125°C.
2
Guaranteed by design, not subject to production test.
ADG1236
Preliminary Technical Data
Rev. PrD | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Ratings
V
DD
to V
SS
38 V
V
DD
to GND
-0.3 V to +25 V
V
SS
to GND
+0.3 V to -25 V
Analog Inputs
1
V
SS
- 0.3 V to V
DD
+ 0.3 V
Digital Inputs
1
GND - 0.3 V to V
DD
+ 0.3 V or
30 mA, whichever occurs first
Peak Current, S or D
100 mA (pulsed at 1 ms, 10%
duty cycle max)
Continuous Current, S or D
30 mA
Operating Temperature Range
Industrial (B Version)
-40°C to +85°C
Automotive (Y Version)
-40°C to +125°C
Storage Temperature Range
-65°C to +150°C
Junction Temperature
150°C
16-Lead TSSOP,
JA
Thermal
Impedance
150.4°C/W
12-Lead LFCSP,
JA
Thermal
Impedance
TBD°C/W
Lead Temperature, Soldering
Vapor Phase (60 s)
215°C
Infrared (15 s)
220°C
1
Over voltages at IN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TRUTH TABLE FOR SWITCHES
Table 4.
IN
Switch A
Switch B
0 Off
On
1 On
Off
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Preliminary Technical Data
ADG1236
Rev. PrD | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
NC = NO CONNECT
IN1
S1A
D1
S1B
V
SS
GND
NC
NC
NC
NC
NC
V
DD
S2B
D2
S2A
IN2
ADG1236
04776-0-002
Figure 2.TSSOP Pin Configuration
PIN 1
INDICATOR
NC = NO CONNECT
1
D1
2
S1B
3
V
SS
9 V
DD
8 S2B
7 D2
4
G
N
D
5
I
N
2
6
S
2
A
1
2
S
1
A
1
1
I
N
1
1
0
N
C
TOP VIEW
(Not to Scale)
ADG1236
04776-0-003
Figure 3. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Function
1
11
IN1
Logic Control Input.
2
12
S1A
Source Terminal. Can be an input or output.
3
1
D1
Drain Terminal. Can be an input or output.
4
2
S1B
Source Terminal. Can be an input or output.
5 3 V
SS
Most Negative Power Supply Potential.
6
4
GND
Ground (0 V) Reference.
7, 8, 1416
10
NC
No Connect.
9
5
IN2
Logic Control Input.
10
6
S2A
Source Terminal. Can be an input or output.
11
7
D2
Drain Terminal. Can be an input or output.
12
8
S2B
Source Terminal. Can be an input or output.
13 9 V
DD
Most Positive Power Supply Potential.
ADG1236
Preliminary Technical Data
Rev. PrD | Page 8 of 16
TERMINOLOGY
I
DD
The positive supply current.
I
SS
The negative supply current.
V
D
(V
S
)
The analog voltage on Terminals D and S.
R
ON
The ohmic resistance between D and S.
R
FLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
I
S
(Off)
The source leakage current with the switch off.
I
D
(Off)
The drain leakage current with the switch off.
I
D
, I
S
(On)
The channel leakage current with the switch on.
V
INL
The maximum input voltage for Logic 0.
V
INH
The minimum input voltage for Logic 1.
I
INL
(I
INH
)
The input current of the digital input.
C
S
(Off)
The off switch source capacitance, measured with reference to
ground.
C
D
(Off)
The off switch drain capacitance, measured with reference to
ground.
C
D
, C
S
(On)
The on switch capacitance, measured with reference to ground.
C
IN
The digital input capacitance.
t
ON
The delay between applying the digital control input and the
output switching on. See Figure 24.
t
OFF
The delay between applying the digital control input and the
output switching off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
Preliminary Technical Data
ADG1236
Rev. PrD | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. On Resistance as a Function of V
D
(V
S
) for Single Supply
Figure 5, On Resistance as a Function of V
D
(V
S
) for Dual Supply
Figure 6. On Resistance as a Function of V
D
(V
S
) for Different Temperatures,
Single Supply
Figure 7. On Resistance as a Function of V
D
(V
S
) for Different Temperatures,
Single Supply
Figure 8, On Resistance as a Function of V
D
(V
S
) for Different Temperatures,
Dual Supply
Figure 9. Leakage Current as a Function of V
D
(V
S
)
ADG1236
Preliminary Technical Data
Rev. PrD | Page 10 of 16
Figure 10. Leakage Currents as a Function of V
D
(V
S
)
Figure 11. Leakage Current as a Function of V
D
(V
S
)
Figure 12. Leakage Currents as a Function of Temperature
Figure 13. Leakage Currents as a Function of Temperature
Figure 14. Supply Currents vs. Input Switching Frequency
Figure 15. Charge Injection vs. Source Voltage
Preliminary Technical Data
ADG1236
Rev. PrD | Page 11 of 16
Figure 16. t
ON
/t
OFF
Times vs. Temperature
Figure 17. Off Isolation vs. Frequency
Figure 18. Crosstalk vs. Frequency
Figure 19. On Response vs. Frequency
Figure 20. THD + N vs. Frequency
ADG1236
Preliminary Technical Data
Rev. PrD | Page 12 of 16
TEST CIRCUITS
I
DS
S
D
V
S
04776-0-020
V
S
D
V
S
A
A
V
D
I
S
(OFF)
I
D
(OFF)
04776-0-021
S
D
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
04776-0-022
Figure 21. Test Circuit 1--On Resistance
Figure 22. Test Circuit 2-- Off Resistance
Figure 23. Test Circuit 3--On Leakage
04776-
0-
023
IN
V
OUT
D
SA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SB
V
IN
V
S
0.1
µ
F
0.1
µ
F
R
L
50
50%
50%
90%
50%
50%
90%
t
ON
t
OFF
V
IN
V
OUT
V
IN
Figure 24. Test Circuit 4--Switching Times
04776-0-024
IN
V
OUT
D
SA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SB
V
IN
V
S
0.1
µ
F
0.1
µ
F
R
L
50
80%
t
BBM
t
BBM
V
OUT
V
IN
Figure 25. Test Circuit 5--Break-before-Make Time Delay
V
IN
(NORMALLY
CLOSED SWITCH)
V
OUT
V
IN
(NORMALLY
OPEN SWITCH)
OFF
V
OUT
ON
Q
INJ
= C
L
×
V
OUT
04776-0-025
IN
V
OUT
D
SA
V
DD
V
SS
V
DD
V
SS
GND
C
L
1nF
NC
SB
V
IN
V
S
0.1
µ
F
0.1
µ
F
Figure 26. Test Circuit 6--Charge Injection
Preliminary Technical Data
ADG1236
Rev. PrD | Page 13 of 16
V
OUT
50
NETWORK
ANALYZER
R
L
50
IN
V
IN
SA
D
V
S
V
DD
V
SS
0.1
µ
F
V
DD
0.1
µ
F
V
SS
GND
04776-0-026
50
NC
SB
OFF ISOLATION = 20 LOG
V
OUT
V
S
Figure 27. Test Circuit 7--Off Isolation
V
OUT
50
NETWORK
ANALYZER
R
L
50
IN
V
IN
SA
D
V
S
V
DD
V
SS
0.1
µ
F
V
DD
0.1
µ
F
V
SS
GND
04776-0-027
50
NC
SB
INSERTION LOSS = 20 LOG
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
Figure 28. Test Circuit 8--Channel-to-Channel Crosstalk
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
V
OUT
GND
SA
D
SB
V
OUT
NETWORK
ANALYZER
R
L
50
R
50
V
S
V
S
V
DD
V
SS
0.1
µ
F
V
DD
0.1
µ
F
V
SS
04776-0-028
IN
Figure 29. Test Circuit 9-- Bandwidth
V
OUT
R
S
AUDIO PRECISION
R
L
600
IN
V
IN
S
D
V
S
V p-p
V
DD
V
SS
0.1
µ
F
V
DD
0.1
µ
F
V
SS
GND
04776-0-029
Figure 30. Test Circuit 10--THD + Noise
ADG1236
Preliminary Technical Data
Rev. PrD | Page 14 of 16
OUTLINE DIMENSIONS
16
9
8
1
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 31. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in inches and (millimeters
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
1
0.50
BSC
0.60 MAX
PIN 1
INDICATOR
0.75
0.55
0.35
0.25 MIN
0.45
TOP
VIEW
12 MAX
0.80 MAX
0.65 TYP
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
*1.45
1.30 SQ
1.15
12
4
10
6
7
9
3
2.75
BSC SQ
3.00
BSC SQ
2
5
8
11
COPLANARITY
0.08
EXPOSED PAD
(BOTTOM VIEW)
SEATING
PLANE
Figure 32. 12-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG1236YRU
-40°C to +125°C
Thin Shrink Small Outline Package (TSSOP)
RU-16
ADG1236YCP
-40°C to +125°C
Lead Frame Chip Scale Package (LFCSP)
CP-12-1
Preliminary Technical Data
ADG1236
Rev. PrD | Page 15 of 16
NOTES
ADG1236
Preliminary Technical Data
Rev. PrD | Page 16 of 16
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04776011/04(PrD)
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