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REV. 0

AD9288

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

8-Bit, 40/80/100 MSPS

Dual A/D Converter

FUNCTIONAL BLOCK DIAGRAM

T/H

ADC

REF

T/H

ADC

OUTPUT REGISTER

TIMING

AD9288

D0

SELECT #1

SELECT #2

DATA FORMAT
SELECT

D0

ENC

REF

OUT

REF

ENC

GND

FEATURES
Dual 8-Bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC
Low Power: 90 mW at 100 MSPS per Channel
On-Chip Reference and Track/Holds
475 MHz Analog Bandwidth Each Channel
SNR = 47 dB @ 41 MHz
1 V p-p Analog Input Range Each Channel
Single +3.0 V Supply Operation (2.7 V3.6 V)
Standby Mode for Single Channel Operation
Twos Complement or Offset Binary Output Mode
Output Data Alignment Mode

APPLICATIONS
Battery Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
I and Q Communications

GENERAL DESCRIPTION

The AD9288 is a dual 8-bit monolithic sampling analog-to-
digital converter with on-chip track-and-hold circuits and is
optimized for low cost, low power, small size and ease of use.
The product operates at a 100 MSPS conversion rate with out-
standing dynamic performance over its full operating range.
Each channel can be operated independently.

The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full-performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.

The encode input is TTL/CMOS compatible and the 8-bit
digital outputs can be operated from +3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options are available to offer a combi-
nation of standby modes, digital data formats and digital data
timing schemes. In standby mode, the digital outputs are driven
to a high impedance state.

Fabricated on an advanced CMOS process, the AD9288 is avail-
able in a 48-lead surface mount plastic package (7

7 mm,

1.4 mm LQFP) specified over the industrial temperature range
(40

C to +85

C).

REV. 0

AD9288SPECIFICATIONS

Test

AD9288BST-100

AD9288BST-80

AD9288BST-40

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Units

RESOLUTION

Bits

DC ACCURACY

Differential Nonlinearity

+25

0.5

+1.25

0.5

+1.25

0.5

+1.25

LSB

Full

+1.50

LSB

Integral Nonlinearity

+25

0.50

+1.25

0.50

+1.25

0.50

+1.25

LSB

Full

+1.50

LSB

No Missing Codes

Full

Guaranteed

Gain Error

+25

2.5

% FS

Full

% FS

Gain Tempco

Full

ppm/

Gain Matching

+25

1.5

% FS

Voltage Matching

+25

ANALOG INPUT

Input Voltage Range

(With Respect to

AIN)

Full

512

mV p-p

Common-Mode Voltage

Full

200

Input Offset Voltage

+25

+35

Full

Reference Voltage

Full

1.2

1.25

1.3

1.2

1.25

1.3

1.2

1.25

1.3

Reference Tempco

Full

130

ppm/

Input Resistance

+25

Full

Input Capacitance

+25

Analog Bandwidth, Full Power

+25

475

MHz

SWITCHING PERFORMANCE

Maximum Conversion Rate

Full

100

MSPS

Minimum Conversion Rate

+25

MSPS

Encode Pulsewidth High (t

)

+25

4.3

1000

5.0

1000

8.0

1000

Encode Pulsewidth Low (t

)

+25

4.3

1000

5.0

1000

8.0

1000

Aperture Delay (t

)

+25

Aperture Uncertainty (Jitter)

+25

ps rms

Output Valid Time (t

)

Full

3.0

Output Propagation Delay (t

)

Full

4.5

DIGITAL INPUTS

Logic "1" Voltage

Full

2.0

Logic "0" Voltage

Full

0.8

Logic "1" Current

Full

Logic "0" Current

Full

Input Capacitance

+25

2.0

DIGITAL OUTPUTS

Logic "1" Voltage

Full

2.45

Logic "0" Voltage

Full

0.05

POWER SUPPLY

Power Dissipation

Full

180

218

171

207

156

189

Standby Dissipation

4, 5

Full

Power Supply Rejection Ratio

(PSRR)

+25

mV/V

DYNAMIC PERFORMANCE

Transient Response

+25

Overvoltage Recovery Time

+25

Signal-to-Noise Ratio (SNR)

(Without Harmonics)

= 10.3 MHz

+25

47.5

= 26 MHz

+25

47.5

= 41 MHz

+25

47.0

= 3.0 V; V

= 3.0 V, Differential Input; External reference unless otherwise noted.)

REV. 0

AD9288

Test

AD9288BST-100

AD9288BST-80

AD9288BST-40

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Units

DYNAMIC PERFORMANCE

(Continued)

Signal-to-Noise Ratio (SINAD) (With Harmonics)

= 10.3 MHz

+25

= 26 MHz

+25

= 41 MHz

+25

Effective Number of Bits

= 10.3 MHz

+25

7.5

7.0

7.5

Bits

= 26 MHz

+25

7.5

7.0

7.5

Bits

= 41 MHz

+25

7.0

7.5

Bits

2nd Harmonic Distortion

= 10.3 MHz

+25

dBc

= 26 MHz

+25

dBc

= 41 MHz

+25

dBc

3rd Harmonic Distortion

= 10.3 MHz

+25

dBc

= 26 MHz

+25

dBc

= 41 MHz

+25

dBc

Two-Tone Intermod Distortion (IMD)

= 10.3 MHz

+25

dBc

NOTES

Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).

and t

are measured from the 1.5 V level of the ENCODE input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to

exceed an ac load of 10 pF or a dc current of

Digital supply current based on V

= +3.0 V output drive with <10 pF loading under dynamic test conditions.

Power dissipation measured under the following conditions: f

= 100 MSPS, analog input is 0.7 dBFS, both channels in operation.

Standby dissipation calculated with encode clock in operation.

SNR/harmonics based on an analog input voltage of 0.7 dBFS referenced to a 1.024 V full-scale input range.

Specifications subject to change without notice.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9288 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V

Analog Inputs . . . . . . . . . . . . . . . . . . . . 0.5 V to V

+ 0.5 V

Digital Inputs . . . . . . . . . . . . . . . . . . . 0.5 V to V

+ 0.5 V

VREF IN . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V

+ 0.5 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . 55

C to +125

Storage Temperature . . . . . . . . . . . . . . . . . . 65

C to +150

Maximum Junction Temperature . . . . . . . . . . . . . . . +175

Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

Test Level
I

100% production tested.

100% production tested at +25

C and sample tested at

specified temperatures.

III Sample tested only.

IV Parameter is guaranteed by design and characterization

testing.

Parameter is a typical value only.

VI 100% production tested at +25

C; guaranteed by design

and characterization testing for industrial temperature
range; 100% production tested at temperature extremes for
military devices.

Table I. User Select Options

User Select Options

Standby Both Channels A and B.

Standby Channel B Only.

Normal Operation (Data Align Disabled).

Data align enabled (data from both channels avail-
able on rising edge of Clock A. Channel B data is
delayed a 1/2 clock cycle).

ORDERING GUIDE

Temperature

Package

Model

Ranges

Options

AD9288BST

-40, -80, -100

C to +85

ST-48*

AD9288/PCB

+25

Evaluation Board

*ST = Thin Plastic Quad Flatpack (1.4 mm thick, 7

7 mm: LQFP).

REV. 0

AD9288

PIN CONFIGURATION

13 14 15 16 17 18 19 20 21 22 23 24

ENC

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

GND

ENC

GND

(MSB) D7

GND

DFS

REF

OUT

REF

NC = NO CONNECT

GND

(MSB)

AD9288

GND

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

Description

1, 12, 16, 27, 29,
32, 34, 45

GND

Ground.

Analog Input for Channel A.

AINA

Analog Input for Channel A
(Complementary).

DFS

Data Format Select: (Offset
binary output available if set
low. Twos complement output
available if set high).

REF

Reference Voltage Input for
Channel A.

REF

OUT

Internal Reference Voltage.

REF

Reference Voltage Input for
Channel B.

User Select #1 (Refer to Table
I), Tied with Respect to V

User Select #2 (Refer to Table
I), Tied with Respect to V

AINB

Analog Input for Channel B
(Complementary).

Analog Input for Channel B.

13, 30, 31, 48

Analog Supply (3 V).

ENC

Clock Input for Channel B.

15, 28, 33, 46

Digital Supply (3 V).

1724

Digital Output for Channel B.

25, 26, 35, 36

Do Not Connect.

3744

Digital Output for Channel A.

ENC

Clock Input for Channel A.

Aperture Delay

The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the EN-
CODE pulse should be left in Logic "1" state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a "best straight line" deter-
mined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product; re-
ported in dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).

Worst Harmonic

The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.

DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

REV. 0

SAMPLE

10

20

30

40

50

60

70

80

90

ENCODE = 100MSPS
A

= 10.3MHz

SNR = 48.52dB
SINAD = 48.08dB
2ND HARMONIC = 62.54dBc
3RD HARMONIC = 63.56dBc

Figure 4. Spectrum: f

= 100 MSPS, f

= 10 MHz,

Single-Ended Input

SAMPLE

10

20

30

40

50

60

70

80

90

ENCODE = 100MSPS
A

= 41MHz

SNR = 47.87dB
SINAD = 46.27dB
2ND HARMONIC = 54.10dBc
3RD HARMONIC = 55.46dBc

Figure 5. Spectrum: f

= 100 MSPS, f

= 41 MHz,

Single-Ended Input

SAMPLE

10

20

30

40

50

60

70

80

90

ENCODE = 100MSPS
A

= 76MHz

SNR = 47.1dB
SINAD = 43.2dB
2ND HARMONIC = 52.2dBc
3RD HARMONIC = 51.5dBc

Figure 6. Spectrum: f

= 100 MSPS, f

= 76 MHz,

Single-Ended Input

MHz

72.00

68.00

64.00

60.00

56.00

52.00

48.00

44.00

40.00

ENCODE RATE = 100MSPS

2ND

3RD

Figure 7. Harmonic Distortion vs. A

Frequency

SAMPLE

10

20

30

40

50

60

70

80

90

ENCODE = 100MSPS
A

1 = 9.3MHz

2 = 10.3MHz

IMD = 60.0dBc

Figure 8. Two-Tone Intermodulation Distortion

MHz

50.00

48.00

46.00

44.00

42.00

40.00

38.00

36.00

ENCODE RATE = 100MSPS

SNR

SINAD

Figure 9. SINAD/SNR vs. A

Frequency

Typical Performance CharacteristicsAD9288

REV. 0

AD9288

MSPS

49.00

48.00

47.00

46.00

45.00

100

110

= 10.3MHz

SINAD

SNR

Figure 10. SINAD/SNR vs. Encode Rate

ENCODE HIGH PULSEWIDTH ns

50.00

46.00

42.00

38.00

30.00

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

= 10.3MHz

SINAD

34.00

SNR

Figure 11. SINAD/SNR vs. Encode Pulsewidth High

BANDWIDTH MHz

0.5

0.0

0.5

1.0

2.0

100

200

300

400

500

600

1.5

ENCODE RATE = 100MSPS

2.5

3.0

3.5

4.0

4.5

5.0

5.5

3dB

Figure 12. ADC Frequency Response: f

= 100 MSPS

MSPS

190

POWER mW

185

180

175

170

= 10.3MHz

165

160

155

150

145

140

100

Figure 13. Analog Power Dissipation vs. Encode Rate

TEMPERATURE C

48.0

47.5

47.0

46.5

46.0

40

45.5

45.0

44.5

44.0

43.5

SNR

SINAD

ENCODE RATE = 100MSPS
A

= 10.3MHz

Figure 14. SINAD/SNR vs. Temperature

TEMPERATURE C

0.6

% GAIN

0.4

0.2

40

0.4

0.6

0.8

1.0

ENCODE RATE = 100MSPS
A

= 10.3MHz

Figure 15. ADC Gain vs. Temperature (with External
+1.25 V Reference)

REV. 0

AD9288

APPLICATION NOTES

THEORY OF OPERATION

The AD9288 ADC architecture is a bit-per-stage pipeline-type
converter utilizing switch capacitor techniques. These stages
determine the 5 MSBs and drive a 3-bit flash. Each stage pro-
vides sufficient overlap and error correction allowing optimiza-
tion of comparator accuracy. The input buffers are differential
and both sets of inputs are internally biased. This allows the
most flexible use of ac or dc and differential or single-ended
input modes. The output staging block aligns the data, carries
out the error correction and feeds the data to output buffers.
The set of output buffers are powered from a separate supply,
allowing adjustment of the output voltage swing. There is no
discernible difference in performance between the two channels.

USING THE AD9288

Good high speed design practices must be followed when using
the AD9288. To obtain maximum benefit, decoupling capacitors
should be physically as close to the chip as possible, minimizing
trace and via inductance between chip pins and capacitor (0603
surface mount caps are used on the AD9288/PCB evaluation
board). It is recommended to place a 0.1

F capacitor at each

power-ground pin pair for high frequency decoupling, and in-
clude one 10

F capacitor for local low frequency decoupling.

The VREF IN pin should also be decoupled by a 0.1

F capaci-

tor. It is also recommended to use a split power plane and
contiguous ground plane (see evaluation board section). Data
output traces should be short (<1 inch), minimizing on-chip
noise at switching.

ENCODE Input

Any high speed A/D converter is extremely sensitive to the qual-
ity of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer. Any noise, distortion or timing
jitter on the clock will be combined with the desired signal at
the A/D output. For that reason, considerable care has been
taken in the design of the ENCODE input of the AD9288, and
the user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS compatible.

Digital Outputs

The digital outputs are TTL/CMOS compatible for lower
power consumption. During standby, the output buffers transi-
tion to a high impedance state. A data format selection option
supports either twos complement (set high) or offset binary
output (set low) formats.

Analog Input

The analog input to the AD9288 is a differential buffer. For
best dynamic performance, impedance at A

and

AIN should

match. Special care was taken in the design of the analog input
stage of the AD9288 to prevent damage and corruption of
data when the input is overdriven. The nominal input range is
1.024 V p-p centered at V

0.3.

Voltage Reference

A stable and accurate 1.25 V voltage reference is built into the
AD9288 (REF

OUT

). In normal operation, the internal reference

is used by strapping Pins 5 (REF

A) and 7 (REF

B) to Pin 6

(REF

OUT

). The input range can be adjusted by varying the

reference voltage applied to the AD9288. No appreciable degra-
dation in performance occurs when the reference is adjusted

5%. The full-scale range of the ADC tracks reference voltage,

which changes linearly.

Timing

The AD9288 provides latched data outputs, with four pipeline
delays. Data outputs are available one propagation delay (t

)

after the rising edge of the encode command (see Figures 1, 2
and 3). The length of the output data lines and loads placed on
them should be minimized to reduce transients within the
AD9288. These transients can detract from the converter's
dynamic performance.

The minimum guaranteed conversion rate of the AD9288 is
1 MSPS. At clock rates below 1 MSPS, dynamic performance
will degrade. Typical power-up recovery time after standby
mode is 15 clock cycles.

User Select Options

Two pins are available for a combination of operational modes.
These options allow the user to place both channels in standby,
excluding the reference, or just the B channel. Both modes place
the output buffers and clock inputs in high impedance states.

The other option allows the user to skew the B channel output
data by 1/2 a clock cycle. In other words, if two clocks are fed to
the AD9288 and are 180

out of phase, enabling the data align

will allow Channel B output data to be available at the rising
edge of Clock A. If the same encode clock is provided to both
channels and the data align pin is enabled, then output data
from Channel B will be 180

out of phase with respect to Chan-

nel A. If the same encode clock is provided to both channels
and the data align pin is disabled, then both outputs are deliv-
ered on the same rising edge of the clock.

EVALUATION BOARD

The AD9288 evaluation board offers an easy way to test the
AD9288. It provides a means to drive the analog inputs single-
endedly or differentially. The two encode clocks are easily
accessible at on-board SMB connectors J2, J7. These clocks are
buffered on the board to provide the clocks for an on-board
DAC and latches. The digital outputs and output clocks are
available at a standard 37-pin connector, P2. The board has
several different modes of operation, and is shipped in the fol-
lowing configuration:

· Single-Ended Analog Input
· Normal Operation Timing Mode
· Internal Voltage Reference

Power Connector

Power is supplied to the board via a detachable 6-pin power
strip, P1.

VREFA

Optional External Reference Input

(1.25 V/1

VREFB

Optional External Reference Input

(1.25 V/1

VDL

Supply for Support Logic and DAC (3 V/215 mA)

VDD

Supply for ADC Outputs

(3 V/15 mA)

Supply for ADC Analog

(3 V/30 mA)

Analog Inputs

The evaluation board accepts a 1 V analog input signal centered
at ground at each analog input. These can be single-ended sig-
nals using SMB connectors J5 (channel A) and J1 (Channel B).
In this mode use jumpers E4E5 and E6E7. (E1E2 and E9
E10 jumpers should be lifted.)

Differential analog inputs use SMB connectors J4 and J6. Input
is 1 V centered at ground. The single-ended input is converted

REV. 0

AD9288

to differential by transformers T1, T2--allowing the ADC perfor-
mance for differential inputs to be measured using a single-
ended source. In this mode use jumpers E1E2, E3E4, E7E8
and E9E10. (E4E5 and E6E7 jumpers should be lifted.)

Each analog input is terminated on the board with 50

ground. Each input is ac-coupled on the board through a 0.1

capacitor to an on-chip resistor divider that provides dc bias.
Note that the inverting analog inputs are terminated on the
board with 25

(optimized for single-ended operation). When

driving the board differentially these resistors can be changed to
50

to provide balanced inputs.

Encode

The encode clock for channel A uses SMB connector J7. Chan-
nel B encode is at SMB connector J2. Each clock input is termi-
nated on the board with 50

to ground. The input clocks are

fed directly to the ADC and to buffers U5, U6 which drive the
DAC and latches. The clock inputs are TTL compatible, but
should be limited to a maximum of V

Voltage Reference

The AD9288 has an internal 1.25 V voltage reference. An ex-
ternal reference for each channel may be employed instead. The
evaluation board is configured for the internal reference (use
jumpers E18E41 and E17E19. To use external references,
connect to VREFA and VREFB pins on the power connector
P1 and use jumpers E20E18 and E21E19.

Normal Operation Mode

In this mode both converters are clocked by the same encode
clock; latency is four clock cycles (see timing diagram). Signal
S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is
set at jumpers E22E29 and E26E23.

Data Align Mode

In this mode channel B output is delayed an additional 1/2 cycle.
Signal S1 (Pin 8) and signal S2 (Pin 9) are both held high. This
is set at jumpers E22E29 and E26E28.

Data Format Select

Data Format Select sets the output data format that the ADC
outputs. Setting DFS (Pin 4) low at E30E27 sets the output
format to be offset binary; setting DFS high at E30E25 sets
the output to be twos complement.

Data Outputs

The ADC digital outputs are latched on the board by two 574s,
the latch outputs are available at the 37-pin connector at Pins
2229 (Channel A) and Pins 3037 (Channel B). A latch out-
put clock (data ready) is available at Pin 2 or 21 on the output
connector. The data ready signal can be aligned with clock A
input by connecting E31E32 or aligned with clock B input by
connecting E31E33.

Ch1

2.00V

CH2

2.00V

M 10.0ns CH4

40mV

PIN 2 (CLOCK)

PIN 22 (DATA)

Figure 24. Data Output and Clock at 37-Pin Connector

DAC Outputs

Each channel is reconstructed by an on-board dual channel
DAC, an AD9763. This DAC is intended to assist in debug--it
should not be used to measure the performance of the ADC. It
is a current output DAC with on-board 50

termination resis-

tors. Figure 25 is representative of the DAC output with a full-
scale analog input. The scope setting was low bandwidth, 50

termination.

Ch1

500mV

M 50.0ns

CH1

380mV

Figure 25. AD9763 Reconstruction DAC Output

Troubleshooting

If the board does not seem to be working correctly, try the
following:
·

Verify power at IC pins.

Check that all jumpers are in the correct position for the

desired mode of operation.

Verify VREF is at 1.25 V

Try running encode clock and analog inputs at low speeds

(10 MSPS/1 MHz) and monitor 574 outputs, DAC outputs,
and ADC outputs for toggling.

The AD9288 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warran-
ties, express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.

REV. 0

AD9288

Figure 26 . Dual Evaluation Board Schematic

REF

2345

GND

C10

0.1

GND

SINGLE-ENDED

GND

E30

E25

E27

VREFA

VREFB

E24

E29

E22

GND

E23

E28

E26

GND

E18

E17

E19

E21

E20

C24

0.1

C27

0.1

GND

DIFFERENTIAL

GND

E10

DIFFERENTIAL

GND

T11T

GND

C12

0.1

SINGLE-ENDED

GND

C11

0.1

GND

0.1

ENC

GND

0.1

GND

0.1

GND

0.1

GND

CLKCONB

GND

74LCX86

GND

E16

E13

E14

CLKDACB

GND

E11

E15

E12

CLKLATB

GND

C13

0.1

ENC

GND

R15

GND

ENCODE B

GND

0.1

GND

0.1

ENC

GND

C15

0.1

GND

MSB

E43

E42

E40

CLKLATA

CLKLATB

GND

C14

0.1

GND

LSB

CLKLATA

E31

E32

E33

CLKCONA

CLKCONB

GND

C37DRPF

OUT_EN

GND

CLOCK

74ACQ574

OUT_EN

GND

CLOCK

C16

C17

C18

C19

C26

GND

VREFB

VREFA

GND

CLKCONA

GND

74LCX86

GND

E36

E35

E34

CLKDACA

GND

E38

E39

E37

CLKLATA

GND

VDL

GND

C25

0.1

ENC

GND

R16

R11

GND

ENCODE A

GND

ENC

GND1

2COMP

REF

OUT

REF

GND2

ENC

GND3

GND7

GND6

GND5

GND4

AD9288

MODE

AVDD

FSADJ1

REFIO

FSADJ2

ACOM

SLEEP

AD9763

DB9P1

DB8P1

DB7P1

DB6P1

DB5P1

DB4P1

DB3P1

DB2P1

DB1P1

DB0P1

NC1

NC2

NC3

DCOM1

DVDD1

WRT1/IQWRT

CLK1/IQCLK

CLK2/IQRESET

WRT2/IQSEL

DCOM2

DVDD2

DB9P2

DB8P2

NC7

NC6

NC5

NC4

DB0P2

DB1P2

DB2P2

DB3P2

DB4P2

DB5P2

DB6P2

DB7P2

R10 50

GND

R8 2k

GND

R12

GND

DAC OUTPUT A

C21 0.1

GND

R9 2k

GND

R13 50

GND

R14

GND

DAC OUTPUT B

GND

D0A

D1A

D2A

D3A

D4A

D5A

D7B

D6B

D5B

D4B

D3B

D2B

D1B

D0B

GND

D6A

D7A

GND

C22

0.1

CLKDACB

CLKDACA

GND

C23

0.1

GND

E41

C20

0.1

GND

Part Number AD9288