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Differential Input, Dual 1 MSPS,
12-Bit, 3-Channel SAR ADC
Preliminary Technical Data
AD7265
FEATURES
Dual 12-bit, 3-channel ADC
Fast throughput rate: 1 MSPS
Specified for V
DD
of 2.7 V to 5.25 V
Low power: 7 mW max at 1 MSPS with 3 V supplies
16.5 mW max at 1 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
On-chip reference: 2.5 V
40°C to +125°C operation
Flexible power/throughput rate management
Simultaneous conversion/read
No pipeline delays
High speed serial interface SPI®/QSPITM/MICROWIRETM/DSP
compatible
Shutdown mode: 1 µA max
32-lead LFCSP and TQFP packages
GENERAL DESCRIPTION
The AD7265 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 1 MSPS. The
device contains two ADCs, each preceded by a 3-channel multi-
plexer, and a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 10 MHz.
The conversion process and data acquisition are controlled using
standard control inputs, allowing easy interfacing to microproces-
sors or DSPs. The input signal is sampled on the falling edge of CS;
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. There are no pipelined delays
associated with the part.
The AD7265 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 5 V supplies and a
1 MSPS throughput rate, the part consumes ? mA maximum. The
part also offers flexible power/throughput rate management when
operating in sleep mode.
The analog input range for the part can be selected to be a 0 V to
V
REF
range or a 2V
REF
range with either straight binary or twos
complement output coding. The AD7265 has an on-chip 2.5 V
reference that can be overdriven if an external reference is pre-
ferred. This external reference range is 100 mV to 2.5 V. The
AD7265 is available in 32-lead lead frame chip scale (LFCSP) and
thin flat quad (TQFP) lead package.
FUNCTIONAL BLOCK DIAGRAM
OUTPUT
DRIVERS
AGND
DGND
V
B1
VA1
+5
AVdd
DVdd
REF SELECT
DcapA
DcapB
DOUTA
SCLK
DOUTB
AD7265
T/H
OUTPUT
DRIVERS
CONTROL
LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
VA2
MUX
V
B2
MUX
VDRIVE
RANGE
AGND
REF
BUF
BUF
VA3
VA4
V
B3
V
B4
DGND
AGND
VA5
VA6
V
B5
V
B6
DIFF/SE
A0
A1
A2
Figure 1
PRODUCT HIGHLIGHTS
1.
The AD7265 features two complete ADC functions that allow
simultaneous sampling and conversion of two channels. Each
ADC has 2 analog inputs, 3 fully differential pairs, or 6 single-
ended channels as programmed. The conversion result of both
channels is available simultaneously on separate data lines, or
in succession on one data line if only one serial port is
available.
2.
High Throughput with Low Power Consumption
The AD7265 offers a 1 MSPS throughput rate with ? mW
maximum power consumption when operating at 3 V.
3.
Flexible Power/Throughput Rate Management
The conversion rate is determined by the serial clock, allowing
power consumption to be reduced as conversion time is re-
duced through an SCLK frequency increase. Power efficiency
can be maximized at lower throughput rates if the part enters
sleep between conversions.
4.
No Pipeline Delay
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a CS
input and once off conversion control.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
Rev. PrA
AD7265
Preliminary Technical Data
TABLE OF CONTENTS
AD7265--Specifications.................................................................. 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Functional Descriptions.......................... 6
Terminology ...................................................................................... 8
Theory of Operation ...................................................................... 10
Circuit Information.................................................................... 10
Converter Operation.................................................................. 10
Analog Input ............................................................................... 11
Output Coding............................................................................ 11
Transfer Functions ..................................................................... 12
Digital Inputs .............................................................................. 12
V
DRIVE
............................................................................................ 12
Modes of Operation ....................................................................... 13
Normal Mode.............................................................................. 13
Partial Power-Down Mode ....................................................... 13
Full Power-Down Mode ............................................................ 14
Outline Dimensions ....................................................................... 15
Ordering Guide............................................................................... 16
REVISION HISTORY
Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 16
Preliminary Technical Data
AD7265
AD7265--SPECIFICATIONS
1
Table 1. T
A
= T
MIN
to T
MAX
, V
DD
= 2.7 V to 5.25 V, f
SCLK
= 16 MHz, f
S
= 1 MSPS, V
DRIVE
= 2.7 V to 5.25 V; Reference = 2.5 V ± 1%,
unless otherwise noted
Parameter Specification
Unit
Test
Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion Ratio (SINAD)
2
70 dB
min
f
IN
= 100 kHz sine wave
Total Harmonic Distortion (THD)
2
75 dB
max
f
IN
= 100 kHz sine wave
Spurious Free Dynamic Range (SFDR)
2
76 dB
max
f
IN
= 100 kHz sine wave
Intermodulation Distortion (IMD)
2
Second Order Terms
88
dB typ
Third Order Terms
88
dB typ
Channel to Channel Isolation
88
dB typ
SAMPLE AND HOLD
Aperture Delay
3
10
ns
max
Aperture Jitter
3
50
ps
typ
Aperture Delay Matching
3
200
ps
max
Full Power Bandwidth
20
MHz typ
@ 3 dB
2.5
MHz typ
@0.1 dB
DC ACCURACY
Resolution 12
Bits
Integral Nonlinearity
2
±1
LSB max
±0.5 LSB typ; differential configuration
±1.5
LSB max
±0.5 LSB typ; single-ended configuration
Differential Nonlinearity
2
±0.95
LSB max
Guaranteed no missed codes to 12 bits
0 V to V
REF
Input Range
Straight binary output coding
Offset Error
±3
LSB max
Offset Error Match
±0.5
LSB typ
Gain Error
±2
LSB max
Gain Error Match
±0.6
LSB typ
0 V to 2 × V
REF
Input Range
Twos complement output coding
Positive Gain Error
±2
LSB max
Zero Code Error
±3
LSB max
Zero Code Error Match
±1
LSB typ
Negative Gain Error
±1
LSB max
ANALOG INPUT
Input Voltage Ranges
0 V to V
REF
V
RANGE pin low upon CS falling edge
0 V to 2 x V
REF
V
RANGE pin high upon CS falling edge
DC Leakage Current
±500
nA max
T
A
= 40°C to +85°C
±1
µA max
85°C < T
A
125°C
Input Capactiance
30
pF typ
When in track
10
pF typ
When in hold
REFERENCE INPUT/OUTPUT
Reference Output Voltage
4
2.49/2.51
V min/V max
Reference Input Voltage Range
0.1/2.5
V min/V max
See Typical Performance plots
DC Leakage Current
±30
µA max
V
REF
pin
±160
µA
max
D
CAP
A, D
CAP
B pins
Input Capactiance
20
pF typ
V
REF
Output Impedance
5
25
typ
Reference Temperature Coefficient
25
ppm/°C max
10
ppm/°C typ
LOGIC INPUTS
Input High Voltage, V
INH
2.8
V
min
Input Low Voltage, V
INL
0.4
V
max
Input Current, I
IN
±1
µA max
Typically 15 nA, V
IN
= 0 V or V
DRIVE
Input Capacitance, C
IN
3
10 pF
max
Rev. PrA | Page 3 of 16
AD7265
Preliminary Technical Data
Parameter Specification
Unit
Test
Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DRIVE
0.2
V min
Output Low Voltage, V
OL
0.4
V
max
Floating State Leakage Current
±1
µA max
Floating State Output Capacitance
3
10 pF
max
Output Coding
Straight (Natural) Binary
SGL/DIFF = 1 with 0 V to V
REF
range selected
Twos
Complement
SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × V
REF
range
CONVERSION RATE
Conversion Time
14
SCLK Cycles
TBD ns with SCLK = 16 MHz
Track/Hold Acquisition Time
3
100 ns
max
Throughput Rate
TBD
MSPS max
POWER REQUIREMENTS
V
DD
2.7/5.25
V min/V max
V
DRIVE
2.7/5.25
V min/V max
I
DD
6
Digital I/Ps = 0 V or V
DRIVE
Normal Mode (Static)
TBD
mA max
Operational, f
s
= 1 MSPS
3.3
mA max
V
DD
= 5 V
2.3
mA
max
V
DD
= 3 V
Partial Power-Down Mode
TBD
mA max
f
s
= 200 kSPS
Partial Power-Down Mode
TBD
µA max
Static
Full Power-Down Mode
TBD
µA max
Power Dissipation
6
Normal Mode (Operational)
16.5
mW max
V
DD
= 5 V
Partial Power-Down (Static)
TBD
mW max
Full Power-Down (Static)
TBD
mW max
NOTES
1
Temperature ranges as follows: -40°C to +125°C
2
See
section.
Terminology
3
Sample tested during initial release to ensure compliance.
4
Relates to Pins D
CAP
A or D
CAP
B.
5
See Reference section for D
CAP
A, D
CAP
B output impedances.
6
See Power Versus Throughput Rate section.
TIMING SPECIFICATIONS
Table 2. AV
DD
= DV
DD
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, T
A
= T
MAX
to T
MIN
, unless otherwise noted
Parameter Limit
at
T
MIN
, T
MAX
Unit Description
f
SCLK
10 kHz
min
20
MHz
max
t
CONVERT
14 × t
SCLK
ns
max
t
SCLK
= 1/f
SCLK
700
ns
max
f
SCLK
= 20 MHz,
t
QUIET
35
ns
max
Minimum time between end of serial read and next falling edge of CS
t
2
10 ns
min
CS to SCLK setup time
t
3
TBD ns
max
Delay from CS until D
OUT
A and D
OUT
B are three-state disabled
t
4
TBD
ns max
Data access time after SCLK falling edge.
t
5
0.4t
SCLK
ns min
SCLK low pulse width
t
6
0.4t
SCLK
ns min
SCLK high pulse width
t
7
TBD
ns min
SCLK to data valid hold time
t
8
25 ns
max
CS rising edge to D
OUT
A, D
OUT
B, high impedance
t
9
TBD
ns min
SCLK falling edge to D
OUT
A, D
OUT
B, high impedance
TBD
ns max
SCLK falling edge to D
OUT
A, D
OUT
B, high impedance
Rev. PrA | Page 4 of 16
Preliminary Technical Data
AD7265
ABSOLUTE MAXIMUM RATINGS
Table 3. AD7265 Stress Ratings
Parameter Rating
V
DD
to AGND
0.3 V to +7 V
DV
DD
to DGND
0.3 V to +7 V
V
DRIVE
to DGND
0.3 V to DV
DD
V
DRIVE
to AGND
0.3 V to AV
DD
AV
DD
to DV
DD
0.3 V to +0.3 V
AGND to DGND
0.3 V to +0.3 V
Analog Input Voltage to AGND
0.3 V to AV
DD
+0.3 V
Digital Input Voltage to DGND
0.3 V to +7 V
Digital Output Voltage to GND
0.3 V to V
DRIVE
+0.3 V
V
REF
to AGND
0.3 V to AV
DD
+0.3 V
Input Current to Any Pin Except
Supplies
1
±10 mA
Operating Temperature Range
40°C to +125°C
Storage Temperature Range
65°C to +150°C
Junction Temperature
150°C
LFCSP Package
JA
Thermal Impedance
108.2°C/W
JC
Thermal Impedance
32.71°C/W
Lead Temperature, Soldering
TBD°C/W
Reflow Temperature (10- 30 sec)
TBD°C
ESD TBD
1
Transient currents of up to 100 mA will not cause SCR latch up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 5 of 16
AD7265
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
AD7265
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
B3
VA1
SCLK
V
DRIVE
A2
+5
AVDD
SGL/
,1..
AGND
DGND
AGND
REF SELECT
RANGE
A0
PIN 1
IDENTIFIER
DGND
V
A3
V
A4
V
A5
V
A6
V
B6
V
B5
V
B4
VA2
VB2
VB1
DCAPB
DCAPA
AGND
DV
DD
D
OUT
A
D
OUT
B
A1
Figure 2. AD7265 Pin Configuration
Table 4. AD7265 Pin Function Descriptions
Pin No.
Mnemonic
Description
4, 20
D
CAP
A,
D
CAP
B
Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective ADC.. The
on-chip reference can be taken from these pins and applied externally to the rest of a system. The range of the
external reference is dependent on the analog input range selected. See the Reference Configuration Options
section.
712 V
A1
V
A6
Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
1813 V
B1
V
B6
Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
27 SCLK Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7265. This clock
is also used as the clock source for the conversion process.
5, 6, 19
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not
be more than 0.3 V apart, even on a transient basis.
32 DV
DD
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7265. The DV
DD
and AV
DD
voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a
transient basis. This supply should be decoupled to DGND.
31 V
DRIVE
Logic power supply input. The voltage supplied at this pin determines at what voltage the interface will operate.
This pin should be decoupled to DGND. The voltage at this pin may be different to that at AV
DD
and DV
DD
but
should never exceed either by more than 0.3 V.
1, 29
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
3 AV
DD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The
AV
DD
and DV
DD
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis. This supply should be decoupled to AGND.
26
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265
and frames the serial data transfer.
30, 28
D
OUT
A,
D
OUT
B
Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are clocked out on the
falling edge of the SCLK input and 14 SCLKs are required to access the data. The data appears on both pins
simultaneously from the simultaneous conversions of both ADCs. The data stream consists of one leading zero
followed by one identification bit, followed by the 12 bits of conversion data. The data is provided MSB first. If CS
is held low for 16 SCLK cycles rather than 14, then two trailing zeros will appear after the 12 bits of data. If CS is
held low for a further 16 SCLK cycles after this on either D
OUT
A or D
OUT
B, the data from the other ADC follows on
the D
OUT
pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on
either D
OUT
A or D
OUT
B alone using only one serial port. See the Serial Interface section.
Rev. PrA | Page 6 of 16
Preliminary Technical Data
AD7265
Pin No.
Mnemonic
Description
21 RANGE
Analog Input Range Selection. Logic input. The polarity on this pin will determine what input range the analog
input channels will have. On the falling edge of CS , the polarity of this pin is checked to determine the analog
input range of the next conversion. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin
is tied to a logic high when CS goes low, the analog input range is 2 × V
REF
.
2523 A0A2
Multiplexer Select. Logic inputs. Thess inputs are used to select the pair of channels to be converted
simultaneously, i.e., Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC, and so on. The pair of
channels selected may be two single ended channels or two differential pairs. The logic states of these pins are
checked upon the falling edge of CS, and the multiplexer is set up for the next conversion. See Table 6 for
multiplexer address decoding.
22
SGL/DIFF
Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic
low selects differential operation while a logic high selects single ended operation.
2 REF
SELECT
Internal/External reference Selection. Logic Input. If this pin is tied to GND, the on-chip 2.5 V reference is used as
the reference source for both ADC A and ADC B. In addition, Pins D
CAP
A and D
CAP
B must be tied to decoupling
capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7265
through the D
CAP
A and/or D
CAP
B pins.
Rev. PrA | Page 7 of 16
AD7265
Preliminary Technical Data
TERMINOLOGY
Differential Nonlinearity
Track-and-Hold Acquisition Time
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all non-fundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Offset Error
This applies to Straight Binary output coding. It is the deviation
of the first code transition (00 . . . 000) to (00 . . . 001) from the
ideal, i.e., AGND + 1 LSB.
Offset Error Match
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
This is the worst case difference in Offset Error between any of
the twelve channels.
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Gain Error
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7265 it is defined as:
This applies to Straight Binary output coding. It is the deviation
of the last code transition (111 . . . 110) to (111 . . . 111) from the
ideal (i.e., VREF 1 LSB) after the offset error has been adjusted
out.
1
2
6
2
5
2
4
2
3
2
2
log
20
)
(
V
V
V
V
V
V
dB
THD
+
+
+
+
=
Gain Error Match
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonics.
This is the difference in Gain Error between the two channels.
Zero Code Error
Peak Harmonic or Spurious Noise
This applies when using twos complement output coding in
particular with the 2 x V
REF
input range as V
REF
to +V
REF
biased
about the V
REF
point. It is the deviation of the midscale
transition (all 1s to all 0s) from the ideal V
IN
voltage, i.e., V
REF
- 1
LSB.
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will
be a noise peak.
Zero Code Error Match
This refers to the difference in Zero Code Error between the
two channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale (2 x V
REF
), 455kHz sine wave signal to all unselected input
channels and determining how much that signal is attenuated in
the selected channel with a 10 kHz signal (0 V to V
REF
). The
figure given is the worst-case across all twelve channels for the
AD7265.
Positive Gain Error
This applies when using twos complement output coding in
particular with the 2 x V
REF
input range as V
REF
to +V
REF
biased
about the V
REF
point. It is the deviation of the last code
transition (011...110) to (011...111) from the ideal (i.e., + V
REF
-
1 LSB) after the Zero Code Error has been adjusted out.
Rev. PrA | Page 8 of 16
Preliminary Technical Data
AD7265
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa fb), while the
third order terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa
2fb).
The AD7265 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
PSR (Power Supply Rejection)
Variations in power supply will affect the full-scale transition
but not the converter's linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value. See Typical
Performance Curves.
Rev. PrA | Page 9 of 16
AD7265
Preliminary Technical Data
THEORY OF OPERATION
04603-P
r
A
-
003
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
IN+
V
IN
V
REF
CIRCUIT INFORMATION
The AD7265 is a fast, micropower, dual 12-bit, single supply,
A/D converter that operates from a 2.7 V to 5.25 V supply.
When operated from either a 5 V or 3V supply, the AD7265 is
capable of throughput rates of 1 MSPS.
The AD7265 contains two on-chip differential track-and-hold
amplifiers, two successive approximation A/D converters, and a
serial interface with two separate data output pins, and is
housed in a 32-lead LFCSP package, which offers the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part but also
provides the clock source for each successive approximation
ADC. The analog input range for the part can be selected to be a
0 V to V
REF
input or a 2 × V
REF
input with the analog inputs
configured as either single ended or differential. The AD7265
has an on-chip 2.5 V reference that can be overdriven if an
external reference is preferred.
Figure 3. ADC Acquisition Phase
When the ADC starts a conversion (Figure 4), SW3 opens and
SW1 and SW2 move to position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the V
IN+
and V
IN
pins must be matched;
otherwise, the two inputs will have different settling times,
resulting in errors.
The AD7265 also features power-down options to allow power
saving between conversions. The power-down feature is
implemented across the standard serial interface, as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7265 has two successive approximation analog-to-
digital converters, each based around two capacitive DACs.
Figure 3 and Figure 4 show simplified schematics of one of
these ADCs in acquisition and conversion phase, respectively.
The ADC is comprised of control logic, a SAR, and two
capacitive DACs. In Figure 3 (the acquisition phase), SW3, is
closed, SW1 and SW2 are in position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
04603-P
r
A
-
004
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
IN+
V
IN
V
REF
Figure 4. ADC Conversion Phase
Rev. PrA | Page 10 of 16
Preliminary Technical Data
AD7265
ANALOG INPUT
The channels to be converted on simultaneously are selected via
the multiplexer address inputs A0 to A2. The logic states of
these pins are also checked upon the falling edge of CS and the
channels are chosen for the next conversion. The selected input
channels are decoded as shown in Table 6.
The analog inputs of the AD7265 may be configured as single
ended or true differential via the SGL/DIFF logic pin, as shown
in Figure 5. On the falling edge of CS, point A, the logic level of
the SGL/DIFF pin is checked to determine the configuration of
the analog input channels for the next conversion. If this pin is
tied to a logic low, the analog input channels to each on-chip
ADC are set up as three true differential pairs. If this pin is at a
logic high when CS goes low, the analog input channels to each
on-chip ADC are set up as six single-ended analog inputs. In
Figure 5 at point A, the SGL/DIFF pin is at a logic high so the
analog inputs are configured as single-ended for the next
conversion, i.e. sampling point B. At point B, the logic level of
the SGL/DIFF pin has changed to low; there fore, the analog
inputs are configured as differential for the next conversion
after this one, even though this current conversion is on single
ended configured inputs.
The analog input range of the AD7265 can be selected as 0 V to
V
REF
or 0 V to 2 × V
REF
via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/DIFF pin by
checking the logic state of the RANGE pin upon the falling edge
of CS. The analog input range is set up for the next conversion.
If this pin is tied to a logic low upon the falling edge of CS, the
analog input range for the next conversion is 0 V to V
REF
. If this
pin is tied to a logic high upon the falling edge of CS, the analog
input range for the next conversion is 0 V to 2 × V
REF
.
OUTPUT CODING
The AD7265 output coding is set to either twos complement or
straight binary depending on which analog input configuration
is selected for a conversion. Table 5 shows which output coding
scheme is used for each possible analog input configuration.
04603-P
r
A
-
005
A
CS
SCLK
SGL/DIFF
1
14
1
14
B
Table 5 AD7265 Output Coding
SGL/DIFF
Range Output
Coding
DIFF
0 V to V
REF
Twos Complement
DIFF
0 V to 2 × V
REF
Twos
Complement
SGL
0 V to V
REF
Straight
Binary
SGL
0 V to 2 × V
REF
Twos
Complement
PSUEDO DIFF
0 V to V
REF
Straight
Binary
PSUEDO DIFF
0 V to 2 × V
REF
Straight
Binary
Figure 5. Selecting Differential or Single Ended Configuration
Table 6. Analog Input Type and Channel Selection
ADC
A
ADC
B
SGL/DIFF
A2 A1 A0 V
IN+
V
IN
V
IN+
V
IN
Comment
1
0 0 0 V
A1
AGND
V
B1
AGND Single
Ended
1
0 0 1 V
A2
AGND
V
B2
AGND Single
Ended
1
0 1 0 V
A3
AGND V
B3
AGND Single
Ended
1
0 1 1 V
A4
AGND V
B4
AGND Single
Ended
1
1 0 0 V
A5
AGND
V
B5
AGND Single
Ended
1
1 0 1 V
A6
AGND
V
B6
AGND Single
Ended
0
0 0 0 V
A1
V
A2
V
B1
V
B2
Fully
Differential
0
0 0 1 V
A1
V
A2
V
B1
V
B2
Pseudodifferential
0
0 1 0 V
A3
V
A4
V
B3
V
B4
Fully
Differential
0
0 1 1 V
A3
V
A4
V
B3
V
B4
Pseudodifferential
0
1 0 0 V
A5
V
A6
V
B5
V
B6
Fully
Differential
0
1 0 1 V
A5
V
A6
V
B5
V
B6
Pseudodifferential
Rev. PrA | Page 11 of 16
AD7265
Preliminary Technical Data
TRANSFER FUNCTIONS
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is V
REF
/4096.
The ideal transfer characteristic for the AD7265 when straight
binary coding is output is shown in Figure 6, and the ideal
transfer characteristic for the AD7265 when twos complement
coding is output is shown in Figure 7.
04603-P
r
A
-
006
000...000
111...111
1LSB = V
REF
/4096
1LSB
V
REF
1LSB
ANALOG INPUT
ADC CODE
0V
000...001
000...010
111...110
111...000
011...111
Figure 6. Straight Binary Transfer Characteristic
04603-P
r
A
-
007
100...000
011...111
1LSB = 2
×
V
REF
/4096
+V
REF
1 LSB
V
REF
+ 1LSB V
REF
1LSB
ANALOG INPUT
ADC CODE
100...001
100...010
011...110
000...001
000...000
111...111
Figure 7. Twos Complement Transfer Characteristic with V
REF
±V
REF
Input
Range
DIGITAL INPUTS
The digital inputs applied to the AD7265 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
V
DD
+ 0.3 V limit as on the analog inputs. See the Absolute
Maximum Ratings. Another advantage of SCLK, RANGE,
A0A2, and CS not being restricted by the V
DD
+ 0.3 V limit is
that power supply sequencing issues are avoided. If one of these
digital inputs is applied before V
DD
, there is no risk of latch-up,
as there would be on the analog inputs if a signal greater than
0.3 V were applied prior to V
DD
.
V
DRIVE
The AD7265 also has the V
DRIVE
feature, which controls the
voltage at which the serial interface operates. V
DRIVE
allows the
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7265 was operated with a V
DD
of 5 V, the
V
DRIVE
pin could be powered from a 3 V supply, allowing a large
dynamic range with low voltage digital processors. For example,
the AD7265 could be used with the 2 × V
REF
input range, with a
V
DD
of 5 V while still being able to interface to 3 V digital parts.
Rev. PrA | Page 12 of 16
Preliminary Technical Data
AD7265
MODES OF OPERATION
The mode of operation of the AD7265 is selected by controlling
the (logic) state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. The point at which CS
is pulled high after the conversion has been initiated determines
which power-down mode, if any, the device enters. Similarly, if
already in a power-down mode, CS can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing application requirements.
accessed on the same DOUT line, as shown in Figure TBD (see
the Serial Interface section). The identification bit provided
prior to each conversion result identifies which on-board ADC
the following result is from. Once 32 SCLK cycles have elapsed,
the DOUT line returns to three-state on the 32
nd
SCLK falling
edge. If CS is brought high prior to this, the DOUT line returns
to three-state at that point. Thus, CS may idle low after 32 SCLK
cycles until it is brought high again sometime prior to the next
conversion (effectively idling CS low), if so desired, since the
bus still returns to three-state upon completion of the dual
result read.
Once a data transfer is complete and D
OUT
A and D
OUT
B have
returned to three-state, another conversion can be initiated after
the quiet time, t
QUIET
, has elapsed by bringing CS low again.
NORMAL MODE
This mode is intended for fastest throughput rate performance
since the user does not have to worry about any power-up times
with the AD7265 remaining fully powered all the time. Figure 8
shows the general diagram of the operation of the AD7265 in
this mode.
PARTIAL POWER-DOWN MODE
04603-P
r
A
-
008
1
10
14
LEADING ZERO, I.D. BIT + CONVERSION RESULT
CS
SCLK
D
OUT
A
D
OUT
B
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7265 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffer.
To enter partial power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the 10
th
falling edge of SCLK, as
shown in Figure 9. Once CS has been brought high in this
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of CS is
terminated, and D
OUT
A and D
OUT
B go back into three-state. If
CS is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the CS line.
Figure 8. Normal Mode Operation
The conversion is initiated on the falling edge of CS, as
described in the Serial Interface section. To ensure that the part
remains fully powered up at all times, CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS. If CS is brought high any time after the 10
th
SCLK falling
edge but before the 14
th
SCLK falling edge, the part remains
powered up but the conversion is terminated and D
OUT
A and
D
OUT
B go back into three-state. Fourteen serial clock cycles are
required to complete the conversion and access the conversion
result. The DOUT line does not return to three-state after 14
SCLK cycles have elapsed, but instead does so when CS is
brought high again. If CS is left low for another 2 SCLK cycles
(e.g. if only a 16 SCLK burst is available), two trailing zeros are
clocked out after the data. If CS is left low for a further 16 SCLK
cycles again, the result from the other ADC on board is also
04603-P
r
A
-
009
1
2
10
14
CS
SCLK
TRI-STATE
D
OUT
A
D
OUT
B
Figure 9. Entering Partial Power-Down Mode
Rev. PrA | Page 13 of 16
AD7265
Preliminary Technical Data
To exit this mode of operation and power up the AD7265 again,
a dummy conversion is performed. On the falling edge of CS,
the device begins to power up, and continues to power up as
long as CS is held low until after the falling edge of the 10
th
SCLK. The device is fully powered up after approximately 1 µs
has elapsed, and valid data results from the next conversion, as
shown in Figure 10. If CS is brought high before the second
falling edge of SCLK, the AD7265 again goes into partial power-
down. This avoids accidental power-up due to glitches on the
CS line. Although the device may begin to power up on the
falling edge of CS, it powers down again on the rising edge of
CS. If the AD7265 is already in partial power-down mode and
CS is brought high between the second and 10
th
falling edges of
SCLK, the device enters full power-down mode.
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substan-
tially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by a
long period of inactivity and thus power-down. When the
AD7265 is in full power-down, all analog circuitry is powered
down. Full power-down is entered in a similar way as partial
power-down, except the timing sequence shown in Figure 9
must be executed twice. The conversion process must be
interrupted in a similar fashion by bringing CS high anywhere
after the second falling edge of SCLK and before the 10
th
falling
edge of SCLK. The device enters partial power-down at this
point. To reach full power-down, the next conversion cycle must
be interrupted in the same way, as shown in Figure TBD. Once
CS has been brought high in this window of SCLKs, the part
powers down completely.
Note that it is not necessary to complete the 14 SCLKs once CS
has been brought high to enter a power-down mode.
To exit full power-down and power the AD7265 up again, a
dummy conversion is performed, as when powering up from
partial power-down. On the falling edge of CS, the device
begins to power up and continues to power up as long as CS is
held low until after the falling edge of the 10
th
SCLK. The
power-up time required must elapse before a conversion can be
initiated, as shown in Figure TBD. See the Power-Up Times
section for the power-up times associated with the AD7265.
04603-P
r
A
-
010
1
A
10
14
1
14
SCLK
INVALID DATA
VALID DATA
D
OUT
A
D
OUT
B
CS
T
POWER-UP
THE PART BEGINS
TO POWER-UP
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION
Figure 10. Exiting Partial Power-Down Mode
Rev. PrA | Page 14 of 16
Preliminary Technical Data
AD7265
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80
SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
BOTTOM
VIEW
0.50
0.40
0.30
3.50 REF
0.50
BSC
3.25
3.10 SQ
2.95
0.60 MAX
0.60 MAX
0.25 MIN
TOP
VIEW
PIN 1
INDICATOR
PIN 1
INDICATOR
5.00
BSC SQ
4.75
BSC SQ
Figure 11. 32-Lead Frame Chip Scale Package [LFCSP
(CP-32)
Dimensions shown in millimeters
TOP VIEW
(PINS DOWN)
1
24
17
25
32
8
9
16
0.45
0.37
0.30
0.80
BSC
7.00
SQ
9.00 SQ
1.05
1.00
0.95
SEATING
PLANE
1.20
MAX
0.15
0.05
7°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MS-026ABA
Figure 12. 32-Lead Thin Flat Quad Package [TQFP]
(SU-32)
Dimensions shown in millimeters
Rev. PrA | Page 15 of 16
AD7265
Preliminary Technical Data
Rev. PrA | Page 16 of 16
ORDERING GUIDE
AD7265 Products
Temperature Package
Package Description
Package Outline
AD7265ACP
40°C to +125°C
Lead Frame Chip Scale Package
CP-32
AD7265BCP
40°C to +125°C
Lead Frame Chip Scale Package
CP-32
AD7265ASU
40°C to +125°C
Thin Quad Flat Package
SU-32
AD7265BSU
40°C to +125°C
Thin Quad Flat Package
SU-32
EVAL-AD7265CB
1
Evaluation
Board
EVAL-CONTROL BRD2
2
Controller
Board
1
This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes.
2
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete
evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7265CB, the EVAL-CONTROL BRD2, and a 12V transformer must be ordered. See relevant Evaluation
Board Technical note for more information.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR0467401/04(PrA)
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