A-Data
ADD8616A8A
Revision History
Revision 1 ( Dec. 2001 )
1.Fister release.
Revision 2 ( Apr. 2002 )
1. Changed module current specification.
2. Add Performance range.
3.
Changed AC Characteristics.
4.
Changed typo size on module PCB in package dimensions.
Rev 2 April, 2002
1
A-Data
ADD8616A8A
Double Data Rate SDRAM
4M x 16 Bit x 4 Banks
General Description
The ADD8616A8A are four-bank Double Data
Rate(DDR) Synchronous DRAMs organized as
4,194,304 words x 16 bits x 4 banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Data outputs occur at both rising edges of CK and
/CK.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Features
·
2.5V for VDDQ power supply
·
SSTL_2 interface
·
MRS Cycle with address key programs
-CAS Latency (2, 2.5)
-Burst Length (2,4 &8)
-Burst Type (sequential & Interleave)
·
4 banks operation
·
Differential clock input (CK, /CK) operation
·
Double data rate interface
·
Auto & Self refresh
·
8192 refresh cycle
·
DQM for masking
·
Package:66-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
Interface
Package
VDD8608A8A-75BA 133Mhz(7.5ns
/CL=2)
ADD8616A8A-75B 133Mhz(7.5ns
/CL=2.5)
SSTL_2 400mil
66pin
TSOPII
Pin Assignment
1
2
3
4
5
6
7
8
9
V
D D
D Q0
V
D D Q
N C
D Q 1
V
S S Q
N C
D Q 2
V
D D Q
6
4
3
62
61
60
5 9
5 8
V
S S
D Q 7
V
S SQ
N C
D Q 6
V
D D Q
N C
D Q 5
V
S SQ
10
11
12
13
14
15
16
1
18
19
20
N C
D Q 3
V
S S Q
N C
NC
V
D D Q
N C
W E
C A S
R A S
C S
N C
D Q 4
V
D D Q
N C
N C
V
S S Q
D Q S
N C
V
D M
A 6
A 5
A4
V
S S
R E F
V
S S
21
22
23
24
25
26
27
28
29
N C
B A 0
B A 1
A10/AP
A 0
A 1
A 2
V
D D
30
31
32
33
34
35
3 6
37
3 8
39
NC
A 3
V D D
N C
40
41
42
43
CK
CK
CKE
NC
NC
A11
A9
A 8
A7
5 7
56
55
54
5 3
52
5 1
5 0
4 9
4 8
47
46
4 5
44
6
65
6
6
7
N C
66-pin plastic TSOP II 400 mil
Rev 2 April, 2002
2
A-Data
ADD8616A8A
Pin Description
PIN NAME
FUNCTION
CK, /CK
System Clock
Differential clock input.
CKE Clock
Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CK, CKE and DQ
A0~A12
Address
Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A9
BS0~BS1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ15 Data
Data inputs / outputs are multiplexed on the same pins.
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
/CAS
Column Address Strobe
Latches Column addresses on the positive edge of the CLK with /CAS
low
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output Power/Ground Power supply for output buffers.
VREF
Reference Voltage
Reference voltage for inputs for SSTL interface.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
CK
CKE
Clock
Generator
Address
/CS
/RAS
/CAS
/WE
DQM
Mode
Register
Command Decoder
Control Logic
Row Decoder
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank0
Bank2
Bank3
Bank1
Amplifier
Column Decoder
Data Control Circuit
Data Latch
DQ0~DQn
DQS
Rev 2 April, 2002
3
A-Data
ADD8616A8A
Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
out
-0.3
~
VDDQ+0.3
V
Voltage on VDD supply relative to Vss
V
DD
, V
DDQ
-0.3
~
3.6
V
Storage temperature
T
STG
-55 ~ +150
Power dissipation
P
D
1
W
Short circuit current
I
OUT
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Min
Max
Unit
Note
Supply voltage
V
DD
2.3 2.7 V
Supply voltage
V
DDQ
2.3 V
DD
1
Input logic high voltage
V
IH
V
REF
+0.15
V
DDQ
+0.3 V
Input logic low voltage
V
IL
-0.3
V
REF
-0.15
V 2
Differential Clock DC Input voltage
V
ICK
-0.3
V
DDQ
+0.3
V
Input Differential CLK&/CLK voltage
V
ID
0.7
V
DDQ
+0.6 V
Input leakage current
I
IL
-5 5
uA 3
Output leakage current
I
OL
-5 5 uA 4
Reference Voltage
V
REF
0.49*
V
DDQ
0.51* V
DDQ
V
Termination Voltage
V
TT
V
REF
-0.04
V
REF
+0.04
V 5
Note : 1. V
DDQ
must not exceed the level of V
DDQ
.
2.V
IL
(min)=-0.9V with a pulse width 5ns .
3.Any
input
0V
V
IN
3.6V, all other pins are not under test = 0V.
4.Dout is disabled, 0V V
OUT
2.7V.
5.
V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of
the same. Peak to peak noise on V
REF
may not exceed ±2% of the DC value.
Rev 2 April, 2002
4
A-Data
ADD8616A8A
AC Test Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Value
Unit
Note
AC input high level voltage
V
IH
VREF+0.31
V
AC input low level voltage
V
IL
VREF-0.31
V
Input Reference Voltage
VREF
0.5xV
DDQ
V
Termination Voltage
VTT
0.5xV
DDQ
V
Input Signal Peak to Peak Swing
V
SWING
1.0
V
Input Difference Voltage. CLK and /CLK Inputs
V
ID
1.5 V
Capacitance
TA=25, f-=1Mhz
Parameter Pin
Symbol
Min
Max
Unit
CK, /CK
Cl1
2
3.0
pF
Input capacitance
A0~A12,BS0,BS1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Cl2 2
3.0
pF
Data input / output capacitance DQM
CI/O
4
5
pF
Output load circuit
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
Rev 2 April, 2002
5
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