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QUIQLGV380SDC-75LPR REV A0. 2156-V380SDC-75LPR REV A0. Standard Package. 14. Order QuickLogic V380SDC-75LPR REV A0 (2156-V380SDC-75LPR REV A0-ND) at DigiKey. Check stock and pricing, view product specifications, and order online.
- Quicklogic
- 2156-V380SDC-75LPR REV A0-ND
- HIGH PERFORMANCE SDRAM CONTROLL
- QuickLogic
The V380SDC is also fully compatible with the EPC family of PCI bridges available from V3 Semiconductor. The V380SDC supports a total SDRAM memory subsystem size to 2 Gbytes. Standard memory devices from 16 Mbit to 256 Mbit are supported; 16-, 32-bit and 64-bit accesses are allowed. Four single-bank or two dualbank industry standard 168-pin PC ...
- Memory
- V380SDC
- High Performance Sdram Controller
- Memory Control
Order QuickLogic V380SDC-75LPR REV A0 (2156-V380SDC-75LPR REV A0-ND) at DigiKey. Check stock and pricing, view product specifications, and order online.
- Quicklogic
- 2156-V380SDC-75LPR REV A0-ND
- HIGH PERFORMANCE SDRAM CONTROLL
- QuickLogic
The processor interface on the V380SDC implements the bus protocol of many popular RISC CPUs (AM29030/40, PowerPC 401 Gx, IDT 79RC32364, i960 Cx/Hx/Jx/Rx/Vx, M68040, 68K/ColdFire, PowerPC 750/60x). The V380SDC is also fully compatible with the EPC family of PCI bridges available from V3 Semiconductor. The V380SDC
Find the best pricing for Rochester Electronics V380SDC-75LPR REV A0 by comparing bulk discounts from 1 distributors. Octopart is the world's source for V380SDC-75LPR REV A0 availability, pricing, and technical specs and other electronic parts.
- Rochester Electronics
- $20 - $21.66
- 2
Find the best pricing for QuickLogic V380SDC-75LPR REV A0 by comparing bulk discounts from 1 distributors. Octopart is the world's source for V380SDC-75LPR REV A0 availability, pricing, and technical specs and other electronic parts.
The V380SDC enables system designers to replace many lower integration support components with a single, high-integration device. This saves design time, board space, and manufacturing cost. The V380SDC from V3 Semiconductor provides the necessary (Enhanced) SDRAM access protocol and bus timing resources to work with the latest (E)SDRAM devices.
