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IDT72V3690 ⎯⎯⎯ 32,768 x 36 ••• Up to 166 MHz Operation of the Clocks ••• User selectable Asynchronous read and/or write ports (PBGA Only) ••• User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out
IDT72V3690 - 32,768 x 36 • Up to 166 MHz Operation of the Clocks • User selectable Asynchronous read and/or write ports (PBGA Only) • User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out • Pin to Pin compatible to the higher density of ...
3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36, IDT72V3690 Datasheet, IDT72V3690 circuit, IDT72V3690 data sheet : RENESAS, alldatasheet, Datasheet, Datasheet search site for Electronic Components and Semiconductors, integrated circuits, diodes, triacs and other semiconductors.
IDT72V3690 ⎯ 32,768 x 36 • Up to 166 MHz Operation of the Clocks • User selectable Asynchronous read and/or write ports (PBGA Only) • User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out
Features. Pin to Pin compatible to the higher density IDT72V361x0. Up to 166 MHz Operation of the Clocks. User selectable Asynchronous read and/or write ports (PBGA Only) User selectable input and output port bus-sizing. 5V input tolerant. Auto power down minimizes standby power consumption. Master Reset clears entire FIFO.
Download IDT72V3690 PDF File. Description. 3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, ...
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