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LH7A404 32-Bit System-on-Chip 2 Product data sheet NXP Semiconductors Figure 1. LH7A404 Block Diagram LH7A404-1 OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and RESET CONTROL VECTORED INTERRUPT CONTROLLER REAL TIME CLOCK 14.7456 MHz 32.768 kHz SYNCHRONOUS MEMORY CONTROLLER PCMCIA/CF CONTROLLER COLOR LCD CONTROLLER 80KB SRAM LCD AHB BUS ...
- 981KB
- 75
FEATURES. • 32-bit ARM9TDMI™ RISC Core. – 16 kB Cache: 8 kB Instruction and 8 kB Data Cache. – MMU (Windows CE™ Enabled) – Up to 266 MHz; See Table 1 for speed options. • 80 kB On-Chip Static RAM. • Vectored In terrupt Contr oller. • External Bus Interface. – U p to 133 MHz; See Table 1 for bus speed options.
FEATURES. • ARM922T™ Core: – 32-bit ARM9TDMI ™ RISC Core (200 MHz) – 16KB Cache: 8KB Instru ction Cache and 8KB. Data Cache. – MMU (Windows CE™ Enabled) • 80KB On-Chip Me mory. • Vectored In terrupt Contr oller. • External Bus Interface. – 100 MHz. – Asynchronous SRAM/ROM/Flash. – Synchronous DRAM/Flash. – PCMCIA. – CompactFlash.
32-Bit System-on-Chip LH7A404 Data Sheet Version 1.0 7 C14 SCKE3 Clock Enable 3 for Synchronous Memory Depends on MEDCHG LOW 12 mA I/O 4 D14 SCLK Synchronous Memory Clock LOW No Change 24 mA I/O 2, 4 A13 nBLE0 Byte Lane Enable 0 HIGH HIGH 12 mA I/O 4 U9 nBLE1 Byte Lane Enable 1 HIGH HIGH 12 mA O Y7 nBLE2 Byte Lane Enable 2 HIGH HIGH 12 mA O
FEATURES. ARM922TTM Core: 32-bit ARM9TDMITM RISC Core (200 MHz) 16KB Cache: 8KB Instruction Cache and 8KB Data Cache. MMU (WinCETM Enabled) 80KB On-Chip Memory. Vectored Interrupt Controller. External Bus Interface. 100 MHz. Asynchronous SRAM / ROM / Flash. Synchronous DRAM / Flash. PCMCIA. CompactFlash. Clock and Power Management.
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Content Revisions LH7A404 User’s Guide iv Ver. 1.3 — 27 August 2007 NXP Semiconductors 3-30-06 13-2 Section 13.1.1.2 Added section. 13-7 Section 13.2.2.4 Corrected reset value of COUNT2 Register.
View LH7A404 Prod Brief by Sharp Microelectronics datasheet for technical specifications, dimensions and more at DigiKey.
