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The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power. Figure 1. DSP56311 Block Diagram YAB XAB PAB YDB XDB PDB GDB MODB/IRQB MODC/IRQC 13 MODD/IRQD ...
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With 300 million multiply accumulates per second (MMACS) operating performance, the 24-bit DSP56311 DSP offers excellent performance density characteristic of DSP56300 devices—maximizing the number of channels processed in a very small space while providing low power dissipation and excellent thermal performance at a competitive price.
With 150 MHz of core processing With 384K bytes, or 128K 24-bit power, the DSP56311 is ideal for words, of integrated SRAM, the multi-channel voice and data applica- DSP56311 can eliminate the need for tions such as digital cellular base sta- external memory devices which may tions and Internet Protocol (IP) tele- reduce performance and phony.
Product Brief. DSP56311PB. Rev. 3, 2/2005. DSP56311. 24-Bit Digital Signal Processor. 3. 16. 6 6 Memory Expansion Area. The DSP56311 is intended. Program. for applications requiring a. SCI. Triple Timer. HI08. ESSI. EFCOP. RAM. 32 K × 24 bits or. 31 K × 24 bits and Instruction. X Data RAM. 48 K × 24 bits. Y Data RAM. 48 K × 24 bits.
View DSP56311 by NXP USA Inc. datasheet for technical specifications, dimensions and more at DigiKey.
DSP56311. 24-BIT DIGITAL SIGNAL PROCESSOR. The Motorola DSP56311, a member of the DSP56300 core family of programmable Digital Signal Processors (DSPs), supports wireless infrastructure applications with general filtering operations.
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DSP56311 Product details. The DSP56311 is intended for applications requiring a large amount of internal memory, such as networking and wireless infrastructure applications. The onboard EFCOP can accelerate general filtering applications, such as echo-cancellation applications, correlation, and general-purpose convolution based algorithms.
