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ARM946E-S Technical Reference Manual - ARM architecture family ... processor ™ ...
- 1.6 System controller
- 1.10 Cache lock-down
- 2.3 Status registers
- 2.4 Exception types
- 2.5 Conditional execution
- 2.6 Four classes of instructions
- 2.10 Block transfers
- 2.13 Coprocessor
- Operation
- 3.7 Debug features
- 4.3 Everything you need
- 4.4 Current support
The system controller oversees the interaction between the Instruction Cache, Instruction RAM, Data Cache, Data RAM, and the Bus Interface Unit. It controls internal arbitration between the blocks and stalls appropriate blocks when required. The system controller arbitrates between instruction and data access to schedule single or simultaneous requ...
Cache lock-down is provided to allow critical code sequences to be locked into the cache to ensure predictability for real-time code. The cache replacement algorithm can be selected by the operating system as either pseudo random or round-robin. Both caches are four-way set-associative. Lock down operates on a per-set basis
All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: four ALU flags (Negative, Zero, Carry, and Overflow), two interrupt disable bits (o ne for each type of interrupt), a bit to indicate ARM or Thumb execution, and five bits to encode the cu...
ARM9E-S supports five types of exception, and a privileged processing mode for each type. The types of exceptions are: fast interrupt (FIQ) normal interrupt (IRQ) memory aborts (used to implement memory protection or virtual memory) attempted execution of an undefined instruction software interrupts (SWIs).
All ARM instructions (with the exception of BLX) are conditionally executed. Instructions optionally update the four condition code flags (Negative, Zero, Carry, and Overflow) according to their result. Subsequent instructions are conditionally executed according to the status of flags. Fifteen conditions are implemented.
The ARM and Thumb instruction sets can be divided into four broad classes of instruction: data processing instructions load and store instructions branch instructions coprocessor instructions.
Load and store multiple instructions perform a block transfer of any number of the general purpose registers to or from memory. Four addressing modes are provided: pre-increment addressing post-increment addressing pre-decrement addressing post-decrement addressing. The base address is specified by a register value (which can be optionally updated ...
There are three types of coprocessor instructions: coprocessor data processing - instructions are used to invoke a coprocessor specific internal operation. coprocessor register transf er - instructions allow a coprocessor value (word or double word) to be transferred to or from an ARM register. coprocessor data transfer - instructions transfer copr...
Mnemonic Operation MOV QADD QSUB RSB CMP TST AND EOR MUL SMULL UMULL CLZ MRS B BL BX LDR LDRH LDRB LDRSH LDMIA SWP Move Saturated add Saturated subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Unsigned Long Multiply Count Leading Zeroes Move From Status Register Branch Branch and Link Branch and Ex...
The ARM9E-S processor core also incorporates a sophisticated debug unit to allow both software tasks and external debug hardware to perform hardware and software breakpoint, single stepping, register and memory access. This functionality is made available to software as a coprocessor and is accessible from hardware via the JTAG port. Full-speed, re...
ARM provides a wide range of products and services to support its processor families, including software development tools, development boards, models, applications software, training, and consulting services. The ARM Architecture today enjoys broad third party support. The ARM9 Thumb Family processors’ strong software compatibility with existing A...
Support for the ARM Architecture today includes: Software toolkits available from ARM - ARM Developer Suite (ADS), Cygnus/GNU, Microtec, Greenhills, JavaSoft, MetaWare, and Windriver allowing software development in C, C++, Java, FORTRAN, Pascal, Ada, and assembler.
ARM 946E-S Technical Reference Manual ... the ...
The ARM946E-S is a Harvard architecture cached processor that provides a complete high-performance processor subsystem, including: An ARM9E-S RISC integer CPU core featuring: ARMv5TE 32-bit instruction set that has improved ARM/Thumb code interworking and an enhanced multiplier designed for improved DSP performance.
Technical reference manual. ARM ARM946E-S Technical Reference Manual. 1. 2. Table Of Contents. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31.
ARM9 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use. [1] . The ARM9 core family consists of ARM9TDMI, ARM940T, ARM9E-S, ARM966E-S, ARM920T, ARM922T, ARM946E-S, ARM9EJ-S, ARM926EJ-S, ARM968E-S, ARM996HS.
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