Did you mean: PLL 103-53
The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured ...
PLL103-53 (PhaseLink). Electronic component documentation (datasheet) «PLL103-53» (Clock Distribution), manufacturer PhaseLink. Download datasheet file: ...
The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured ...
Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay. Skew between any ...
PDF PLL103-53 Data sheet ( Hoja de datos ) ; Número de pieza, PLL103-53 ; Descripción, DDR SDRAM Buffer ; Fabricantes, PhaseLink Corporation ; Logotipo, PhaseLink ...
Datasheet Archive is an online archive of electronic component datasheets and application notes for PhaseLink Parts starting with 'P'.
Preliminary PLL103-53 DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS FEATURES Generates 30-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR ...
Searched Keyword: 3-TO-8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCH 0.5 HARD DOCUMENT GEN2, PAIR, SWITCH . Part #: PLL103-53. Datasheet: 148Kb/7P.
PLL103-53 : Standard Clock Buffer (SDRAM And DDR) , (14x2 DDR) or (12 Sdram + 8x2 DDR), 66-170MHz in. VT83201 : 3.3V Low Phase Noise Vcxo And PLL Clock ...
Preliminary PLL103-53 DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS FEATURES Generates 30-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR ...