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PA7140JNI-25 Pin-compatible Superset of Ep910, More Logic Than Epm7032/ Mach110 . Features. Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches to 72 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried High-Speed Commercial
PA7140JNI-25: Description: 25ns programmable electrically erasable logic array: Manufacturer: Package: PLCC: Pins: 44: Oper. temp.:-40 to 85: Datasheet: PDF (466K). Click here to download *) The PA7140 is a member of the Programmable Electrically Erasable Logic (PEELTM) Array family based on ICT's CMOS EEPROM technology.
Full datasheet PA7140JNI-25 manufactirer Diodes, SPLD SPLDs (Simple PLD) Archive 1.687.043 components : Datasheets Cross-reference Online-stock: ChipFind:
pa7140f-20, pa7140f-25, pa7140fi-25, pa7140j-20, pa7140j-25, pa7140ji-25, pa7140jn-20, pa7140jn-25, pa7140jni-25, pa7140p-20, pa7140p-25, pa7140pi-25 Search datasheet on manufacturer web-site © 2006 — 2023 ChipFind Ltd.
PA7140 Datasheet : Programmable Electrically Erasable Logic Array, PA7140 PDF International-Cmos, PA7140 Datasheet PDF, Pinouts, Data Sheet, Equivalent, Schematic ...
PA7140JNI-25: 25ns programmable electrically erasable logic array in 44-pin PLCC package. Operational temperature range from -40 ° C to 85 ° C. Datasheet *) PA7140P-20: 20ns programmable electrically erasable logic array in 44-pin PDIP package. Operational temperature range from 0 ° C to 70 ° C. Datasheet *) PA7140P-25
Integrated Circuit Technology Corp. PA7140JI-25 Datasheet. If it is not shown correctly, Click here to open the file on a separate window 0-C D-L M-R S-Z
